EP0231202A1

EP0231202A1 - Circuit arrangement to align the pcm groups entering a communication branch point with another

Info

Publication number: EP0231202A1
Application number: EP86903362A
Authority: EP
Inventors: Francesco Marchelli; Piercarlo Sarto
Original assignee: Italtel SpA; Italtel Societa Italiana Telecomunicazioni SpA
Current assignee: Italtel SpA
Priority date: 1985-07-31
Filing date: 1986-05-29
Publication date: 1987-08-12
Also published as: IT8521782A0; WO1987001006A1; GR861642B; YU105586A; IT1200701B

Abstract

L'agencement de circuit est conçu pour gérer la transmission bidirectionnelle de canaux MIC et inclut une section de transmissison (ST), une section de réception (SR) et une unité génératrice de temps de base (TBG). La section de transmission (ST) code les signaux MIC selon les règles prévues par le code Manchester II, entraîne une infraction auxdites réglementations chaque fois qu'elle reçoit une impulsion de synchronisation (S1) de ladite unité génératrice de temps de base (TBG). La section de réception (SR) décode les signaux reçus, extrait le signal de synchronisation (Sr) et sort les signaux MIC avec un retard qui est fonction de la relation temporelle entre le signal de synchronisation (Sr) extrait du flot de données et le signal de synchronisation (S1) sorti par l'unité génératrice de temps de base (TBG).The circuit arrangement is designed to handle bidirectional transmission of PCM channels and includes a transmitting section (ST), a receiving section (SR) and a base timing generating unit (TBG). The transmission section (ST) encodes the PCM signals according to the rules provided by the Manchester II code, infringes said regulations each time it receives a synchronization pulse (S1) from said base time generating unit (TBG) . The receiving section (SR) decodes the received signals, extracts the synchronization signal (Sr) and outputs the PCM signals with a delay which is a function of the temporal relationship between the synchronization signal (Sr) extracted from the data stream and the synchronization signal (S1) output by the basic time generating unit (TBG).

Description

- 1 -

Circuit arrangement to align the PCM groups entering a coπ-munication branch point with another.

The present invention relates to a circuit arrangement to align the PCM groups entering a communications branch point (such as a switching matrix) and having a lag that varies from group to group, one another.

Henceforth, in the following description, the invention will be described with reference to a PCM switching network as described in _{the us} Patent No. 4.536.870, however it can be advantageously used in all those cases in which a technical problem exists of how to align the PCM groups entering any communications branch point, with one another.

The switching network mentioned above includes three switching stages henceforth respectively indicated with the terms input switching stages, intermediate switching stages and output switching stages.

In practical implementation of the switching network, the input switching stages - and/or the output switching stages - can be placed at a distance, from the intermediate switching stages, that for some stages will amount to only a few meters, whilst for others will amount to a hundred odd meters. Therefore the PCM groups entering the intermediate switching stages are affected by lags that differ from group 5 to group according to the distance at which the input switching stages are placed.

It must be borne in mind that before' switching of the digital words allocated in the temporal channels of the said - 2 -

PCM groups is carried out, the said PCM groups must be aligned so that, at any one moment, the digital words allocated in the nth temporal channel of all the groups are present on the matrix's input.

Evaluation of the entity of the lag is usually carried out by using a synchronizing pulse output by a timing unit.

According to some known solutions the aligning operations referred to above are carried out through means designed to be used in the presence of a lag condition of the PCM signals output from the input switching stages compared to the synchronizing pulse output by the said timing unit.

However, the said known solutions are not suitable for carrying out the said aligning operations in the presence of a lead condition of the PCM signals compared to the reference pulse (synchronizing signal). This latter condition can occur when the distance between the intermediate switching stages is minimum and consequently the signal transit times are determined by the lags introduced by their respective logical circuits.

The purpose of the present invention is to make a circuit arrangement to align the PCM groups entering a communications branch point both in the presence of the said lag condition as well as in the presence of the said lead condition.

Therefore the object of the present invention is a circuit arrangement comprising a transmitting section and a 3 -

receiving section, connected to the ends of a connection line, as well as a basic time generating unit which outputs a clock signal/ having a frequency equal to that of the PCM signals to be aligned on its first output, and a synchronizing pulse with a predetermined repetition rate on its second output.

The transmitting section includes the presence of means to encode the PCM signals according to a biphase type law and also to introduce violations of the said law each time they receive a synchronizing pulse from the said basic time generation unit.

The receiving section, on the other hand, includes the presence in combination of the following characteristic elements:

- decoding means to output the PCM signals on their first output after having carried out conversion of the same from the said biphase type law into the law of origin, a clock signal extracted from the received signals on their second output, and a synchronizing pulse on their third output each time they pick up the presence of the said violations in the biphase type law;

- an elastic memory having K + 2 memory cells, K being an iιi_eger number expressing the degree of elasticity of the memory;

- a write counter designed to enable writing of the cells of the said elastic memory starting from a predetermined cell, having K + 2 counting steps and also having its counting and enabling inputs respectively connected to the second and third output of the decoding means; - 4 -

- a read counter designed to enable reading of the cells of the said elastic memory starting from a predetermined cell, again having K + 2 counting . _st_epS ^anα also having its counting and enabling _input-;^' respectively connected to the first and second output of the basic time generating unit.

In other words the alignment of the PCM groups entering a communications branch point is carried out by determining the simultaneous reading of a specific bit of the frame _Qf all the PCM groups in the instant defined by the synchronizing pulse output by the basic time generating unit. Instead, the writing operation is carried out in an instant that differs from group to group and is defined by the synchronizing pulse extracted from the received data; ie: the writing operation can have a lead on the reading operation by a number of bits that varies from 1 to K + 1.

Further characteristics of the invention will be made clear by the description that follows which refers to an example of . embodimerit and to ^■* the ^' attached ^** figures in • which:

- fig. 1 shows some elements of a communications branch point to which the circuit arrangement according to the invention is associated;

- fig. 2 shows an embodiment according to the invention of the circuit arrangement RIL of fig. 1 in detail;

- fig. 3 shows waveforms relating to fig. 2. - 5 -

In fig. 1 some switching stages that are part of a digital signal switching network are illustrated. In particular, SC-P1 , _{• 11} SC-Pri indicates ri peripheral switching stages (input/output stages), whilst SC-I1, SC-In indicates the same number of intermediate switching stages to which the peripheral switching stages are connected by means of bidirectional lines L. Each line L can carry out bidirectional transmission of a PCM group and has a length that can in actual fact vary from a few meters to about one hundred meters.

RIL indicates the circuit arrangement as claimed in the present invention which, in a preferred form of embodiment is configured in order to manage four bidirectional PCM groups, even if circuits suitable to manage only one PCM group are illustrated in fig. 2. Each RIL unit therefore is able to align four bidirectional PCM groups with one another by introducing a lag, for each group, that is determined by using the synchronizing pulses S output by their respective stage timing unit UTS. In particular, each UTS unit receives a clock signal CK with a frequency for example equal to 2 MHz from a network timing unit UTR.

This signal has discontinuities (for example the cancelling of a pulse) with a repetition rate equal to 4 KHz the picking up of which makes it possible to extract the synchronizing pulses S. The CK signal is in fact input into each stage timing unit UTS which then extracts the said synchronizing signal S and also outputs a signal CK- with a frequency equal to 8 MHz. - 6 -

Each RIL circuit receives the S signal and the CK_ signal o from its respective UTS unit and includes - for each PCM group - a transmitting section and a receiving section. Presuming that the RIL circuit in question is associated to a peripheral switching stage, the transmitting section encodes the PCM signals according to a biphase type code (for example Manchester II) and introduces a violation of the encoding law each time it receives the synchronizing pulse S.

The PCM group thus encoded is input to the SC-I stage to which it is addressed, to the input of which a respective RIL unit is connected which carries out the said alignment operations by comparing the temporal position of the local synchronizing pulse S output by its respective timing unit with the temporal position of the synchronizing pulse S extracted from the received data stream.

If the two pulses (S and S ) appear to coincide, the PCM

1 r signals are output with a lag of 8 bits (1 byte); in all other cases the lag can take on values which, according to a preferential embodiment may vary from 1 to 11 bits.

Fig. 2 illustrates the circuits of the RIL unit necessary to manage a PCM group; said circuits are constituted by a basic time generating unit TBG, a transmitting section ST and a receiving section SR.

The TBG unit receives the said sequence of timing pulses .CK₀ o from its relevant stage timing unit UT$ as well as the synchronizing signal S having a frequency of 4 KHz. The TBG - 7 -

unit outputs the said local synchronizing pulse S every two frames of the PCM signal, as well as a local timing signal

CK . with a frequency of 2 MHz. 2L

The transmitting section ST has an encoding unit for converting the PCM signals from their original code (N.R.Z.) into a biphase type code (eg: Manchester II henceforth also referred to as Mil). The said encoding unit is implemented by means of a logical product circuit A which receives the said signal CK on its first input and the local

__*> synchronizing pulse S on its second input. The output of the A unit is input into the first input of an exclusive OR circuit EX which receives the NRZ signals_/ represented in diagram A of fig. 3*on its second input; diagram B on the other hand illustrates the said signal CK .

The output of the A unit corrisponds to the PCM signal converted into Mil code which, as can be seen from diagram C, includes the transmission - during the first half of the bit time - of the same logical value as the NRZ signal and during the second half of the bit time the transmission of said logical value inverted.

The output of the EX unit on the other hand corrisponds to the MIl/S signal where a violation - operated by the signal S (see diagram D) - to the encoding regulations of the Mil code (see diagram E), is present. It must be kept in mind that transmission of the said violation must be carried out when a couple of bits with the same logical value are present in the NRZ signal and, according to a preferred form of embodiment, said transmission is carried out, in - 8 _

alternate frames, . in corrispondence to the first bit of tthhee ttiimmee sslloott zzeerroo TTSS iinnttoo wwhhiicchh aa control __{: WO}rd with the configuration 00011110 is inserted.

The PCM signal, after being manipulated as described above, is sent to the line L, to the other end of which a receiving section SR of a relevant RIL unit is connected.

The SR unit includes a decoder DC comprising an exclusive OR circuit EX to the output of which a gϋlf register comprising five memory cells C , ••., C made with B type bistable elements is connected. The said bistable elements receive a clock signal CK₀ with a frequency of 8 o

MHz on their timing input. The decoder DC also comprises a sampling unit C- , made by means of a further B

6 type bistable circuit which will receive the inverted output of the C cell on its timing input and the MIl/S signal on its data input. The inverted output of the C cell corrisponds to a clock signal with a frequency of 2 MHz, extracted from the received data stream, henceforth indicated by CK .

^J 2R

In order to correctly sample the MIl/S signal, the C, unit o must receive a pulse on its timing input in the instant in which the "true" logical value of the MIl/S signal (first half of the bit time) is present on its own data input.

The sampling instant is determined by the EX units, in as much as the EX unit outputs a pulse each time the "true" logical value - "inverted" logical value transition is present in the MIl/S signal. The said pulse 9 -

spreads over the C and C cells at the rate defined by the ^ 1 2

CK- signal and consequently corrisponds to the output of the C unit after an interval of time equal to 3/4T, where T is the duration of a bit of the NRZ signal. As can be seen from diagrams A and C of fig. 3, after an interval of time equal to 3/4T, the "true" logical value of the original signal is present on the input of the C, unit and consequently the DC

0 decoding unit can correctly reconstruct the NRZ signal.

The C_, C. and C_ units - together with the C. and C_n units 3 4 5 1 2 and together with a logical sum unit 0 - have the function of extracting the said synchronizing pulse S from the MIl/S stream. The extracting operation requires the use of at least four memory cells because during the time T mentioned above the CK₀ signal presents four pulses and consequently, o for all the time that the Mil signal encoding law is respected, in at least one of the cells C , ..., C the said pulse concerning the enabling of the output of the EX unit specified above is present. Consequently, for all the time that the condition described above occurs, logical value "one" corrisponds to the output of the 0 units. Instead, when the Mil code encoding law is violated to transmit the said synchronizing signal S (see diagram E where the violation has been evidenced with a broken line), suppression of a transition in the Mil signal is registered and as a consequence for an interval of time equal to T/2 the pulse mentioned above is not present in any of the cells C , •••>, C . As a consequence the output of the 0 unit assumes a zero logical value for an interval of time of a predetermined entity, which constitutes the synchronizing pulse S extracted from the received data stream. r - 10 -

The output of the C . unit is connected to the K + 2 cells of an elastic memory ME, where K represents the memory's degree of elasticity, said memory having a further two cells to ensure that a time interval of at least one bit passes between a write operation and a read operation.

Writing of the bits available on the output of the C, unit o is controlled by a write counter CS, with a counting capacity of K + 2, which receives the said pulses CK on

2R its counting input and the synchronizing pulse S available r on the output of the 0 unit on its preset input.

Reading of the memory cells of the ME unit is controlled instead by a read counter CL, also with a counting capacity of K + 2, which receives the signal CK and the synchronizing signal S output by the relevant basic time generating unit TBG respectively on its counting input and preset input. The outputs of the CL unit monitor a multiplexer MX, with K + 2 inputs, to the output of which a PCM data stream corrisponds that is aligned with the remaining streams that enter the communications branch point.

According to a preferred form of embodiment the number K is assumed equal to 10 in order to allow the carrying out of alignment operations when the deviation between the S r pulses and the S pulses is not more than 7 bits of lag and . 3 bits of lead.

Again according to the said preferred form of embodiment the write counter CS is preset to i s first counting step whilst 11 -

the read counter CL is preset to its fifth counting- step,

If the synchronizing pulses S coincide with the S pulses r 1 writing of the M cell and reading of the M cell occurs. Therefore, reading of the bit written in the M cell is carried out after eight pulses of the CK sequence.

When the S pulse is in the maximum allowed lag condition r

(seven pulses from the CK sequence) reading of the M

2R 1— cell occurs and writing of the M cell. Reading of the bit written i . the M cell is therefore carried out after one pulse of the CK sequence.

ΛΛJLf

On the other hand when the S pulse is in the maximum r allowed lead condition (three pulses of the CK sequence)

2R writing of the M. cell and reading of the M_ cell occur.

4 5

Reading of the bit written in the M cell is therefore

4 carried out after eleven pulses of the CK sequence.

£έ-L_

Therefore, the bit written in any one cell of the elastic memory is read with a ^'.delay that varies in relationship to the position of the S pulse compared to that of the S pulse. In particular, the said delay can assume a value that goes from one pulse to eleven pulses of the CK sequence. The alignment operation of the PCM groups that enter a communications branch point is therefore carried out by determining the simultaneous reading of a predetermined bit of the frame . of all the groups; within the ambit of each group the write operation is instead carried out in an instant that differs from group to group in relation to the position of the S pulses compared with r that of the S pulses.

The circuit arrangement as claimed in the invention also includes the presence of an alarm unit AL to verify the state of the respective line L and of the memory ME by using said monitoring word transmitted in alternate patterns in the time slot TS . In particular, the said alarm unit

0 includes the presence of a third exclusive OR circuit EX which receives the said monitoring word P from the TBG unit in predetermined instants that coincide with the instants in which said word corrisponds to the output of the MX unit.

The output of EX is input into a logical product unit A„

3 *• which receives an enabling signal Ab output by the TBG unit on its second input. If there is a failure on the line L and/or in the memory ME, activation of the output of the A

__> unit is registered thus signalling the presence of an abnormal condition.

In the description given above reference has been made to a circuit arrangement comprising a transmitting section ST, a receiving section SR and a basic time generating unit TBG. Without leaving the ambit of the invention it is possible to embody a circuit arrangement which might be implemented in the form of an integrated circuit comprising a single TBG unit to which ri transmitting sections and ii receiving sections are connected.

Claims

- 13 -

l) Circuit arrangement to align the PCM groups entering a communications branch point by means of lines, one another, characterized in that it includes the presence of a transmitting section (ST) and of a receiving section (SR), connected on to each end of each of the said lines (L), as well as of_abasic time generating unit (TBG) designed to output a clock signal (CK ) with a frequency equal to that of the PCM signals to be aligned on its first output, and a local synchronizing pulse (S ) with a predetermined repetition rate on its second output,' in that the transmitting section (ST) includes , means designed to encode the PCM signals according to a biphase law and also designed to introduce violations to said law each time they receive the said local synchronizing pulse (S ), and in that the said receiving section (SR) includes the presence in combination of the following characteristic elements: - decoding means (DC) designed to output the PCM signals on their first output after having converted the same from the said biphase type law (Mil) into the original law

(NRZ), a clock signal (CK ), extracted from the received K. signals, on their second output , and a synchronizing pulse (S ) every time that they pick up the presence of the said violations in the biphase type law on their third output ; - an elastic memory (ME) with K + 2 memory cells, K being a integer _numDer expressing the memory's degree of elasticity; - a write counter (CS) designed to enable writing in the cells of said elastic memory (ME) starting from a specific - 14 -

cell, with K + 2 counting steps and with its counting input and its enabling input respectively connected to the second (CK ) and third (S ) outputs of the decoding means (DC); - a read counter (CL) designed to enable reading of the cells of the said elastic memory (ME) starting from a specific cell, also with K + 2 counting . steps and with its counting and enabling inputs respectively connected to the first (CK ) and second (S ) outputs of

_C!_• X the basic time generating unit (TBG).

2) Circuit arrangement as described in claim 1 characterized in that the said biphase type code is the Manchester II code as well as that the said encoding means include the presence in combination of the following characteristic elements:

- a first logical product circuit (A ) designed to receive said first and second output (CK and S ) of the basic time generating unit on its input;

- a first exclusive logical sum circuit (EX ) designed to receive the output of the first logical product circuit

(A ) on its first input and the PCM signals on its second inpu .

3) Circuit arrangement as described in claim 1 characterized in that the said decoding means (DC) include the presence in combination of the following characteristic elements: a second exclusive logical sum circuit (EX ) which receives the PCM signals converted into said biphase type code on its first input, and the signals output on the first output of the decoding means (DC) on its second input; - 15 -

- a , . shift- register with h + 1 memory cells (C , ..., C_), where h is a integer number, designed to receive the data available on the output of the second exclusive logical sum circuit (EX ) on its input, at the rate defined by a second clock with a frequency li times greater than that of the received data stream;

- a D type bistable circuit (C_ή) with its data input connected to the said line (L) and its timing input connected to the output of the shift- register' s h/2 cell;

- a logical sum circuit (0 ) with its inputs connected to the output of their respective cell of the shift- register, on the output of which the synchronizing pulse

(S ) extracted from the received data stream is available, r

4) Circuit arrangement as described in claim 1 characterized, in that said number K is assumed equal to 10 as well as that the write counter (CS) is preset to its first counting step whilst the read counter (CL) is preset to its fifth counting - step.

5) Circuit arrangement as described in claim 1 characterized in that said write counter (CS) is of the type with decoded outputs whilst the read counter (CL) has its outputs connected onto the monitoring inputs of a multiplexer (MX) which has its data inputs connected to their respective cell of the said elastic memory (ME).

6) Circuit arrangement as described in claim 1 characterized in that the said receiving section (SR) also includes the presence of an alarm unit (AL) which includes the following - 16 -

characteristic elements:

- a third exclusive logical sum circuit (EX ) which receives the output of the said multiplexer (MX) on its first input and a monitoring word (P) on its second input that is output by the basic time generating unit (TBG) at predetermined instants;

- a second logical product circuit (A ) designed to receive the output of the third exclusive logical sum circuit (EX ) on its first input and an enabling signal (Ab) output by the basic time generating unit (TBG) on its second input.

7) Circuit arrangement as described in claim 1 characterized in that it is embodied in the form of an integrated circuit and includes the presence of a basic time generating unit (TBG) to which ri transmitting sections (ST) and n receiving sections (SR) are connected.

8) Circuit arrangement according to all that has been illustrated in the aforegoing description and attached drawings as also any isolated or combined parts of the same.