EP0192723A1 - Procede et appareil de chargement d'informations dans un dispositif semi-conducteur a circuit integre - Google Patents

Procede et appareil de chargement d'informations dans un dispositif semi-conducteur a circuit integre

Info

Publication number
EP0192723A1
EP0192723A1 EP19850904470 EP85904470A EP0192723A1 EP 0192723 A1 EP0192723 A1 EP 0192723A1 EP 19850904470 EP19850904470 EP 19850904470 EP 85904470 A EP85904470 A EP 85904470A EP 0192723 A1 EP0192723 A1 EP 0192723A1
Authority
EP
European Patent Office
Prior art keywords
mask
arrangement
regions
memory
radiation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19850904470
Other languages
German (de)
English (en)
Inventor
Jerzy Josef Ullmann
Richard Fry
Anthony Raven
Willy Michel Désiré SIERENS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PA Consulting Services Ltd
Original Assignee
PA Consulting Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB848432518A external-priority patent/GB8432518D0/en
Priority claimed from GB848432583A external-priority patent/GB8432583D0/en
Application filed by PA Consulting Services Ltd filed Critical PA Consulting Services Ltd
Publication of EP0192723A1 publication Critical patent/EP0192723A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/005—Arrangements for writing information into, or reading information out from, a digital store with combined beam-and individual cell access

Definitions

  • This invention relates to method and apparatus for loading information into an integrated circuit semiconductor device.
  • the information may be in the form either of data to be loaded into a memory or of a pattern of logic states for an array of logic elements.
  • Background of the Invention ⁇ o
  • U.S. Patent Specification No. 3488636 discloses a semiconductor memory formed by diodes, each memory cell comprising two back-to-back diodes connected to an associated photosensitive diode.
  • a mask having a plurality of selected openings allows light to be is- incident only on selected photosensitive diodes, thus programming the array of cells in accordance with desired information. Only a specially designed diode memory array is contemplated.
  • the integrated column conductors provide the function of the mask.
  • IGFET insulated gate field effect transistors
  • ⁇ c photo-transistors the latter being responsive to light to change the state of the bistables.
  • the memory devices are specially constructed to include these photo-transistors which are additional components and hence decrease the storage capacity per unit size on
  • Circuit structures have altered considerably with the onset of WSI (wafer scale integration) and VLSI circuits.
  • the trend is to increase the density of ⁇ electronic systems which leads to a scaling down of the .
  • ⁇ o delay arises due to the electrical loading of memories. Another form of delay arises due to multiplexing, which is required to reduce the number of external connections.
  • DRAM Dynamic ' ⁇ Random Access memory
  • This consists of an array of diffusions (forming IGFET transistors having drain junctions) which act as charge storage capacitors in reverse bias polarisation. The capacitance is usually increased by a small integrated parallel plate capacitor.
  • the scources of the addressing transistors are tied together in columns as bit lines, and the gates are tied ⁇ together in rows as the word lines.
  • the bit lines are held at a high or low voltage according to the information to be written, which results in charge being transferred to or removed from individual drain junctions. In this operation only one word line is ⁇ o switched on and all the storage capacitors attached to other word lines will remain unaffected. This allows selective writing of the information.
  • This RAM structure is very dense as a result of the extreme simplicity of the storage and addressing device (one transistor cell) . It suffers from the disadvantage that each bit has to be refreshed at a rate
  • ⁇ form of circuit structure is a dynamic logic array having a plurality of logic gates. Pulsing or driving of gates is discussed in "Switching characteristics of logic gates addressed by picosecond light pulses" Jain & Snyder, IEEE Journal of Quantum electronics, Vol.QE-19, No. 4, April 1983.
  • the light source used for switching the gate is a laser, focused to a small spot diameter, e.g. 10 ⁇ m for
  • This irradiation technique is unsuitable for the large number of gates on a WSI or VLSI semiconductor chip.
  • an apparatus comprising an integrated circuit device; and a mask having a pattern of radiation more transmissive and less transmissive
  • the mask being removably mounted to a holding structure fixed with respect to the device so that the mask can be positioned with respect to the device to load said pattern into the device by irradiating the device --ic via the mask, the apparatus including alignment means for ' positioning the mask with respect to the device so that the mask can be removed from the structure and replaced by a further mask having similar alignment means to enable a different state pattern to be loaded into the l ⁇ device.
  • the device may have a plurality of radiation sensitive regions for controlling the state of semiconductor elements of the device.
  • it may comprise a semiconductor memory having storage
  • Relocations including the semiconductor elements or it may comprise an array of logic means linked by interconnection means incorporating said semiconductor elements, the interconnection pattern of the logic means being controlled by said state pattern.
  • ⁇ Preferred embodiments enable loading of a memory or logic array to take place without interruption of use of the memory or array. That is, where binary information is being continually read from a memory by electrical addressing, "optical updating" by changing the mask can occur simultaneously, data currently stored in the memory being read out while a new mask is put in
  • Reading of the memory can be stopped so that the new data can be loaded into the memory by irradiating it via the new mask with a pulse of radiation.
  • an apparatus comprising an
  • alignment of the mask is carried out as part of the manufacturing process. This enables a plurality of standard semiconductor chips to be manufactured, with the addition of a mask to each chip s ⁇ enabling "personalisation" according to individual manufacturer's requirements.
  • the light will enhance the rate of charge decay by orders of magnitude.
  • IGFET insulated gate field effect transistor
  • They have special gate insulator structures such as double 5 dielectric layers at the gate or a floating gate buried into the gate dielectric.
  • the special gate insulator provides trapping centres for permanent charge storage either at the double dielectric interface or in the floating gate. Charge can be transferred to these gates ⁇ c by channelling effects, hot electron effects or similar mechanisms based on relatively high voltage or current pulses thereby shifting the threshold voltage. In the normal operating regime, no charge is transferred to or from these trapping centres and the device behaves as a -- 15 " ROM.
  • ROMS read only memory
  • ultraviolet light is used to excite the carriers in the floating gate sufficiently that they can tunnel back. .20 This is * done to erase the memory.
  • loading of the memory can be carried out by precharging all the storage nodes followed by selective erasure of the memory by irradiating it via a mask.
  • the mask can be removed and replaced, according to the first aspect, by an alternative mask or by a combination of two masks one above the other as described
  • the information carried by the mask itself could be altered in the first and second aspects.
  • an apparatus comprising an is integrated circuit device; and a mask fixedly mounted with respect to the device and having a plurality of regions whose ' transmissivity to radiation is alterable to provide more transmissive and less transmissive regions to form a pattern representing a set of digital information to be loaded into the device, said mask being positioned with respect to the device so that any one of
  • a plurality of different sets of digital information can be loaded into the memory by altering the alterable regions of the mask accordingly, and by irradiating the device through the mask.
  • the device may comprise a memory having an array
  • the mask is positioned with said alterable regions corresponding respectively to said radiation sensitive regions.
  • Preferred embodiments of this aspect of the invention enable fast loading of a memory to occur. This overcomes the problems associated with the loading of the currently available memories, which may have storage capacities of 500 Kilobit or 1 Megabit. It is a * >particularly useful where a memory 'forms part of a processor or overall computing circuit and is to be used in an on-line situation in which it is intermittently to be reloaded with information to permit a fresh computation or fresh set of data to be available. In
  • any down time of the memory dictates the total down time of the processor and associated circuitry, since while the memory is being loaded or up-dated o electrically it cannot be used in the on-line mode as part of the processor or computing circuit.
  • the down time is substantially reduced.
  • the device can function conventionally provided that a light
  • ⁇ source for irradiating the chip via the mask remains off, .and indeed may be a chip packaged in a DIN mounting so as to be pin-to-pin compatible with existing chips.
  • the light source can be activated to parallel load the state pattern carried by the mask in parallel ⁇ o into the device.
  • the state pattern of the mask can be changed by altering the temperature and addressing the mask to alter selected ones of the alterable regions whilst the device is operating with its existing data content.
  • MOS transistors of a DRAM and IGFET transistor of a ROM embodiments of the invention may be used with arrays of any suitable transistor, e.g. FETs and bipolar transistors.
  • a mask may be located remote from the semiconductor surface, the light pattern therefrom being focussed onto the surface of the memory using an optical
  • the mask can be formed directly at the surface of the memory so that light incident on the mask can illuminate selectively the radiation sensitive regions below the mask, depending on the particular electrical
  • the mask can be located in close juxtaposition, to the memory in a light tight housing with the alterable regions of the mask aligned with the radiation sensitive
  • ⁇ i_ ⁇ regions of the memory are formed.
  • the term "light tight" is used to denote a housing which does not permit external radiation to irradiate the memory.
  • a further mask may be interposed between the first mask and the integrated circuit to provide radiation transmissive passages to respective sensitive regions.
  • means may be provided for so irradiating the surface of the device before exposing the surface via the mask.
  • material of the mask may be frequency o sensitive so that it is opaque at one frequency of electromagnetic radiation but sufficiently transmissive at a second frequency of electromagnetic radiation as to cause the entire surface of the device to be subjected to electromagnetic radiation at the said second frequency. is For example by exposing a memory, via the mask, to radiation at the second frequency before exposure to radiation at the first frequency, all of the storage locations within the memory will be exposed, so that subsequent exposure to a state pattern using radiation of
  • a wide spectrum radiation source may be used with this type of mask such that radiation in one range of frequencies can pass therethrough whilst radiation in a
  • the opaque (less transmissive) regions of the mask may be polarization sensitive so that electromagnetic radiation polarised in one particular orientation can pass but radiation oriented in other l ⁇ directions will be prevented from passing.
  • the whole device is exposed to unpolarised light or to light polarised in the passing direction. Subsequent selective exposure is achieved by irradiating the device via the mask by light polarised in a direction perpendicular to the passing direction.
  • the mask may be made of a material
  • the mask may alternatively be such that the refractive index of the material forming the mask can be changed/by the application of electrical signals or other x ⁇ means so that the light transmissive properties of different regions within the mask can be changed by altering the refractive index of the regions to cause selectively either divergence of electromagnetic radiation incident thereon or total internal reflection is " to occur.
  • a fourth aspect of the present invention there is provided a method of loading information in the form of a two-dimensional image into a memory of an integrated circuit device, the memory having
  • the image may be formed by illumination through a transparency, a lens forming the size reduction.
  • the image may be the output of an optical computer, for example as discussed in "Digital Optical Computing", Sawchuck and Strand, Proc. IEEE Vol.72, No. z> 1 , July 1984. In this case no image reduction would be required.
  • an optical computer may be defined as a device for performing optically numerical computations on n dimensional data that are generally not images.
  • an optical computer for providing an output in the form of a two dimensional image representing a state pattern
  • an integrated circuit semiconductor device having
  • an integrated circuit semiconductor memory having a plurality of storage locations, each location comprising a transistor responsive to incident radiation to control the
  • the manufacture of the opaque layer is made simpler, due to the aperture size, than the case where a small aperture is provided to illuminate only a small portion of the transistor.
  • a computer system comprising: an integrated circuit memory having storage S locations whose state can be controlled in response to incident radiation; an image forming device comprising a source of radiation and a mask having a two dimensional array of regions corresponding respectively to said storage ⁇ locations, each of which regions is alterable between a more transmissive and a less transmissive state thereby to form a pattern representing a set of digital information to be loaded into the memory; means for actuating the source of radiation to is " irradiate the memory via the mask to cause the information represented by the pattern to be loaded into the memory; and means for controlling the image forming device to alter the pattern, so that on subsequent irradiation a ⁇ 3 ⁇ further set of digital instructions is loaded into the memory.
  • the image forming device may be part of a machine including the memory, or it may be in another machine, whereby one machine can communicate with another.
  • Figure 1 illustrates diagrammatically a system ⁇ c, according to one embodiment of the present invention
  • Figure 2 shows a computer system using the system of Figure 1;
  • Figure 3 illustrates the electronic structure of a dynamic random access memory
  • ⁇ Figure 4 illustrates a typical semiconductor structure of two cells of a dynamic random access memory, with a mask diffused thereon
  • Figure 5 illustrates a semiconductor structure as shown in Figure 4 except that the mask has been manufactured separately and subsequently bonded to the memory structure
  • Figure 6 illustrates a mask and memory structure which is the same as that of Figure 4, except that the mask has regions which are alterable so as to be more or less transmissive to radiation;
  • Figures 7a to 7c illustrates assembly steps of a ⁇ c "mask module” and Figure 7d illustrates such a module;
  • Figure 8 illustrates a chip holding structure with a memory chip
  • Figure 9 illustrates a device for locating the mask module relative to the chip
  • Figure 10 illustrates another system for transferring the data carried by a mask onto a semiconductor chip, the mask being carried by a card rather than in a mask module;
  • Figure 11 shows one system for aligning the state OJC- pattern on the mask with the memory on a chip
  • Figure 12 shows a light source, an alterable mask, a lens and a chip fixed in a light tight housing
  • Figure 13 shows a package containing a chip carrying two masks, the first being fixed and the second 2S ⁇ being alterable;
  • Figure 14 illustrates a form of optical grating which may be used to generate Moire fringes
  • Figure 15 shows a structure similar to that of Figure 5, having two masks, both of which are alterable ⁇ to enable logic functions to be performed;
  • Figure 16 shows diagrammatically a system using an alterable mask as a nonvolatile buffer
  • Figures 17a and 17b illustrate possible arrangements for 4 x 4 data and logic masks
  • ⁇ Figure 18 illustrates diagrammatically the loading of a chip from the output of an optical computer
  • Figure 19 is a diagram illustrating another- form of alignment
  • FIG. 1 shows a VLSI integrated circuit semiconductor device 10, e.g. a DRAM, which has an array of selectively addressable regions or storage locations
  • a mask 14 is provided, having a pattern of light and dark zones corresponding to a set of digital information to be loaded into the memory. Collimated light 12, from a light source (not shown) and condensing '• lens 34, is projected * through the mask 14 and through a reducing lens 16 onto the device 10 to irradiate selected ones of the addressable regions.
  • the condensing lens serves to focus an image of the light source onto the reducing lens: it is not always necessary to provide
  • Position sensors 18, 20 for ensuring the required registration between the light pattern and the device 10 are provided. These are preferably constituted by optical gratings o generating Moire fringes.
  • Moire fringes may be generated by aligned optical gratings with a fixed line spacing to indicate relative movement between two surfaces carrying the gratings. In order to use Moire fringes to indicate the position of
  • Figure 2 illustrates a computer system which is conventional apart from the addition of a nonvolatile buffer 60 to be described in more detail hereinafter.
  • the system has a microprocessor 62 which communicates via
  • bus 64 with conventional ROM address, RAM address and I/O port address circuitry 66, 68, 204. Also connected to the bus 64 is direct memory access control logic 206. Other components will communicate with the bus 64 as in a conventional computer system, but these are not shown• for
  • ROM 70, RAM 72, I/O port 208, and DMA control logic 206 comprise a plurality of semiconductor chips, one or more of which may be a device such as 10 ( Figure 1) associated with an arrangement as described with reference to Figure 1. This is possible
  • the device 10 of Figure 1 may be a pin-to-pin-compatible conventional integrated circuit chip.
  • the chip may include a register for storing data.
  • a cache RAM 210 is shown communicating directly with the
  • this RAM may also include a device such as 10 in Figure 1.
  • the cache RAM 210 may be replaced by a memory management unit. In the case of the ROM, and DRAM it is only necessary to provide a flash of light sufficient to load the state pattern into the chip:
  • FIG. 3 illustrates one form of structure of the DRAM of Figure 1.
  • Each cell has a transistor T1-T4 and a storage capacitor Cl to C4.
  • All the transistor cells will be set to "1" to charge the capacitors. Irradiation of any one of the capacitors will cause it to discharge, changing the state of digital information stored at that location from a "1" to "0".
  • the transistors have their sources connected in ⁇ c rows to buried bit lines, and their gates connected in columns to word lines.
  • the photocurrent has to discharge:-
  • this . switching mechanism can be described as reasonably effective, in fact more effective than any electronically ⁇ addressed switching in this size of array.
  • the switching energy of 1.03 pj is actually the power-delay product of the gate or memory cell.
  • the lightflulxx nneecceessssaarryy ttoo aacchieve a write time t is at least:-
  • ⁇ power-delay product is therefore 1.03 uJ. Since the power needs to be limited to 1 W maximum, a loading cycle time of 1 MHz is achievable. A complete memory update can be carried out in 1 us. Therefore, the data rate for writing to the memory is 1 Tbit/s. ⁇ C
  • the values given above are examples of one form of DRAM. Using a 1 Mbit DRAM with 3D Stacked Capacitor Cells, values of capacitance up to 75fF may be attained.
  • Figure 4 illustrates a typical dynamic RAM structure having a p-type substrate 5 with n- and p-type
  • the storage capacitors Cl, C3 are formed by polysilicon plates 6, 7.
  • the plates 6, 7 are shown "floating" but will be grounded by suitable connections.
  • the substrate 5 carries two SiO layers.8, a metal layer 9 forming the word line, and
  • a mask in the form of an opaque layer 13 is deposited over regions of the chip as the final layer.
  • the mask has holes 15 corresponding to selected locations of the memory for allowing a radiation source to irradiate the storage ⁇ ' transistor and capacitor of those memory locations which are to be discharged.
  • the holes are dimensioned to enable radiation to irradiate a major portion of the transistor and associated capacitance e.g. at least 75%, not just the capacitance.
  • Other memory locations are
  • Figure 5 illustrates part of a memory chip having the structure as shown in Figure 4, but in which a two-dimensional mask 18 of self-supportng material has been manufactured separately and subsequently bonded to
  • the mask has more transmissive and less transmissive regions, such as are shown at 19 and 21 respectively. It may be a photographic transparency.
  • the state pattern to be loaded into the semiconductor device is clearly unalterable once the mask layer has been deposited onto the chip, or bonded onto the chip as the
  • Figure 6 illustrates the chip and mask arrangment of Figure 5 with the important difference that the mask -28 is such that it has alterable regions 29, 30 which can be made more or less transmissive to radiation in
  • the mask 28 in Figure 6 may be a spatial light modulator (SLM) having a two-dimensional . array of alterable regions, two of which are shown at 29 and 30.
  • SLM spatial light modulator
  • an optically addressed SLM as
  • a liquid crystal display can be used, preferably a non-volatile LCD display.
  • Suitable LCDs are those of the type which cannot be S written to at room temperature, but which must first be heated and then electrically written to. If allowed to cool, "they will retain the state pattern written into them.
  • One form of LCD is such that it can be written by applying a potential difference across its cells, for example using transparent electrodes disposed above and below the display, and subsequently heating those regions S of the LCD whose state is to be changed. The state patterns will remain in the LCD if the voltage is applied for sufficient time to hold the state change while the LCD is cooled.
  • a suitable LCD for the present application is that described in the articlee ⁇ o entitled "A 4 Mpel Liquid Crystal Projection Display addressed by Gallium Arsenide laser array", in the 82 Digest of the Society of Information Display from IBM General Products Division, pages 240 and 241.
  • Another form of liquid crystal array may include electrically
  • A*> the state pattern to be loaded into the semiconductor device can be altered by addressing the mask 29, as illustrated diagrammatically by arrow 31 in Figure 6, to change the transmissivity state of the alterable regions such as 29, 30, e.g. via conventional memory addressing
  • the mask can be
  • Figures 7a to 7c illustrate assembly steps for making such a mask module
  • Figure 7d is a perspective view thereof.
  • Figure 7a shows a mask 32 about to be sandwiched between two transparent acrylic covers 33, 34.
  • the mask 32 carries a state pattern in the form of opaque and translucent [less transmissive and more transmissive] regions. In this form, the mask may be a photographic transparency.
  • the mask 32 is provided with an alignment point 35.
  • the layers 32, 33, 34 are laminated together
  • a mask structure 36 generally denoted 36 [ Figure 7b].
  • the mask structure 36 is supported by a cylindrical support 37.
  • An alignment point 38 in the support 37 is used, with the mark 35 on the mask, accurately to position the mask structure 36 relative to the support ⁇ o 37.
  • An automatic position control system [not shown] can be used to manipulate the mask structure 36 to the desired position.
  • a cover 38 is welded onto the support 37 to form the mask module shown in Figure 7d.
  • a semiconductor chip 40 ( Figure 8) is mounted to a chip holding structure 41, the chip holding structure having external dimensions such as to provide a sliding fit within the mask module so that it can be aligned therewith as shown, by dotted lines, in Figure 9.
  • Figure 8 A semiconductor chip 40 ( Figure 8) is mounted to a chip holding structure 41, the chip holding structure having external dimensions such as to provide a sliding fit within the mask module so that it can be aligned therewith as shown, by dotted lines, in Figure 9.
  • ⁇ c 9 illustrates a housing 42 carrying the chip supporting structure 41 and having a light source 43.
  • the mask module is pressed into the housing 42 against the action of a
  • __r spring 43 by movement in the direction of arrow A at the same time as a spring-biased dust cover 44 is urged away from the chip holding structure 41 by the module.
  • the spring 43 serves to urge the mask module into position over the chip holding structure 41 so that the mask is
  • the module having a sliding fit with the chip holding structure.
  • the state pattern carried by the mask is loaded into the chip. It is apparent that a different Tstate pattern can be loaded into the chip by simply removing the mask module and replacing it by a further mask module supporting a mask carrying a different state - - pattern .
  • V grooves As an alternative to spring loading, other forms of mechanical alignment can be carried out, i.e. three coplanar V grooves, preferably directed to a common point 5 on, say, the chip, or its mounting and three pegs on the mask module which can engage those slots.
  • An alternative is the so-called Kelvin support where three pegs are located respectively by a tetrahedral hole (sometimes approximated by a conical hole), a V groove (probably ic directed at the hole) and a plane surface. Either of these provides the six constraints which are necessary and sufficient to determine the relative positions of two rigid bodies. For convenience in use the memories or logic arrays are adjusted to a specific relationship to
  • a mask 35' could be carried by a relatively rigid card 46 as shown in Fig. 10, the state pattern carrying
  • a lens 49 is located between the chip and the - ⁇ mask in such a position as to focus light from a light source 50 via the pattern carried by the mask onto the chip.
  • the lens effects a suitable size reduction for the pattern.
  • a required tolerance in chip/mask alignment of for example -+ 3 urn is increased to + 30 ⁇ m when setting the mask within the card.
  • FIG. 11 One suitable arrangement for loading into a semiconductor device a state pattern carried by a mask in r ⁇ a mask module is shown in Figure 11.
  • the module casing 37 carrying the mask with the pattern to be loaded into the device on a chip is located in a holding structure 51 which is mounted to a PCB 52 carrying the chip 53.
  • the holding structure 51 has a lens 54 and a x movable mirror 55 mounted therein, movement of the mirror about mutually orthogonal axes being carried out by two d.c. servo motors 56, 57 driving micrometer screws.
  • the structure 51 has a door 58 carrying a light source 59, the door being shown in its open (full line) and closed
  • An array of features is provided on the mask 35 e.g. a linear array of opaque and transparent blocks, preferably of a pitch which cannot be confused with that of the state pattern carrying portion of the mask.
  • the pattern may be read by photodetectors incorporated in the chip.
  • the detectors may be distinct from and
  • ⁇ geometrically separated from the memory array, or specific cells of the array may be designed to respond to the illumination pattern of the linear array of features. Signals from detectors or cells are fed to a control system 300 to control the motors 57, 58 until the pattern
  • the memory or logic array has two or more small areas 30Zcfnigher reflectivity than the remainder to be aligned with respective ones of two small transmissive areas 304 of the mask, e.g. two small holes.
  • light 305 is projected through the mask onto the array, and the light reflected back from the highly reflective areas on the memory can be detected through the holes 304 in the masks by suitably positioned detectors 308 mounted in the module. Details of the Ao module and chip holding structure are " omitted for the sake of clarity.
  • any misalignment is measured at at least two points.
  • the ___» *• very small distance between the mask and the chip, and rotations about axes parallel to the plane of the chip may be adjusted mechanically. Translational movements in the plane of the chip may be monitored at one point, and rotation about that point monitored at the second point.
  • Figure 12 shows a light tight housing 37 containing a chip 76 carrying an integrated circuit memory or logic array, a lens 78, a mask structure 80, [similar to that described in Figure 7a but including an in alterable mask 82] and a light source 84.
  • the addressing circuitry for the alterable mask 82 is not shown in Figure 12.
  • Figure 16 illustrates diagramatically a similar system with a chip 86 carrying an array of transistor cells an
  • the alterable mask as arranged in the diagram of Figure 16 is as a non-volatile buffer, for example that designated 60 in Figure 2.
  • a liquid crystal panel formed of a material having a resp ' onse time which is long compared with the time for which a state pattern is to be carried by the mask at the
  • a mask can be made in which any pattern, once established, will persist for a useful length of time.
  • such a mask may be made with a pair of transparent electrodes to which a voltage can be ic applied to tend to drive the liquid crystal material to one optical state.
  • the liquid crystal material is then heated sufficiently to allow it to attain that optical state, and is subsequently allowed to cool.
  • a voltage [which may be zero] is then applied to tend to drive the is " liquid crystal material to the opposite optical state, but, as the liquid crystal is cool, no change occurs.
  • the mask is then scanned by a modulated laser beam, which causes a change of optical state where it strikes the material,to produce a mask with .more or less transmissive
  • Non-volatile mask is a magneto optic mask which comprises a two dimensional array of small garnets.
  • a matrix of wires is associated ⁇ with the array of garnets and is such that when a current of a certain magnitude is carried by one of the wires associated with one particular garnet, no change occurs. When that current passes through both the wires associated with that garnet, a magnetic field is produced
  • the mask can act as a buffer memory, storing data in the form of a state pattern written into a non-volatile mask.
  • the mask can be located over one of the chips of the ROM or RAM (see figure 2), and will cause the data represented by the state pattern carried _ " by the mask to be loaded into that chip when it is illuminated.
  • the buffer can be addressed from the address line connected to the conventional RAM circuit 68.
  • c source of illumination can be turned off, and the mask can then be rewritten with a fresh set of data which can be loaded into the chip with a fresh pulse of radiation.
  • FIG 13 there is illustrated a chip carrying two masks, the lower 92 of which is a fixed mask having S " an array of radiation transmissive regions, which may simply be apertures in an opaque layer, each aperture 96 corresponding to one cell of the integrated circuit array so that a major portion of the transistor in that location is exposed.
  • the upper mask 94 is an alterable
  • FIG. 13 also diagrammatically illustrates an I C package 200 in section, showing a form of illumination which may be used with the arrangements of Figures 4, 5 or 6.
  • a layer of radiation diffusing material 98 is formed over the upper mask 94.
  • the layer 98 may be illuminated at its edges by a light emitting diode (LED).
  • the resulting chip is pin to pin compatible with existing chips, in that the light emitting diode is controlled by an AND gate 201 on the chip and responsive to a unique combination of signals on signal lines _T conventionally provided on the chip.
  • the combination selected to turn the LED on or off will be one which does not normally occur in conventional operation of the chip.
  • Figure 15 shows a structure similar to that of Figure 13 except that both upper and lower masks 100, 102 are alterable and can be addressed by conventional matrix
  • One of the masks serves as a logic mask, and the other as a data mask. They can be in io contact and bonded to the chip as shown or can be bonded to each other and separate from the chip, or imaged one onto the other and subsequently onto the chip using suitable lenses. A four by four representation of a portion of the mask is shown in Figures 17a and b. The
  • ⁇ data mask is coded as shown in Figure 17a according to two binary inputs.
  • a logic mask is then set at one of 16 possible combinations as shown in Figure 17b corresponding to the sixteen possible logic operations on two binary inputs. The combination of the data. and logic.
  • Ha masks will only transmit light if the logic function is true for that data combination. More details on combinational logic with Liquid Crystal Light Valves is discussed further in the article entitled “Digital Optical Computing” referred to earlier. In contrast with ⁇ the arrangements discussed therein for storing logic results, e.g. optical feedback loops, in the present case the output from the masks is loaded directly into the memory.
  • FIG. 18 illustrates diagrammatically the loading
  • a focussing arrangement may be provided where necessary.
  • a two dimensional array 314 of lenslets is formed at the surface of the device 310 to focus radiation from the computer 310 onto the
  • any other suitable means for focussing the radiation may be used.
  • the pattern could be copied onto a fixed-pattern mask for quantity production.

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Un agencement permettant de charger des informations dans un dispositif semi-conducteur à circuit intégré (10) comprend un masque (14) ayant une pluralité de régions qui transmettent plus ou moins une radiation (12) pour former un diagramme d'état. Le dispositif (10) peut être une mémoire ou un réseau de portes logiques ayant une pluralité de régions sensibles à la radiation pour commander l'état des éléments semi-conducteurs du dispositif. L'irradiation sélective des régions sensibles à la radiation via le masque permet de charger le diagramme d'état dans le dispositif. Le masque peut être porté séparément par rapport au dispositif pour qu'on puisse le remplacer par un autre masque portant un diagramme d'état différent, auquel cas des moyens d'alignement sont prévus, par exemple des grilles optiques (18, 20) pour générer des franges moirées, dans le but d'aligner chaque masque avec le dispositif. Dans une variante, le masque peut être lié ou intégré sur la surface du dispositif. Comme alternative au remplacement du masque, celui-ci peut avoir des régions pouvant être altérées de manière à les rendre plus ou moins transmissives à la radiation dans le but de pouvoir changer le diagramme d'état porté par le masque. Les agencements ci-décrits permettent un chargement très rapide de données dans des dispositifs à circuit intégré VLSI ou WSI (intégration à très grande échelle ou intégration à l'échelle d'une tranche).
EP19850904470 1984-09-07 1985-09-09 Procede et appareil de chargement d'informations dans un dispositif semi-conducteur a circuit integre Withdrawn EP0192723A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB8422657 1984-09-07
GB8422657 1984-09-07
GB848432518A GB8432518D0 (en) 1984-09-07 1984-12-21 Computer memories
GB8432518 1984-12-21
GB848432583A GB8432583D0 (en) 1984-12-22 1984-12-22 Computer memory
GB8432583 1984-12-22

Publications (1)

Publication Number Publication Date
EP0192723A1 true EP0192723A1 (fr) 1986-09-03

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Application Number Title Priority Date Filing Date
EP19850904470 Withdrawn EP0192723A1 (fr) 1984-09-07 1985-09-09 Procede et appareil de chargement d'informations dans un dispositif semi-conducteur a circuit integre

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EP (1) EP0192723A1 (fr)
GB (1) GB2165693A (fr)
WO (1) WO1986001931A1 (fr)

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GB2190789B (en) * 1986-04-17 1990-05-09 Plessey Co Plc System for optically coupling components of integrated circuits
US4760249A (en) * 1986-12-22 1988-07-26 Motorola, Inc. Logic array having multiple optical logic inputs
DE3701295A1 (de) * 1987-01-17 1988-09-08 Messerschmitt Boelkow Blohm Sensor zum bestimmen von messgroessen
US5189494A (en) * 1988-11-07 1993-02-23 Masato Muraki Position detecting method and apparatus
DE3929132A1 (de) * 1989-09-01 1991-03-07 Siemens Ag Neuronales netzwerk mit optischer programmierung in duennfilmtechnologie
IT1237269B (it) * 1989-11-15 1993-05-27 Rete neurale con capacita' di apprendimento per il trattamento di informazioni, e procedimento per il trattamento di informazioni con l'impiego di tale rete.

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GB1055601A (en) * 1965-03-27 1967-01-18 Ibm Data store
US3488636A (en) * 1966-08-22 1970-01-06 Fairchild Camera Instr Co Optically programmable read only memory
US3626387A (en) * 1968-12-24 1971-12-07 Ibm Fet storage-threshold voltage changed by irradiation
BE756467A (fr) * 1969-09-24 1971-03-22 Philips Nv Dispositif pour aligner des objets, comportant une source lumineuse, unsysteme de detection photosensible et deux porteurs pour configuration
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US3766533A (en) * 1972-05-30 1973-10-16 Ibm Processor utilizing one holographic array and a plurality of photoresponsive storage arrays for high paging performance
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Also Published As

Publication number Publication date
WO1986001931A1 (fr) 1986-03-27
GB8522306D0 (en) 1985-10-16
GB2165693A (en) 1986-04-16

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