EP0192723A1 - Method and apparatus for loading information into an integrated circuit semiconductor device - Google Patents

Abstract

An arrangement for loading information into an integrated circuit semiconductor device (10) includes a mask (14) having a plurality of regions which more or less transmit radiation (12) to form a state diagram. The device (10) can be a memory or an array of logic gates having a plurality of regions sensitive to radiation for controlling the state of the semiconductor elements of the device. Selective irradiation of regions sensitive to radiation via the mask allows the state diagram to be loaded into the device. The mask can be worn separately from the device so that it can be replaced by another mask carrying a different state diagram, in which case alignment means are provided, for example optical grids (18, 20) for generate moire fringes, in order to align each mask with the device. In a variant, the mask can be linked or integrated on the surface of the device. As an alternative to replacing the mask, the mask may have regions which can be altered so as to make them more or less transmissive to radiation in order to be able to change the state diagram carried by the mask. The arrangements described below allow very fast loading of data into VLSI or WSI integrated circuit devices (very large scale integration or integration on the scale of a wafer).

Description

METHOD ANDAPPASATUS FOR LOADING INFORMATION INTO AN

INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE

Technical Field

This invention relates to method and apparatus for loading information into an integrated circuit semiconductor device. The information may be in the form either of data to be loaded into a memory or of a pattern of logic states for an array of logic elements. Background of the Invention ιo U.S. Patent Specification No. 3488636 discloses a semiconductor memory formed by diodes, each memory cell comprising two back-to-back diodes connected to an associated photosensitive diode. A mask having a plurality of selected openings allows light to be is- incident only on selected photosensitive diodes, thus programming the array of cells in accordance with desired information. Only a specially designed diode memory array is contemplated. In one embodiment the integrated column conductors provide the function of the mask. U.S.

_.© Specifications No. 3855582 and 3689900 also disclose diode memory arrays specially constructed to include photodiodes.

In IBM Technical Disclosure Bulletin Vol.21, No.l, June 1978, there is described a method of loading

15 information into an integrated circuit semiconductor memory by illuminating capacitive regions of insulated gate field effect transistors (IGFET) forming cells of the memory thereby to change the charge state of the capacitive regions to load digital information into the ^C memory. The information to be loaded is determined by means of a mask which is integrated as an additional layer of the semiconductor memory and which has light transmissive and non-transmissive regions so that only selected memory locations (i.e. the capacitive regions,

3^5" but not the remainder of the associated transistors] are illuminated. Only one set of digital data can be loaded -2- into the memory, and the mask is integrated as an additional layer during manufacture, under very strictly controlled conditions, of the integrated circuit.

In another system, described in GB 1,376,876, different sets of data are stored as holograms so that on irradiation of each hologram with coherent (laser) radiation, the reconstructed diffraction pattern forms a light pattern which_ illuminates a memory device. The memory device comprises a plurality of bistables and

\c photo-transistors, the latter being responsive to light to change the state of the bistables. The memory devices are specially constructed to include these photo-transistors which are additional components and hence decrease the storage capacity per unit size on

• chip.

Circuit structures have altered considerably with the onset of WSI (wafer scale integration) and VLSI circuits. The trend is to increase the density of ■ electronic systems which leads to a scaling down of the .

■2c basic features. However, the need to communicate between- various sections or sub-sections imposes a speed limit due to the interconnection length. The scaling down approach leaves the interconnection time delay unchanged whilst reducing the gate delay. This effect increases

■IS the relative importance of the interconnection delay compared to the device delay. Moreover the increase of density allows more functions to be put on a fixed silicon area, increasing the importance of the relative difference between delays. One form of interconnection

→o delay arises due to the electrical loading of memories. Another form of delay arises due to multiplexing, which is required to reduce the number of external connections.

One currently available structure is the Dynamic ^'ϋ~ Random Access memory (DRAM) . This consists of an array of diffusions (forming IGFET transistors having drain junctions) which act as charge storage capacitors in reverse bias polarisation. The capacitance is usually increased by a small integrated parallel plate capacitor. The scources of the addressing transistors are tied together in columns as bit lines, and the gates are tied ≤ together in rows as the word lines. In the write mode, the bit lines are held at a high or low voltage according to the information to be written, which results in charge being transferred to or removed from individual drain junctions. In this operation only one word line is ιo switched on and all the storage capacitors attached to other word lines will remain unaffected. This allows selective writing of the information.

In the read mode, the addressing principle is the same, only the function of the peripheral circuitry on

K>^" the bit lines has now been changed to a sensing mode. The charge on the storage capacitors is now transferred to the corresponding bit lines (which have been preset to zero), and a sensitive read-out circuit distinguishes between a high and a low state and latches this o information. The read-out scheme is obviously destroying the information content of the storage nodes attached to the addressed word line. Therefore an automatic refresh cycle is needed, in which the latched read-out information is transferred to the storage nodes in a

^•xζ write cycle.

This RAM structure is very dense as a result of the extreme simplicity of the storage and addressing device (one transistor cell) . It suffers from the disadvantage that each bit has to be refreshed at a rate

"io of a few Hz/tens of Hz hence it qualifies as a dynamic memory. The necessity of refreshing arises from^* slow leakage of stored charge due to capacitor leakage current.

Apart from memories, another currently available

→≤ form of circuit structure is a dynamic logic array having a plurality of logic gates. Pulsing or driving of gates is discussed in "Switching characteristics of logic gates addressed by picosecond light pulses" Jain & Snyder, IEEE Journal of Quantum electronics, Vol.QE-19, No. 4, April 1983. The light source used for switching the gate is a laser, focused to a small spot diameter, e.g. 10^m for

5 illuminating the gate of a MESFET used to construct the logic array.

This irradiation technique is unsuitable for the large number of gates on a WSI or VLSI semiconductor chip.

¹⁰ Summary of the Invention

According to a first aspect of the present invention there is provided an apparatus comprising an integrated circuit device; and a mask having a pattern of radiation more transmissive and less transmissive

.i regions representing a state pattern to be loaded into the device, the mask being removably mounted to a holding structure fixed with respect to the device so that the mask can be positioned with respect to the device to load said pattern into the device by irradiating the device --ic via the mask, the apparatus including alignment means for^' positioning the mask with respect to the device so that the mask can be removed from the structure and replaced by a further mask having similar alignment means to enable a different state pattern to be loaded into the l≤ device.

The device may have a plurality of radiation sensitive regions for controlling the state of semiconductor elements of the device. In particular it may comprise a semiconductor memory having storage

Relocations including the semiconductor elements, or it may comprise an array of logic means linked by interconnection means incorporating said semiconductor elements, the interconnection pattern of the logic means being controlled by said state pattern. ≤ Preferred embodiments enable loading of a memory or logic array to take place without interruption of use of the memory or array. That is, where binary information is being continually read from a memory by electrical addressing, "optical updating" by changing the mask can occur simultaneously, data currently stored in the memory being read out while a new mask is put in

5 position. Reading of the memory can be stopped so that the new data can be loaded into the memory by irradiating it via the new mask with a pulse of radiation.

According to a second aspect of the present invention there is provided an apparatus comprising an

»c integrated circuit semiconductor memory having a plurality of transistor elements which include regions sensitive to radiation to control the state of said elements; and a mask which is manufactured separately from said semiconductor memory so that it is not ^^'integrated therewith, the mask having a pattern of radiation more transmissive and less transmissive regions representing a state pattern to be loaded into the device and being fixed with respect to the semiconductor memory in such a position that said state pattern can be loaded ic into the device by irradiating the memory via the mask.

In this case, alignment of the mask is carried out as part of the manufacturing process. This enables a plurality of standard semiconductor chips to be manufactured, with the addition of a mask to each chip s≤ enabling "personalisation" according to individual manufacturer's requirements.

In one embodiment, in the case of the DRAM discussed above, one can pre-charge all the storage nodes, and subsequently, due to exposure of the chip to a

-c light pattern, very quickly and in parallel discharge those nodes which are exposed to light by the pattern. The effect of light is to discharge a charged capacitor.

The light will enhance the rate of charge decay by orders of magnitude. When, after a suitable exposure

^'i'-»^'.time, the memory is read, the illuminated bits will be "0" and the rest will still be "1". ■

Another type of memory.which is suitable is the reprogrammable ROM. The information in these devices is written in the form of an insulated gate field effect transistor (IGFET) threshold voltage shift. They have special gate insulator structures such as double 5 dielectric layers at the gate or a floating gate buried into the gate dielectric. The special gate insulator provides trapping centres for permanent charge storage either at the double dielectric interface or in the floating gate. Charge can be transferred to these gates ιc by channelling effects, hot electron effects or similar mechanisms based on relatively high voltage or current pulses thereby shifting the threshold voltage. In the normal operating regime, no charge is transferred to or from these trapping centres and the device behaves as a -- 15^" ROM. The charge transfer in some ROMS is reversible by applying a high pulse of opposite polarity but more often it is not reversible electrically. In the latter case, ultraviolet light is used to excite the carriers in the floating gate sufficiently that they can tunnel back. .20 This is^* done to erase the memory. In accordance with an embodiment of the invention, loading of the memory can be carried out by precharging all the storage nodes followed by selective erasure of the memory by irradiating it via a mask.

2→ In order to change the data to be loaded into the memory, or the state pattern to be loaded into the logic array, the mask can be removed and replaced, according to the first aspect, by an alternative mask or by a combination of two masks one above the other as described

^■.c hereinafter. As an alternative to this, the information carried by the mask itself could be altered in the first and second aspects.

Thus, according to a third aspect of the present invention, there is provided an apparatus comprising an is integrated circuit device; and a mask fixedly mounted with respect to the device and having a plurality of regions whose^'transmissivity to radiation is alterable to provide more transmissive and less transmissive regions to form a pattern representing a set of digital information to be loaded into the device, said mask being positioned with respect to the device so that any one of

5 a plurality of different sets of digital information can be loaded into the memory by altering the alterable regions of the mask accordingly, and by irradiating the device through the mask.

The device may comprise a memory having an array

^■■c of radiation sensitive regions by means of which the state of storage locations of the memory can be altered by irradiating said regions. In this case the mask is positioned with said alterable regions corresponding respectively to said radiation sensitive regions.

\≤ Preferred embodiments of this aspect of the invention enable fast loading of a memory to occur. This overcomes the problems associated with the loading of the currently available memories, which may have storage capacities of 500 Kilobit or 1 Megabit. It is a_*>particularly useful where a memory 'forms part of a processor or overall computing circuit and is to be used in an on-line situation in which it is intermittently to be reloaded with information to permit a fresh computation or fresh set of data to be available. In

5 such situations, where the memory device forms an integral part of the processor or other computing circuit, any down time of the memory dictates the total down time of the processor and associated circuitry, since while the memory is being loaded or up-dated o electrically it cannot be used in the on-line mode as part of the processor or computing circuit. In contrast, where the memory is loaded by irradiating via a mask,^' the down time is substantially reduced.

Moreover, using a mask of a type having more and → less transmissive portions and non-coherent light, a simpler and cheaper arrangement is provided than a switchable hologram system using a laser. Further, if the mask is non-volatile at the operating temperature of the chip, that is it retains a state pattern written into it at that temperature, the device can function conventionally provided that a light

≤ source for irradiating the chip via the mask remains off, .and indeed may be a chip packaged in a DIN mounting so as to be pin-to-pin compatible with existing chips. When required, the light source can be activated to parallel load the state pattern carried by the mask in parallel ιo into the device. The state pattern of the mask can be changed by altering the temperature and addressing the mask to alter selected ones of the alterable regions whilst the device is operating with its existing data content. It will be appreciated that while reference is made to MOS transistors of a DRAM and IGFET transistor of a ROM, embodiments of the invention may be used with arrays of any suitable transistor, e.g. FETs and bipolar transistors.

^•2c Any of the above described masks can.be arranged in any convenient manner for example:-

1. A mask may be located remote from the semiconductor surface, the light pattern therefrom being focussed onto the surface of the memory using an optical

2S" lens system or the like.

2. The mask can be formed directly at the surface of the memory so that light incident on the mask can illuminate selectively the radiation sensitive regions below the mask, depending on the particular electrical

So signals supplied to the mask controlling the opacity or transmissivity of the mask in different regions.

3. The mask can be located in close juxtaposition, to the memory in a light tight housing with the alterable regions of the mask aligned with the radiation sensitive

^■i_^~ regions of the memory. The term "light tight" is used to denote a housing which does not permit external radiation to irradiate the memory. To obviate cross-talk a further mask may be interposed between the first mask and the integrated circuit to provide radiation transmissive passages to respective sensitive regions. z> Where the device needs to be fully exposed to radiation before irradiation via the mask, means may be provided for so irradiating the surface of the device before exposing the surface via the mask. In one arrangement material of the mask may be frequency o sensitive so that it is opaque at one frequency of electromagnetic radiation but sufficiently transmissive at a second frequency of electromagnetic radiation as to cause the entire surface of the device to be subjected to electromagnetic radiation at the said second frequency. is For example by exposing a memory, via the mask, to radiation at the second frequency before exposure to radiation at the first frequency, all of the storage locations within the memory will be exposed, so that subsequent exposure to a state pattern using radiation of

9J3 the first frequency will result in appropriate electrical discharging at the desired storage locations.

A wide spectrum radiation source may be used with this type of mask such that radiation in one range of frequencies can pass therethrough whilst radiation in a

^^"different frequency range is unable so to do, and means may then be provided operable in response to electrical signals to introduce a filter between the source of radiation and the mask to restrict the incident radiation to that of the second mentioned frequency when the state

^*.& pattern is to be loaded into the semiconductor device. In another form the opaque (less transmissive) regions of the mask may be polarization sensitive so that electromagnetic radiation polarised in one particular orientation can pass but radiation oriented in other l ~ directions will be prevented from passing. The whole device is exposed to unpolarised light or to light polarised in the passing direction. Subsequent selective exposure is achieved by irradiating the device via the mask by light polarised in a direction perpendicular to the passing direction.

In this case, the mask may be made of a material

5^" which is normally polarised in one direction only and in which the application of electrical signals to the material can identify selectable regions to alter the polarisation orientation thereof so that if the mask is illuminated with light polarised in the one orientation,

^*ιc regions in which the polarisation orientation has been changed will not enable incident radiation to pass therethrough to the surface of the device. It will be seen that in this event, the device can be fully illuminated over the entire area (as a prelude to

^selective exposure of the device) by subjecting the mask to unpolarised radiation.

The mask may alternatively be such that the refractive index of the material forming the mask can be changed/by the application of electrical signals or other x → means so that the light transmissive properties of different regions within the mask can be changed by altering the refractive index of the regions to cause selectively either divergence of electromagnetic radiation incident thereon or total internal reflection is^" to occur.

According to a fourth aspect of the present invention there is provided a method of loading information in the form of a two-dimensional image into a memory of an integrated circuit device, the memory having

^o a plurality of radiation sensitive regions by means of which the state of the storage locations of the memory ' can be altered by irradiating the said regions the method comprising projecting the image onto the memory reduced in size so that the information is loaded into said

→≤ memory by irradiation of selected ones of the radiation sensitive regions.

The image may be formed by illumination through a transparency, a lens forming the size reduction. In another form the image may be the output of an optical computer, for example as discussed in "Digital Optical Computing", Sawchuck and Strand, Proc. IEEE Vol.72, No. z> 1 , July 1984. In this case no image reduction would be required. For the purpose of the present text, an optical computer may be defined as a device for performing optically numerical computations on n dimensional data that are generally not images.

*o Thus according to a fifth aspect of the present invention there is provided in combination an optical computer for providing an output in the form of a two dimensional image representing a state pattern; and an integrated circuit semiconductor device having

»s^" a two dimensional array of radiation sensitive regions for controlling the state of semiconductor elements of the device, the device being arranged to receive the output of the optical computer whereby the state pattern is loaded into the device.

-**- According to a sixth aspect of the present invention there is provided in combination an integrated circuit semiconductor memory having a plurality of storage locations, each location comprising a transistor responsive to incident radiation to control the

2ώ^' information stored at that location, and a mask having an opaque layer with apertures corresponding respectively to said location and dimensioned so that on irradiating the opaque layer of the memory, radiation reaches a major portion of the transistor of those locations via their lc associated apertures.

With this arrangement, the manufacture of the opaque layer is made simpler, due to the aperture size, than the case where a small aperture is provided to illuminate only a small portion of the transistor.

^Further, more radiation reaches each cell than with a small aperture. Moreover,, this aspect can be implemented using current DRAM chips. According to a seventh aspect of the present invention, there is provided a computer system comprising: an integrated circuit memory having storage S locations whose state can be controlled in response to incident radiation; an image forming device comprising a source of radiation and a mask having a two dimensional array of regions corresponding respectively to said storage ^locations, each of which regions is alterable between a more transmissive and a less transmissive state thereby to form a pattern representing a set of digital information to be loaded into the memory; means for actuating the source of radiation to is^" irradiate the memory via the mask to cause the information represented by the pattern to be loaded into the memory; and means for controlling the image forming device to alter the pattern, so that on subsequent irradiation a ■3^further set of digital instructions is loaded into the memory.

The image forming device may be part of a machine including the memory, or it may be in another machine, whereby one machine can communicate with another. ^ For a better understanding of the present invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:-

Figure 1 illustrates diagrammatically a system →c, according to one embodiment of the present invention;

Figure 2 shows a computer system using the system of Figure 1;

Figure 3 illustrates the electronic structure of a dynamic random access memory; → Figure 4 illustrates a typical semiconductor structure of two cells of a dynamic random access memory, with a mask diffused thereon; Figure 5 illustrates a semiconductor structure as shown in Figure 4 except that the mask has been manufactured separately and subsequently bonded to the memory structure; 5 Figure 6 illustrates a mask and memory structure which is the same as that of Figure 4, except that the mask has regions which are alterable so as to be more or less transmissive to radiation;

Figures 7a to 7c illustrates assembly steps of a \c "mask module" and Figure 7d illustrates such a module;

Figure 8 illustrates a chip holding structure with a memory chip;

Figure 9 illustrates a device for locating the mask module relative to the chip; Figure 10 illustrates another system for transferring the data carried by a mask onto a semiconductor chip, the mask being carried by a card rather than in a mask module;

Figure 11 shows one system for aligning the state OJC- pattern on the mask with the memory on a chip;

Figure 12 shows a light source, an alterable mask, a lens and a chip fixed in a light tight housing;

Figure 13 shows a package containing a chip carrying two masks, the first being fixed and the second 2S~ being alterable;

Figure 14 illustrates a form of optical grating which may be used to generate Moire fringes;

Figure 15 shows a structure similar to that of Figure 5, having two masks, both of which are alterable ^to enable logic functions to be performed;

Figure 16 shows diagrammatically a system using an alterable mask as a nonvolatile buffer;

Figures 17a and 17b illustrate possible arrangements for 4 x 4 data and logic masks; ^ Figure 18 illustrates diagrammatically the loading of a chip from the output of an optical computer; and Figure 19 is a diagram illustrating another- form of alignment;

Figure 1 shows a VLSI integrated circuit semiconductor device 10, e.g. a DRAM, which has an array of selectively addressable regions or storage locations

Vindicated diagramatically by the square boxes.

A mask 14 is provided, having a pattern of light and dark zones corresponding to a set of digital information to be loaded into the memory. Collimated light 12, from a light source (not shown) and condensing '• lens 34, is projected^* through the mask 14 and through a reducing lens 16 onto the device 10 to irradiate selected ones of the addressable regions. The condensing lens serves to focus an image of the light source onto the reducing lens: it is not always necessary to provide

^•• collimated light.

While a single reducing lens is shown, a two dimensional array of lenslets, having dimensions of the order of microns may be used to focus light onto each location of the device 10. Manufacture of such lenslets is discussed in "NEC Develop New Technology to improve CCD sensitivity": Monitoring Japanese Science: Technical Report Rg. No. Scan 2504, Reporter: M. Kodera.

Radiation impinging on the selected location controls the state of information stored at that

■22^" location. Thus, the information represented by the pattern on the mask is loaded into the device. Position sensors 18, 20 for ensuring the required registration between the light pattern and the device 10 are provided. These are preferably constituted by optical gratings o generating Moire fringes.

Moire fringes may be generated by aligned optical gratings with a fixed line spacing to indicate relative movement between two surfaces carrying the gratings. In order to use Moire fringes to indicate the position of

IS^"one surface relative to another, circular optical gratings such as that shown in Figure 14 can be used, one on each surface. The spacing of the lines decreases towards the outer edge of the circle. Two such gratings, superimposed one on the other, generate a series of bars, the spacing of which indicates in which direction the surfaces should be moved relative to one another - the

S wider the spacing, the closer the gratings are to a perfect alignment. With the gratings perfectly aligned, the bars disappear. As an alternative to circles, two one dimensional gratings with an aperiodic line spacing disposed at 9O⁰ to each other can be provided in each

'"o surface to achieve a similar effect (Figure 1).

Figure 2 illustrates a computer system which is conventional apart from the addition of a nonvolatile buffer 60 to be described in more detail hereinafter. The system has a microprocessor 62 which communicates via

\≤ a bus 64 with conventional ROM address, RAM address and I/O port address circuitry 66, 68, 204. Also connected to the bus 64 is direct memory access control logic 206. Other components will communicate with the bus 64 as in a conventional computer system, but these are not shown• for

Λothe sake of clarity. ROM 70, RAM 72, I/O port 208, and DMA control logic 206 comprise a plurality of semiconductor chips, one or more of which may be a device such as 10 (Figure 1) associated with an arrangement as described with reference to Figure 1. This is possible

2s~ since the device 10 of Figure 1 may be a pin-to-pin-compatible conventional integrated circuit chip. For example, in the I/O port 208, the chip may include a register for storing data. In addition a cache RAM 210 is shown communicating directly with the

^*_<-> microprocessor 62: this RAM may also include a device such as 10 in Figure 1. The cache RAM 210 may be replaced by a memory management unit. In the case of the ROM, and DRAM it is only necessary to provide a flash of light sufficient to load the state pattern into the chip:

^'& for a DRAM the memory contents can thereafter be refreshed using conventional DRAM refreshing techniques. Figure 3 illustrates one form of structure of the DRAM of Figure 1. Four cells or storage locations, 1 to 4, of the multibit array, e.g. IMbit, are shown in Figure 3. Each cell has a transistor T1-T4 and a storage capacitor Cl to C4. Initially, e.g. on power-on of the 5" computer, all the transistor cells will be set to "1" to charge the capacitors. Irradiation of any one of the capacitors will cause it to discharge, changing the state of digital information stored at that location from a "1" to "0". The transistors have their sources connected in \c rows to buried bit lines, and their gates connected in columns to word lines.

The light flux required on one cell to effect the necessary discharge to write the device can be calculated for a 1Mbit DRAM as follows. S Below is given a list of typical numerical values:-

C = 50fF storage capacitance

V = 5V logic swing lambda = 600nm (illumination w _*avelength)

*° eta = 0.5 (quantum efficiency)

The photocurrent has to discharge:-

CV = .25pC = 1,560,550 electrons

It therefore requires 1/eta times this number or

3,121,099 photons. 25^" The energy quantum of a 600nm photon equals

0.329aJ.

Thus an optical switching energy of 1.03pJ is required.

We may compare this figure with the electrical 2 energy dissipated during the discharge, being:-

CV²/2 = .625pJ.

With a switching energy overhead of 165%, this . switching mechanism can be described as reasonably effective, in fact more effective than any electronically →≤ addressed switching in this size of array.

The switching energy of 1.03 pj is actually the power-delay product of the gate or memory cell. The lightflulxx nneecceessssaarryy ttoo aacchieve a write time t is at least:-

For the complete 1 M bit array, the (write)

≤ power-delay product is therefore 1.03 uJ. Since the power needs to be limited to 1 W maximum, a loading cycle time of 1 MHz is achievable. A complete memory update can be carried out in 1 us. Therefore, the data rate for writing to the memory is 1 Tbit/s. ^ιC The values given above are examples of one form of DRAM. Using a 1 Mbit DRAM with 3D Stacked Capacitor Cells, values of capacitance up to 75fF may be attained.

Figure 4 illustrates a typical dynamic RAM structure having a p-type substrate 5 with n- and p-type

^•.5^" regions diffused therein to form cells 1, 3. The storage capacitors Cl, C3 are formed by polysilicon plates 6, 7. The plates 6, 7 are shown "floating" but will be grounded by suitable connections. The substrate 5 carries two SiO layers.8, a metal layer 9 forming the word line, and

A. a further silicon dioxide layer 11. A mask in the form of an opaque layer 13 is deposited over regions of the chip as the final layer. The mask has holes 15 corresponding to selected locations of the memory for allowing a radiation source to irradiate the storage ϋ' transistor and capacitor of those memory locations which are to be discharged. The holes are dimensioned to enable radiation to irradiate a major portion of the transistor and associated capacitance e.g. at least 75%, not just the capacitance. Other memory locations are

'ic screened by the opaque layer.

Figure 5 illustrates part of a memory chip having the structure as shown in Figure 4, but in which a two-dimensional mask 18 of self-supportng material has been manufactured separately and subsequently bonded to

3≤ the semiconductor chip. The mask has more transmissive and less transmissive regions, such as are shown at 19 and 21 respectively. It may be a photographic transparency. By arranging for the mask to be manufactured separately from the chip, there is no need to manufacture the mask under the strict conditions in which the chip is manufactured. Further, it provides the ζ manufacturer with the opportunity to construct several identical semiconductor chips, the mask for each chip then being made separately and according to the requirements of a particular customer. The mask can then be bonded to the chip to "personalise" that chip for the ic customer.

In the two cases described above, the state pattern to be loaded into the semiconductor device is clearly unalterable once the mask layer has been deposited onto the chip, or bonded onto the chip as the

Figure 6 illustrates the chip and mask arrangment of Figure 5 with the important difference that the mask -28 is such that it has alterable regions 29, 30 which can be made more or less transmissive to radiation in

-I-.response to signals which may be optical or thermal and electrical. For example, the mask 28 in Figure 6 may be a spatial light modulator (SLM) having a two-dimensional . array of alterable regions, two of which are shown at 29 and 30. In one form, an optically addressed SLM as

-is^' described in SPIE Vol. 465 Spatial Light Modulators and Applications (1984), these alterable regions then each have a membrane which can adopt a relaxed or extended position to transmit or reflect light respectively. Other forms of construction of suitable spatial light

-c modulators are described for example in Optical Engineering Vol.22, No.6 November 1983.

.. - As an alternative a liquid crystal display (LCD) can be used, preferably a non-volatile LCD display. Suitable LCDs are those of the type which cannot be S written to at room temperature, but which must first be heated and then electrically written to. If allowed to cool, "they will retain the state pattern written into them. One form of LCD is such that it can be written by applying a potential difference across its cells, for example using transparent electrodes disposed above and below the display, and subsequently heating those regions S of the LCD whose state is to be changed. The state patterns will remain in the LCD if the voltage is applied for sufficient time to hold the state change while the LCD is cooled. As an example, a suitable LCD for the present application is that described in the articlee ιo entitled "A 4 Mpel Liquid Crystal Projection Display addressed by Gallium Arsenide laser array", in the 82 Digest of the Society of Information Display from IBM General Products Division, pages 240 and 241. Another form of liquid crystal array may include electrically

\≤ addressable liquid crystal light valves such as described in "Silicon liquid crystal light valves : States and Issues", Efron et al, Optical Engineering Nov/Dec. 1983, Vol.22, No.6, pps 682-685.

Using this embodiment of the present invention, A*> the state pattern to be loaded into the semiconductor device can be altered by addressing the mask 29, as illustrated diagrammatically by arrow 31 in Figure 6, to change the transmissivity state of the alterable regions such as 29, 30, e.g. via conventional memory addressing

^circuits, such that these circuits and the mask constitute buffer memory 60 of Figure 1.

As an alternative to depositing an extra layer onto a semiconductor chip to form a mask, or to bonding a separately manufactured mask to the chip, the mask can be

3.c held separately from the chip. Where the mask carries a fixed state pattern that is it is non-alterable, the mask can be held in an exchangeable "mask module". Figures 7a to 7c illustrate assembly steps for making such a mask module, and Figure 7d is a perspective view thereof. Figure 7a shows a mask 32 about to be sandwiched between two transparent acrylic covers 33, 34. The mask 32 carries a state pattern in the form of opaque and translucent [less transmissive and more transmissive] regions. In this form, the mask may be a photographic transparency. The mask 32 is provided with an alignment point 35. The layers 32, 33, 34 are laminated together

≤ to form a mask structure generally denoted 36 [Figure 7b]. The mask structure 36 is supported by a cylindrical support 37. An alignment point 38 in the support 37 is used, with the mark 35 on the mask, accurately to position the mask structure 36 relative to the support ιo 37. An automatic position control system [not shown] can be used to manipulate the mask structure 36 to the desired position. When the mask structure 36 has been accurately positioned, a cover 38 is welded onto the support 37 to form the mask module shown in Figure 7d.

^ A semiconductor chip 40 (Figure 8) is mounted to a chip holding structure 41, the chip holding structure having external dimensions such as to provide a sliding fit within the mask module so that it can be aligned therewith as shown, by dotted lines, in Figure 9. Figure

Λc 9 illustrates a housing 42 carrying the chip supporting structure 41 and having a light source 43. In order to load the state pattern carried by the mask 35 into a memory or logic array on the chip 40 the mask module is pressed into the housing 42 against the action of a

__r spring 43 by movement in the direction of arrow A at the same time as a spring-biased dust cover 44 is urged away from the chip holding structure 41 by the module. The spring 43 serves to urge the mask module into position over the chip holding structure 41 so that the mask is

-io aligned with the chip, the module having a sliding fit with the chip holding structure. By charging the cells

:. of- the memory of the chip and then illuminating the chip via^" the mask, the state pattern carried by the mask is loaded into the chip. It is apparent that a different Tstate pattern can be loaded into the chip by simply removing the mask module and replacing it by a further mask module supporting a mask carrying a different state - - pattern .

As an alternative to spring loading, other forms of mechanical alignment can be carried out, i.e. three coplanar V grooves, preferably directed to a common point 5 on, say, the chip, or its mounting and three pegs on the mask module which can engage those slots. An alternative is the so-called Kelvin support where three pegs are located respectively by a tetrahedral hole (sometimes approximated by a conical hole), a V groove (probably ic directed at the hole) and a plane surface. Either of these provides the six constraints which are necessary and sufficient to determine the relative positions of two rigid bodies. For convenience in use the memories or logic arrays are adjusted to a specific relationship to

^■i" one part of the chip holding structure and the mask is manufactured in a specific relation to the mask module.

As an alternative to the mask module described above, a mask 35' could be carried by a relatively rigid card 46 as shown in Fig. 10, the state pattern carrying

Ac portion of the mask being fixed in a precise position relative to two of the edges of the card. This arrangement is suitable where the mask is several times, e.g. about 10 times, larger than the chip. The card is then slotted into a chip holding structure 47 in which a r chip 48 is supported with its memory or logic array in a known position relative to the structure. The card is received in channel portions 47a and 47b, portion 47b being spring loaded, as diagrammatically shown at 47c, to urge one of said two edges against the base of the

^'io channel of channel portion 47a, which base defines a first accurately positioned surface of the structure. Spring means 47d urges the second of said edges against a surface 47e which is a second accurately positioned surface. A lens 49 is located between the chip and the - ^~ mask in such a position as to focus light from a light source 50 via the pattern carried by the mask onto the chip. The lens effects a suitable size reduction for the pattern. As a result of the image reduction e.g. 10:1 it can be seen that a required tolerance in chip/mask alignment of for example -+ 3 urn is increased to + 30 μm when setting the mask within the card. Once the chip 48 5 has been fixed relative to said two accurately positioned surfaces of the chip holding structure 47 at manufacture, no further adjustments are required. Here, different state patterns can be loaded into the chip by replacing one mask-carrying card for another.

^1c The above described methods of alignment are suitable for cases where only a few masks are to be interchanged, and where a strict tolerance on both the mask and the semiconductor device on chip is acceptable. For cases where a large number of masks are to be

'"a interchanged, and where, as a consequence, it is required to impose minimum additional manufacturing tolerances on the mask, the following alignment methods can be used.

One suitable arrangement for loading into a semiconductor device a state pattern carried by a mask in r~ a mask module is shown in Figure 11. Here, the module casing 37 carrying the mask with the pattern to be loaded into the device on a chip is located in a holding structure 51 which is mounted to a PCB 52 carrying the chip 53. The holding structure 51 has a lens 54 and a x movable mirror 55 mounted therein, movement of the mirror about mutually orthogonal axes being carried out by two d.c. servo motors 56, 57 driving micrometer screws. The structure 51 has a door 58 carrying a light source 59, the door being shown in its open (full line) and closed

2>c (broken line) positions. With the door closed, and the light source 59 activated, light is focussed onto the chip 53 via the mask 35, lens 54 and mirror 55. To align the state pattern with the device, e.g. a memory array into which it is to be loaded, the following arrangement i'-" may be adopted.

An array of features is provided on the mask 35 e.g. a linear array of opaque and transparent blocks, preferably of a pitch which cannot be confused with that of the state pattern carrying portion of the mask. The pattern may be read by photodetectors incorporated in the chip. The detectors may be distinct from and

≤ geometrically separated from the memory array, or specific cells of the array may be designed to respond to the illumination pattern of the linear array of features. Signals from detectors or cells are fed to a control system 300 to control the motors 57, 58 until the pattern

>o is correctly aligned. In another form of alignment system shown in Fig. 19 the memory or logic array has two or more small areas 30Zcfnigher reflectivity than the remainder to be aligned with respective ones of two small transmissive areas 304 of the mask, e.g. two small holes. is In this case light 305 is projected through the mask onto the array, and the light reflected back from the highly reflective areas on the memory can be detected through the holes 304 in the masks by suitably positioned detectors 308 mounted in the module. Details of the Ao module and chip holding structure are^" omitted for the sake of clarity.

In a further arrangement, suitable for correctly loading an actual size mask in near contact, any misalignment is measured at at least two points. The ___»^*• very small distance between the mask and the chip, and rotations about axes parallel to the plane of the chip may be adjusted mechanically. Translational movements in the plane of the chip may be monitored at one point, and rotation about that point monitored at the second point.

→c However, searching for a point is time consuming as its position is uncertain in two dimensions, whereas a line can be found by a one dimensional search. An advantageous system thus has a linear feature on the chip and/or the mask. The first stage of the search is by "Si^" motion nominally perpendicular to that line. When the line has been found, a search is carried out along the length of the line to find a defined point on the line. such as one end. Alignment is completed by rotation about that point to locate a second point on the line which may be the other end of the line. The line is not necessarily continuous, but may be a series of marks and -^~ spaces, as described earlier, such marks and spaces may be arranged to indicate position along the line, this information enabling a control system to traverse more quickly to the end of the line.

When a larger mask is used and the optical

^••c* reducing lens is fixed with respect to the chip it will again be easily possible to align the mask at the correct distance from the memory, and parallel to it, mechanically. Alignment of the mask in its plane may again be performed with an array of features. In that Ucase, if the linear array is monitored by elements of the memory array, the technique will be the same in detail as for the near control case. If separate detectors or mirror features are provided, they will be more conveniently arranged immediatel ^■ adjacent the plane of .

Ao the mask.

Figure 12 shows a light tight housing 37 containing a chip 76 carrying an integrated circuit memory or logic array, a lens 78, a mask structure 80, [similar to that described in Figure 7a but including an in alterable mask 82] and a light source 84. The addressing circuitry for the alterable mask 82 is not shown in Figure 12. For this, reference is made to Figure 16 which illustrates diagramatically a similar system with a chip 86 carrying an array of transistor cells an

"ϊc alterable mask 88 and a light source 90. No lens is shown in Figure 16, which is a diagrammatic representation only. Clearly, for a system similar to that ^"of Figure 12 a lens would be required whereas, where the dynamic mask is bonded directly to the chip (as in

^'i Figure 5), no lens would be required. One application for the alterable mask as arranged in the diagram of Figure 16 is as a non-volatile buffer, for example that designated 60 in Figure 2. By using as the alterable mask a liquid crystal panel formed of a material having a resp^'onse time which is long compared with the time for which a state pattern is to be carried by the mask at the

≤ relative operating temperature a mask can be made in which any pattern, once established, will persist for a useful length of time. As described earlier with reference to Figure 5, such a mask may be made with a pair of transparent electrodes to which a voltage can be ic applied to tend to drive the liquid crystal material to one optical state. The liquid crystal material is then heated sufficiently to allow it to attain that optical state, and is subsequently allowed to cool. A voltage [which may be zero] is then applied to tend to drive the is^" liquid crystal material to the opposite optical state, but, as the liquid crystal is cool, no change occurs. The mask is then scanned by a modulated laser beam, which causes a change of optical state where it strikes the material,to produce a mask with .more or less transmissive

SJ- regions which will remain so without refreshment until they are altered again.

Another example of a non-volatile mask is a magneto optic mask which comprises a two dimensional array of small garnets. A matrix of wires is associated ι~~ with the array of garnets and is such that when a current of a certain magnitude is carried by one of the wires associated with one particular garnet, no change occurs. When that current passes through both the wires associated with that garnet, a magnetic field is produced

'io which is strong enough to change the optical state of the garnet. This enables each garnet in a two dimensional array to be written in turn, and that data will remain until overwritten. This is described further in "Two-dimensional magneto optic spatial light modulator

"S for signal processing" : ROSS, W.E. SPIE Vol. 341 Real Time Signal Processing V (1982) pps 191-198.

Thus, the mask can act as a buffer memory, storing data in the form of a state pattern written into a non-volatile mask. The mask can be located over one of the chips of the ROM or RAM (see figure 2), and will cause the data represented by the state pattern carried _^" by the mask to be loaded into that chip when it is illuminated. The buffer can be addressed from the address line connected to the conventional RAM circuit 68. Once the data represented by the state pattern carried by the mask has been loaded into the chip, the

>^c source of illumination can be turned off, and the mask can then be rewritten with a fresh set of data which can be loaded into the chip with a fresh pulse of radiation.

In Figure 13, there is illustrated a chip carrying two masks, the lower 92 of which is a fixed mask having S^" an array of radiation transmissive regions, which may simply be apertures in an opaque layer, each aperture 96 corresponding to one cell of the integrated circuit array so that a major portion of the transistor in that location is exposed. The upper mask 94 is an alterable

- mask whose alterable regions are aligned with the apertures 96 of the fixed mask 92. This arrangement eliminates any cross talk which might otherwise occur, that is illumination of one cell by radiation intended for its neighbouring cell. ^s Figure 13 also diagrammatically illustrates an I C package 200 in section, showing a form of illumination which may be used with the arrangements of Figures 4, 5 or 6. In this system, a layer of radiation diffusing material 98 is formed over the upper mask 94. The layer 98 may be illuminated at its edges by a light emitting diode (LED). The resulting chip is pin to pin compatible with existing chips, in that the light emitting diode is controlled by an AND gate 201 on the chip and responsive to a unique combination of signals on signal lines _T conventionally provided on the chip. Clearly, the combination selected to turn the LED on or off will be one which does not normally occur in conventional operation of the chip.

Figure 15 shows a structure similar to that of Figure 13 except that both upper and lower masks 100, 102 are alterable and can be addressed by conventional matrix

5" addressing circuitry via busses 104 and 106. This arrangement enables logic operations to be performed in parallel, and the results to be loaded directly into the integrated circuit. One of the masks serves as a logic mask, and the other as a data mask. They can be in io contact and bonded to the chip as shown or can be bonded to each other and separate from the chip, or imaged one onto the other and subsequently onto the chip using suitable lenses. A four by four representation of a portion of the mask is shown in Figures 17a and b. The

\≤ data mask is coded as shown in Figure 17a according to two binary inputs. A logic mask is then set at one of 16 possible combinations as shown in Figure 17b corresponding to the sixteen possible logic operations on two binary inputs. The combination of the data. and logic.

Ha masks will only transmit light if the logic function is true for that data combination. More details on combinational logic with Liquid Crystal Light Valves is discussed further in the article entitled "Digital Optical Computing" referred to earlier. In contrast with ≤ the arrangements discussed therein for storing logic results, e.g. optical feedback loops, in the present case the output from the masks is loaded directly into the memory.

Figure 18 illustrates diagrammatically the loading

-e. of an integrated circuit device 310 from an optical computer 312. A focussing arrangement may be provided where necessary. For example, a two dimensional array 314 of lenslets is formed at the surface of the device 310 to focus radiation from the computer 310 onto the

^o device. Clearly, any other suitable means for focussing the radiation may be used.

Industrial applicabilty In addition to the applications described above, there are many other applications to be considered.

For the first aspect of the present invention, with the removable mask, masks could be manufactured

_f carrying databases to be loaded into memories to provide equivalents to PROMS or EPROMS. As an alternative to conventional ROM cartridges, an optical mask could be used to distribute software and databases for use with computers . ^c As regards aspects of the present invention where information loaded into an integrated circuit device is derived from an alterable mask or two dimensional image, there is an application in chip design, e.g. state patterns for gate arrays could be programmed and tested

\≤ during production. When proven, the pattern could be copied onto a fixed-pattern mask for quantity production.

However, an important industrial application of the present invention is in the fast loading of currently available VLSI semiconductor devices.

Claims

1. An arrangement comprising: an integrated circuit device; and a mask having a pattern of radiation more transmissive and less transmissive regions

≤ representing a state pattern to be loaded into the device, the mask being removably mounted to a holding structure fixed with respect to the device so that the mask can be positioned with respect to the device to enable said pattern to be loaded into the device by to irradiating the device via the mask, the arrangement including alignment means for use in positioning the mask with respect to the device so that the mask can be removed from the structure and replaced by a further mask carrying a different state pattern and being similar to ■^ the first mask in so far as the alignment means are capable of use in positioning the further mask with respect to the device to enable the different state pattern to be loaded into the device.

2. An arrangement as claimed in claim 1, in which ^othe alignment means comprises a first alignment element at a predetermined position relative to the mask, and a complementary, second alignment element at a predetermined position relative to the device.

3. An arrangement as claimed in claim 2, in which 2 the first alignment element comprises a first optical grating, and the second alignment element comprises a second optical grating, the first and second optical gratings each having an aperiodic set of lines, whereby the gratings are cooperable to generate a plurality of Jo fringes by means of which the position in which one optical grating is aligned with the other can be located.

4. An arrangement as claimed in claim 2,.in which the first and second alignment elements comprise respective abutment portions, there being means for

3-T urging one of the abutment portions into contact with the other, thereby to align the mask and the device. _ -

5. An' arrangement as claimed in claim 4, in which the mask is carried by a carrier member and in which the abutment portion of the carrier member is an internal cylindrical surface thereof and the other abutment

≤ portion is an external cylindrical surface fixed with respect to the device and dimensioned as a fit within the carrier member.

6. An arrangement as claimed in claim 4, in which there are first and second linear abutment portions at an

\o angle to one another and fixed relative to the mask, and third and fourth linear abutment portions at the said angle to one another and fixed relative to the device, the urging means being arranged to urge the first and third regions together and the second and fourth regions together to align the mask and device.

7. An arrangement as claimed in claim 1, in which the alignment means comprises: an alignment array provided on an integrated circuit incorporating the device and fixed with respect to the holding structure; o means for sensing that array via the mask; and means responsive to the. sensing means for moving the mask relative to the integrated circuit thereby to align the mask and the device.

8. An arrangement as claimed in claim 1, in which ≤ the alignment means comprises: an alignment array provided on a member carrying the mask and fixed with respect to the state pattern; means provided on an integrated circuit incorporating the device for sensing that array; and means responsive to the sensing means →o for moving the mask relative to the integrated circuit thereby to align the mask and the device.

9. An arrangement comprising an integrated circuit including a semiconductor memory having a plurality of transistor elements sensitive to radiation

35^"to control the state of said elements; and a mask which is manufactured separately from said semiconductor memory so that it is not integrated therewith, the mask having a -31 - pattern of radiation more transmissive and less transmissive regions representing a state pattern to be loaded into the memory and being fixed with respect to the semiconductor memory in such a position that said

_- state pattern can be loaded into the device by irradiating the memory via the mask.

10. An arrangement as claimed in any preceding claim in which the mask comprises a photographic transparency.

'°

11. An arrangement comprising: an integrated circuit device; and a mask fixedly mounted with respect to the device and having a plurality of regions whose transmissivity to radiation is alterable to provide more transmissive and less transmissive regions to form a is- pattern representing a set of digital information to be loaded into the device, said mask being positioned with respect to the device so that any one of a plurality of different sets of digital information can be loaded into the memory by altering the alterable regions of the mask

ΛOaccordingl , and by irradiating the device through the mas .

12. An arrangement as claimed in claim 11, in which the mask has been manufactured separately from the circuit device and has been subsequently bonded to the

__»' surface of the device.

13. An arrangement as claimed in claim 11 or 12 in which the mask comprises a two dimensional array of liquid crystal regions.

14. An arrangement as claimed in claim 11 or 12 > in which the mask comprises a spatial light modulator.

15. An arrangement as claimed in any of claims 11 to 14 in which the mask is non-volatile.

16. An arrangement as claimed in any of claims 11 to 15 in which the mask is electrically addressable to _l_r alter said regions.

17. An arrangement as claimed in any of claims 11 to 15 in which the mask is thermally addressable to alter - 32 - said regions.

18. An arrangement as claimed in any of claims 11 to 17, in which the regions of the mask are alterable to provide more transmissive and less transmissive regions ζ to radiation at a first frequency, said regions being transmissive to radiation at a second frequency whereby all of the device can firstly be irradiated with radiation at the second frequency, and selected regions of the device can subsequently be irradiated by radiation

.- at the first frequency.

19. An arrangement as claimed in any preceding claim which comprises at least one further such mask disposed between the first mentioned mask and the memory or device, as the case may be, whereby logic operations is^* can be performed and the results loaded directly into the memory or device.

20. An arrangement as claimed in claim19, in which the or at least one of the further masks has alterable regions.

^■2o 21. An arrangement as claimed in any of claims 1 to 8 or Ho 18_jcrl9 or 20 when appendent thereto, in which the device has a plurality of radiation sensitive regions for controlling the state- of semiconductor elements of the device.

^ 22. An arrangement as claimed in claim 21, in which the device comprises a semiconductor memory having storage locations including the semiconductor elements.

23. An arrangement as claimed in claim 21, in which the device comprises an array of logic means linked

So by interconnection means incorporating said semiconductor elements, the interconnection pattern of the logic means being controlled by said state pattern.

24. An arrangement as claimed in any of claims 21 to 23, wherein the semiconductor elements comprise

3_^* transistors.

25. An arrangement as claimed in claim 24 where the transistors comprise insulated gate field effect - 33 - transistors.

26. An arrangement as claimed in any of claims 21 to 25 in which the device comprises a dynamic memory.

27. An arrangement as claimed in claim 26, in ≤^' which the device includes memory addressing and refreshing circuitry.

28. An arrangement as claimed in any of claims 21 to 23 which includes a further mask disposed between the first mentioned mask and the device and having a

«= plurality of radiation transmissive regions corresponding respectively to the radiation sensitive regions of the device.

29. An arrangement comprising an integrated circuit including a semiconductor memory having a is- plurality of storage cells, each cell comprising a transistor responsive to incident radiation to control the information stored at that cell, the memory having an opaque layer with radiation transmissive portions corresponding respectively to. selected ones of said cells

Sχ> and dimensioned so that on irradiating the opaque layer, radiation reaches a major portion of the transistors of those selected cells via their associated radiation transmissive portions.

30. In combination, an optical computer for x≤ providing an output in the form of a two dimensional image representing a state pattern;^* and an integrated circuit semiconductor device having a two dimensional array of radiation sensitive regions for controlling the state of semiconductor elements of the device, the device a being arranged to receive the output of the optical computer whereby the state pattern is loaded into the device.

31. A computer system comprising; an integrated circuit including a memory ^"U> having storage locations whose statescan be controlled in response to incident radiation; an image forming device comprising a source of radiation and a mask having a two dimensional array of regions corresponding respectively to said storage locations, each of which regions is alterable between a more transmissive and a less transmissive state thereby ^■*> to form a pattern representing a set of digital information to be loaded into the memory; and means for actuating the source of radiation to irradiate the memory via the mask to cause the information represented by the pattern to be loaded into

^■.o the memory; and means for controlling the image forming device to alter the pattern so that on subsequent irradiation a further set of digital information is loaded into the memory.