EP0179802A1 - Integrated circuits with contact pads in a standard array - Google Patents

Integrated circuits with contact pads in a standard array

Info

Publication number
EP0179802A1
EP0179802A1 EP85901784A EP85901784A EP0179802A1 EP 0179802 A1 EP0179802 A1 EP 0179802A1 EP 85901784 A EP85901784 A EP 85901784A EP 85901784 A EP85901784 A EP 85901784A EP 0179802 A1 EP0179802 A1 EP 0179802A1
Authority
EP
European Patent Office
Prior art keywords
array
input
layer
output contacts
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85901784A
Other languages
German (de)
French (fr)
Other versions
EP0179802A4 (en
Inventor
Daniel J. Quinn
Wayne A. Mulholland
Robert H. Bond
Michael A. Olla
Jerry S. Cupples
Ilya L. Tsitovsky
Barbara R. Mozdzen
Charles F. Held
Linda S. Wilson
Yen T. Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Components-Mostek Corp
Original Assignee
Thomson Components-Mostek Corp
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Components-Mostek Corp, Mostek Corp filed Critical Thomson Components-Mostek Corp
Publication of EP0179802A1 publication Critical patent/EP0179802A1/en
Publication of EP0179802A4 publication Critical patent/EP0179802A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01009—Fluorine [F]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the field of the invention is that of attaching leads to integrated circuit chips.
  • the assembly operation for integrated circuits consists of taking a silicon wafer containing several dozen or more integrated circuit chips; testing, sometimes referred to as “probing", the chips, to determine which are working and which are not; cutting the wafer apart to produce individual chips; attaching the chip to a leadframe; bonding wires to the leads one at a time; and encapsulating the combination in plastic to provide protection for the device and cutting and forming the external leads of the leadframe to their final shape.
  • the standard method of attaching wires to the chip is by wire bonding, in which a gold or aluminum alloy wire is pressed very hard (in the presence of elevated temperatures and/or ultrasonic energy) against a pad on the chip until a bond is formed.
  • the leads must be plated with gold, silver or other precious metal so that the bonding wire can form a reliable connection to the lead.
  • One prior art method that provides for simultaneous lead soldering is the "flip-chip” method developed by IBM, in which a lump of solder is placed on the chip and the chip is soldered to a ceramic substrate that is attached to the leads. This IBM method does not have a layer of leads on the top of the chip.
  • the invention relates to an integrated circuit chip adapted for an automated method of assembling and encapsulating integrated circuit chips in which the chips have standard connections that are in the same position for a number of different models of chips; the leads are all attached at the same time (by a fusible alloy reflow bonding method); the leadframe is stamped from an inexpensive metal, such as copper, and the integrated circuit die is not attached to a support in an intermediate step.
  • Another feature of the invention is the routing of input and output leads carrying relatively high current over interior portions of an integrated circuit.
  • Another feature of the invention is the provision of a standard pad array used for different chips having the same number of pins, so that only one type of leadframe need be kept in inventory for each pin-family.
  • Yet another feature of the invention is the provision of a leadframe adapted for reliable formation of bonds simultaneously in an automatic process.
  • Yet another feature of the invention is the elimination of the need to control thermal expansion between the chip support and the chip. Yet another feature of the invention is the provision of corrosion protection of the semiconductor metallization by a thick dielectric. Yet another feature of the invention is the use of a single array of probe electrodes for testing a pin-count family of chips.
  • Figure 1 illustrates the process flow in a system using the subject invention.
  • FIG 2 illustrates the steps in Figure 1 in more detail.
  • Figures 3A and 3B illustrate different forms of a chip used in the subject invention.
  • Figure 4A and 4B illustrate alternative arrays of contacts.
  • Figure 5 illustrates a portion of a leadframe.
  • Figure 6 shows a cross section of an integrated circuit chip suitable for use wi th the invention .
  • Figure 7 illustrates a carrier used to hold a leadframe and die during the bonding step.
  • a process that may be part of the "front-end” or the "back-end” accepts as input a wafer that has been completed with all the conventional steps (including passivation - etc.) and applies a further layer of dielectric having a thickness sufficient to protect the chip circuits and to insulate them electrically from signals being carried on the top surface of the dielectric.
  • a pattern of metal leads is formed that extends from the contact pads on the previous chip to a standard array of contact pads on the top of the dielectric. The standard array is the same for all chips having the same number of pins, regardless of the size of the chip die.
  • the wafer is then probe tested, in major step II with the results of the probe test being stored electrically, such as in a computer.
  • the conventional ink-dot marking system for bad chips is not used.
  • the wafer is then adhesively mounted on an adhesive film in a frame holder that is shaped to allow for automatic insertion and orientation in various fixtures further along in the process and cut apart in an automatic sawing process (Step III) that cuts through the entire thickness of the wafer.
  • the good dice are then removed from the wafer in an automatic sequence (Step IV) that presses from above against the tape to selectively pick a die down into a dedicated carrier where it rests circuit s ide down. This is not a problem since the active circuitry is protected by the standard pad dielectric and standard pads.
  • the wafer and punch-out device are moved under computer control to put the dice into the correct positions in the carrier.
  • the dice are transferred to a mating carrier simultaneously in an inversion operation that rotates the two-carrier "sandwich" by 180 degrees, so that the dice resting in the second carrier have contacts on the top side.
  • a set of dice are transferred to a bonding fixture that holds a convenient number, illustratively 14 dice.
  • Step V a leadframe matching the spacing of the dice in the fixture is pos itioned above the dice in the soldering fixture and an upper bonding fixture is added to maintain lead to pad contact during the bonding process.
  • the bonding fixture is heated to reflow the solder and form the interconnection (Step V).
  • the leadframe with dice attached is placed in a transfer or injection molding machine that encapsulates the die together with the interconnections to the leadframe (Step VI).
  • the molded strip of devices is then trimmed and formed conventionally (Step VII).
  • Figure 2 sets out the steps in Figure 1 in more detail and also illustrates the material and data flow.
  • a convention used in this figure is that a broken line indicates a material transport step of the sort of loading the material into a container and moving the container to another location and a double arrow indicates data flow into or out of a computer or other storage device.
  • the three material inputs to the process are the wafers, leadframes and plastic for encapsulation.
  • Two recirculation loops involve, respectively, a frame used to support the wafers during the sawing and die selection steps and a positioning fixture used to maintain a set of dice in alignment with a leadframe segment during the bonding operation.
  • FIG. 3A an integrated circuit according to the invention is illustrated in Figure 3A, in which integrated circuit 300 is any conventional integrated circuit with substrate, transistors and other active components, interconnections, passivation layer and the like, all indicated generally by the numeral 310.
  • a protective isolating layer 320 serves to isolate the circuit below from electrical signals carried by the input and output leads as well as to provide physical and chemical protection for the circuit below.
  • protective layer 320 is chosen to provide a moisture-resistant seal as well as to provide electrical insulation.
  • the array of contact pads is located in the center of the die and has the same configuration for all dice that have the same pins count.
  • Leads 326 extend from locations 330 at the edge of the die along paths that lead to array 340.
  • Illustrative dielectric layer 320 is a polyimide, such as Dupont 2525, applied with a thickness of 6 microns and cured at a temperature of greater than 260 degrees centigrade. There may be a nitride or other layer below the polyimide to improve adhesion to the reflow glass or other top layer.
  • the electrical contact pads that have been previously formed in the integrated circuit chip by conventional processing techniques are exposed by applying a photoresist, either liquid or in the form of a tape, on top of the dielectric and etching down through it a passageway to the metal contact pad in the circuit in a conventional manner.
  • a "via" will be formed by filling the contact holes with a metal or other conductor until the surface of the dielectric is reached.
  • the photoresist is stripped off and a layer of metal is applied by any technique , such as sputtering , over the surface of the polyimide. In one example, the polyimide was back sputtered to prepare the surface, after which 600
  • a second layer of photoresist is applied and patterned to define a set of metal leads in the metal layer.
  • the leads reach from the vias penetrating the dielectric to an area in the center of the chip which has a standard pad array of pad contacts that is the same for all the chips that have the same number of leads. For example, a 16 pin chip will have the same standard pad array, of size about .016" by .016" in a standard configuration having dimensions of .126" by .126", whether it is a memory or any other logic device.
  • the standard pad array will be sized so that it fits on the smallest chip that is to be used with that leadframe.
  • Optional versions of the invention employ a pad array that is arranged for some particular purpose.
  • the exposed areas of the metal are plated with a solder composed of a standard mixture of lead and tin in a conventional electrolytic plating process that employs a mixture of 95% tin and 5% lead.
  • the photoresist is stripped and the plated areas of the metal layer are used as an etching mask in the next step in which the remaining unwanted area of the metal layer is etched away in a bath of hydrogen peroxide plus ammonium hydroxide followed by hydrogen peroxide, which does not attack the solder.
  • chip 300 of the form illustrated in Figure 3A in which die 310 has on it a thick layer of polyimide 320 and a network of metal lines 326 leading from the contact areas 330 on the outside of the chip to the standard pad array 340.
  • the metal lines 326 have lower inductance greater thermal conductivity and greater strength compared to the wires that were previously used.
  • the first contacts and the vias through the polyimide layer are all formed on the perimeter of the chip.
  • the term "perimeter" is used to refer to the area near the edge of the chip that is used in the prior art for the contact pads.
  • This figure illustrates a chip in which the layout design was made for the old wire-bonding method in which the contact areas had to be on the perimeter of the chip.
  • FIG. 3B It is also possible to use the invention and put the contact areas through the dielectric at any convenient location, as shown in Figure 3B.
  • the vias for these leads are shown as originating at different locations on the chip surface, not exclusively at the edge as was the case in the prior art.
  • Lead 348 is shown as connecting a via that is located within the standard pad array.
  • Lead 343 is connected to a via-section 344 through a bridge, not shown in the drawing, that is placed on top of the passivation layer of the underlying chip below the polyimide. This illustrates an additional degree of freedom in routing leads and placing components that is provided by the invention.
  • a via 305 is shown in Figure 3A in a cut-away portion of the figure as extending from a lower contact area 304 to an upper contact 306 at an end of one of leads 326.
  • the lower contact pads in current practice are typically 4 mils by 4 mils.
  • the alignment tolerance for the formation and location of the vias and the placement of leads 326 are typically ⁇ 2 mils to 3 mils, which is much greater than a typical tole rance of ⁇ 1/2 mil to 1 mil for connecting leads in the precision processes that are used with conventional wirebonding.
  • the steps of forming vias and putting down leads may be performed in the front-end using the standard machines for photolithography, if that is convenient.
  • a contact pad, 6-05 is shown with a series of apertures defined above it.
  • Pad 6-05 which is typically aluminum and is connected by metallization strips, not shown, to the rest of the circuit, is surrounded by oxide 6-10, which has a conventional composition of SiO 2 plus phosphorous and other additives and a thickness of 1 micron.
  • Oxide 6-10 has a top surface 6-15 on which polyimide layer 6-50 was, at first, applied directly. Early tests showed significant difficulty, in that polyimide layer 6-50 (layer 320 in Figure 3) often disbonded, causing the leadframe to pull the polyimide away from the underlying layer.
  • Oxide 6-10 functions as the top dielectric layer in the circuit. It not only coats the substrate and contacts, as shown in Figure 16, but also the circuit elements and metallization.
  • Nitride layer 6-20 is deposited by plasma-assisted CVD at a temperature of 250 C, in a conventional manner, to a thickness of .3 micron after street 6-200 has been etched through oxide 6-10 to the substrate.
  • a layer of 2525 polyimide from Dupont is applied and spun to produce a relatively flat top surface. Apertures 6-45 above contact 6-05 and 6-55 above street 6-200 are opened through the uncured polyimide by wet etching with a conventional basic solution such as Shipley 312 developer.
  • Typical dimensions for the top of aperture 6-55 and 6-45 are 100 and 87 microns, respectively.
  • aperture 6-40 is opened through nitride layer 6-20 by plasma etching in CF4.
  • a typical dimension of aperture 6-40 is 75 microns, so that aperture 6-40 is surrounded by nitride 6-20 and does not expose any of oxide 6-10.
  • nitride 6-20 adheres well to oxide at surface 6-15.
  • the function of nitride 6-20 is thus to improve the adhesion of the polymide by means of a structure that totally encloses the oxide 6-10, not only at the vias but also at the saw cuts on the streets.
  • the next major step II is a test with the individual circuit dice still remaining in the wafer.
  • a conventional wafer electrical test step could be performed in which small probes are attached to the contacts that will be used for the input/output and the individual chips are tested.
  • An advantage of this invention is that the metal leads on top of the polyimide cover a much larger area than the old-style contact pads do, so that it is easier to make electrical contact at reduced pressure of the electrical contact probe or electrode with these large metal pads than it is with the small contact pads used in conventional techniques. It is also possible to make electrical contact to the leads before you reach the contact area, thus providing additional flexibility in the probe step.
  • An important economic benefit from the invention is that only a single set of probe tips will be needed to match the standard pad array for the whole family of circuits that have the same number of pins. In the prior art, a different set of probe tips was typically needed for each chip design.
  • the chip has optional electric contact pads outside the standard pad array, as shown by contact 350 in Figure 3B (which is a via formed to provide access to a point in a circuit that is to be tested, yet does not connect to one of the regular contacts), then a different set of probe pins will be needed in that case, of course.
  • defective chips are marked by a small dot of ink so that, in manual assembly, they can be identified and discarded.
  • the chips are identified electrically i.e. the wafer is oriented in a particular way and the chips are identified by their locations in an X-Y matrix.
  • the test data for individual chips are stored in the central computer memory or in a floppy disk or other storage medium and defective chips are identified in the computer. This step is referred to in Figure 2 as wafer mapping.
  • the chip has the feature of redundant or optional circuits that are connected or disconnected by blowing fuses by a laser (as is done in large scale memory arrays), then this step will have been done before the polyimide layer is put down, as is currently being done. It is possible, however, to provide for the enabling or disabling of optional subcircuits or the enabling of redundant circuits to be done electrically by means of access through additional contacts (similar to contact 350) that are placed through the polyimide layer outside of the metal strips, or by putting down the polyimide with a large opening over the redundant circuits that will be closed later. In that case, the central computer would identify optional circuits that are to be enabled or disabled and blow fuses appropriately through the test probes. The point in the sequence at which fuse-blowing is to be done is optional, of course.
  • the wafers have not been given an identifying label before, it is now necessary to put a label on them in order to maintain the connection between the test data stored in the computer and the wafer the data came from. There are many ways of doing this correlation, of course, and no particular method is required.
  • One preferred method is to put the identification on an identifying label, such as an optical bar code, that identifies the wafer.
  • Another method is to form a programmable memory in the wafer in which the identities of defective chips may be stored. In that case, the wafer carries with it the necessary information so that there is no problem of getting the wafer separted from the test results.
  • Step V in Figure 1 and Leadframe Fixture Assemble, Bond, Disassemble in Figure 2 is shown in an exploded view in Figure 7, in which holder 7-110, represented schematically, holds 14 chips with the correct spacing, only two of the receptacles 7-225 being shown. Above receptacle 7-225, there is positioned chip 7-230 and, above the chip, a set of finger contacts 5-122 in leadframe 5-100, part of leadframe strip 5-125. The details of the leadframe will be described below. Cover 7-120 Dresses down on edge 5-110 of leadframe strip 5-125, which edges rest on shelves 7-112 to position the outer parts of the strip so that the contact tips will be deflected slightly.
  • This deflection is done to compensate for inevitable fluctuations in the position of the tips during the manufacturing process, so that reliable contact is ensured during the bonding operation.
  • the deflection is effected by making the depth of receptacle 7-225 such that the top of chip 7-230 projects above the plane of shelves 7-112 by a set amount.
  • the amount of deflection, (.005 inch to .007 inch) is illustratively several standard deviations of the nominal fluctuation of the tip position to ensure reliable joint formation.
  • the edges 5-110 of leadframe strip 5-125 will be forced on to shelves 7-112 by cover 7-120 and tips 5-122 will thus be pressed against the pads by the spring constant of the leads.
  • a typical leadframe used in the invention is illustrated in Figure 5, in which half of an individual frame is shown.
  • the individual leadframes are stamped out of a ribbon of metal that may be an inexpensive copper alloy, in contrast to the expensive alloy having the correct thermal properties that is used in the standard prior art process.
  • the leadframe will be referred to as being "metallurgically continuous" in order to distinguish it from the prior art, in which a relatively thick frame is connected to a chip by a thin wire, so that the prior art electrical connection changes size and shape as well as composition.
  • solder does not affect whether a leadframe is metallurgically continuous. Strips 5-110 on either side of the ribbon serve to carry the actual leads 5-120 along.
  • Leads 5-120 have an exterior end 5-123, shaped for insertion in a socket or for surface-mounting, and an interior portion 5-121 for attachment to a die. The two portions are joined by segments 5-124 that will be severed after the bonding step. Holes 5-112 are provided to give a reference in positioning the leadframe. At the end of each lead 5-120, there is a region, 5-122, in which the lead is bent in a quarter circle (or bent twice to form a parallel contact section) to form a standard dimension flat contact area. Each of the different leads 5-120, with its different length, has been shaped to provide substantially the same spring constant so that the contact areas 5-122 will be uniformly pressed against the mating pads on the die to give correct alignment for the soldering operation. The leads 5-120 have been tinned with solder in a previous step in the fabrication of the leadframe ribbon. Both the contact pads 342 of the die and the tips
  • the bonding is done by a vapor phase reflow soldering technique or other means of heating the materials to reflow the fusible alloys.
  • vapor phase reflow a liquid such as Flourinert FC-71 is maintained at its boiling point, the liquid having been selected so that its boiling point is above the soldering temperature.
  • the soldering assembly of holders 7-110 and 7-120, with chips plus leadframe maintained in alignment, is inserted into a container or oven that is filled with the vapor at the boiling-point temperature and held there until the solder has melted and flowed to form a bond.
  • a typical length of time for the heating cycle is 5 to
  • This boiling point temperature is typically above 225 degrees C but below 300 degrees
  • the bonding fixture should have low mass and many apertures to permit the vapor to flow freely about the solder joints.
  • Holders 7-110 and 7-120 have been shown schematically in order to reduce the complexity of the drawing. It is not necessary that all the lead tips 5-121 be used in a system. If there are unnecessary leads and it is desi red to use a standard leadframe, the extra lead tips 5-122 may be connected to dummy contacts in standard array 340 or simply rest on polyimide 320.
  • An important economic benefit of this invention is that all the leads are soldered at the same time. This is in contrast to the wire-bonding technique, in which the leads must be bonded one by one. The soldering step takes no longer for a 28 pin chip than it does for a 16 pin chip.
  • Step VII in Figure 1 leadframe 5-100, with 14 chips attached, is placed into a transfer or injection molding machine to mold plastic about it, thus encapsulating and protecting the chip.
  • the molding process will be done us i ng conventional techniques and equipment. It is an advantageous feature of this invention that the wide contact area between the leadframe and the contact pads is extremely rugged compared to the wire bonding technique that is in standard use so that a far smaller fraction of chips will be damaged during handling and the chips can be moved about at a greater rate and with less delicacy required. It is a further advantage that the leads conduct heat away from the chip during operation. After the encapsulated dice, (still in the leadframe) are removed from the molding machine, the optional labelling step of Figure 2 is performed.
  • the dice identity first appeared during probe test, when data were measured that applied to an individual die. That identity was preserved by the labels on the wafer, tape frame and leadframe, the computer being updated as required to log the die identity on the leadframe.
  • Each chip may be marked by a laser branding process or any other convenient technique with an identifying label, test results, etc.
  • step VIII of Figure 1 the chip plus leadframe combination is separated from the ribbon and the spacing segments 5-124 that served to maintain the leads in correct alignment are severed. If the ribbon is formed from a sheet of copper or copper alloy, it is necessary to sever the connections 5-12 4 or else all the leads will be shorted together. If another version of the ribbon is used, in which a plastic backing is used for the portion 5-110 and to support leads 5-120, on top of which a plated copper lead has been formed, then it will be easy to maintain the sections 5-124 in plastic and it is not necessary to separate the leads.
  • FIGs 4A and 4B there is shown a variation of a die using the standard pad layout.
  • the standard pad array of Figures 3A and 3B used a square outline that was sized to fit on a very small chip, so that a single leadframe could be used for the complete size range. There may be other technical or economic considerations, however, that justify a different pad array (which may still be common to a number of integrated circuits).
  • Figure 4A shows a die having the same substrate 310 and polyimide 320 as before, but in which the pad array comprises two rows 350 illustratively of eight pads each, set toward the outside of the chip.
  • bus 353 which distributes the power supply voltage to various points in the circuit, one of which is a via indicated by the numeral 352 and positioned at one of the array positions to make contact with a lead.
  • bus 353 offers considerably less resistance and inductance.
  • bus 354 makes contact with pad 351 and distributes the ground terminal about the die.
  • a further advantage of the sturdy polyimide layer 320 is that discrete electrical devices, active or passive, may be placed on top of layer 320 and connected to the circuit, either by vias or to the standard pads .
  • device 368 is shown as being connected to vias 370 and 369.
  • the device may be a thick-film resistor having a large magnitude (that is difficult to achieve with conventional integrated circuit techniques). It also may be a separately formed device, optionally with conventional surface-mounted-device packaging. Examples are resistors, inductors and capacitors.
  • One useful example of a capacitor is shown as unit 355, a charge reserve capacitor connected between the power supply and ground using a conductive adhesive at point 367 and to strap 366.
  • a device such as unit 355 may be connected to any point in the circuit, of course.
  • One variation that is of great interest is the use of a separate device 355 that is an optical or other element that is difficult to fabricate on the same substrate.
  • device 355 could be a solid-state laser using a gallium arsenide subs t ra te and die 310 could be a conventional silicon integrated circuit. In that case, a fiber-optic pigtail would be included for communication to other optical devices.
  • R-C timing network either fixed or having an adjustable element for which an access hole is formed in the encapsulating plastic; or a power transistor using the area of device 355 to spread the heat load.
  • Heat sinks may also be attached directly to layer 320 or to vias that provide a low impedance thermal conduction path from high-power sections of substrate 310.
  • These other devices may be attached in any convenient manner. They may be adhesively attached before or after the soldering of the leadframe (or they may be soldered and the leadframe adhesively attached). Alternatively, soldering or gluing of leadframe and discrete devices may be done simultaneously, with the leadframe maintained in position prior to bonding by an adhesive.
  • Figure 4B illustrates another variation of the invention that offers considerable reduction in inventory.
  • a two-chip assembly comprising a first chip 300' having substrate 310, polyimide 320 and surface pads as before, and asecond chip 380 comprising substrate 310', polyimide 320' and array of contacts 382' that mate with an array of contacts 382 on layer 320.
  • An alternate U-shaped contact array 350' is shown, which has the advantage of freeing up half of layer 320 for chip 380. In order to bring all the leads over to one half of chip 300', it may be necessary to permit some variation in the spring constant of the leads.
  • Chip 380 may connect directly to the leads for input/output, of course. In the case illustrated, chip 380 is a ROM that needs only power supply and ground and communicates only with the larger chip through vias in array 382 or through surface leads, such as lead 373.
  • a multi-purpose chip such as a single-chip microcomputer that is customized by adding a ROM. If the ROM is a mask option, then there must be a reserve supply of customized microcomputers to allow for fluctuations in the yield, or rush orders and the manufacturer must maintain an inventory of chips that are good only for one customer. With the embodiment of Figure 4B, however, the inventory for each customer need only be his ROMs, which are much cheaper than microcomputers. The manufacturer will maintain a reserve of microcomputer chips sufficient to meet the needs of all his customers, of course. It is evident that the total value of inventory will be less with a central reserve, simply because of the laws of statistics.
  • a variation of the two-chip system is that in which the main chip 302 is a generalized system, such as an input controller and the second chip 380 is one of a number of alternatives, each customized for a particular application .
  • the main chip might be a 5-volt logic chip and chip 380 might be designed to withstand the high voltages of the telephone network in a telephone interface such as a modem or coder.
  • One convenient method of attaching chip 380 is to form pads 382 ' with a suff icient amount of high temperature solder to make reliable contact and to reflow that bond before bonding the leads at a lower temperature. Another method is to adhesively attach chip 380 in alignment and to solder both sets of contacts simultaneously.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

Une puce à circuits intégrés (310) comprend une couche supérieure de diélectrique (320) dans laquelle pénètrent des conducteurs (305) reliant les contacts électriques (304) dans le circuit intégré proprement dit à un réseau de conducteurs électriques (326) disposés au sommet de la couche diélectrique (320); le réseau de conducteurs (326) est relié à son tour à un réseau de plots de contact (330) adaptés à la connexion simultanée par soudage à un cadre conducteur.An integrated circuit chip (310) comprises an upper dielectric layer (320) into which conductors (305) penetrate connecting the electrical contacts (304) in the integrated circuit proper to a network of electrical conductors (326) arranged at the top the dielectric layer (320); the network of conductors (326) is in turn connected to a network of contact pads (330) adapted for simultaneous connection by welding to a conductive frame.

Description

Integrated Circuits with Contact Pads in a Standard Array
Technical Field The field of the invention is that of attaching leads to integrated circuit chips.
Background Art
The assembly operation for integrated circuits, sometimes referred to as the "back-end", consists of taking a silicon wafer containing several dozen or more integrated circuit chips; testing, sometimes referred to as "probing", the chips, to determine which are working and which are not; cutting the wafer apart to produce individual chips; attaching the chip to a leadframe; bonding wires to the leads one at a time; and encapsulating the combination in plastic to provide protection for the device and cutting and forming the external leads of the leadframe to their final shape. The standard method of attaching wires to the chip is by wire bonding, in which a gold or aluminum alloy wire is pressed very hard (in the presence of elevated temperatures and/or ultrasonic energy) against a pad on the chip until a bond is formed. One wire is done at a time. This method uses a great deal of labor and expensive materials. Automated wire bonding machines are known, but they have an inherent limitation. Even with the most rapid machines that can be imagined, there are factors that provide a necessary limitation to approximately 2,000 units per hour for a 16 pin chip. With wire bonding techniques, it is also necessary to attach the chip to the package or leadframe in order to maintain it in position while the wire bonds are formed. Also, the leads in this process must be typically made of an expensive expansion-controlled alloy in order to have the correct thermal expansion matching between the chip and the leads when gold-silicon eutectic die bonding is used or expensive special alloys or adhesives must be used to correct the thermal mismatch. Also, the leads must be plated with gold, silver or other precious metal so that the bonding wire can form a reliable connection to the lead. One prior art method that provides for simultaneous lead soldering is the "flip-chip" method developed by IBM, in which a lump of solder is placed on the chip and the chip is soldered to a ceramic substrate that is attached to the leads. This IBM method does not have a layer of leads on the top of the chip.
Disclosure of Invention
The invention relates to an integrated circuit chip adapted for an automated method of assembling and encapsulating integrated circuit chips in which the chips have standard connections that are in the same position for a number of different models of chips; the leads are all attached at the same time (by a fusible alloy reflow bonding method); the leadframe is stamped from an inexpensive metal, such as copper, and the integrated circuit die is not attached to a support in an intermediate step. Another feature of the invention is the routing of input and output leads carrying relatively high current over interior portions of an integrated circuit. Another feature of the invention is the provision of a standard pad array used for different chips having the same number of pins, so that only one type of leadframe need be kept in inventory for each pin-family. Yet another feature of the invention is the provision of a leadframe adapted for reliable formation of bonds simultaneously in an automatic process.
Yet another feature of the invention is the elimination of the need to control thermal expansion between the chip support and the chip. Yet another feature of the invention is the provision of corrosion protection of the semiconductor metallization by a thick dielectric. Yet another feature of the invention is the use of a single array of probe electrodes for testing a pin-count family of chips.
Brief Description of Drawings
Figure 1 illustrates the process flow in a system using the subject invention.
Figure 2 illustrates the steps in Figure 1 in more detail.
Figures 3A and 3B illustrate different forms of a chip used in the subject invention. Figure 4A and 4B illustrate alternative arrays of contacts. Figure 5 illustrates a portion of a leadframe. Figure 6 shows a cross section of an integrated circuit chip suitable for use wi th the invention .
Figure 7 illustrates a carrier used to hold a leadframe and die during the bonding step.
Best Mode for Carrying Out the Invention
The present invention was developed together with other components of a system for assembling and testing integrated circuits. Other features of the system are the subject of co-pending patent applications, filed the same day herewith and assigned to the assignee hereof. In order to convey the invention in context, discussion of the overall system is included in this specification. An overall flow chart of the steps used in the back-end assembly is illustrated in Figure 1, in which a number of steps are illustrated schematically and are performed by a variety of different machines in communication with and sometimes controlled by a computer for storing test and other data.
In the first major step, represented by the box labelled I, a process that may be part of the "front-end" or the "back-end", accepts as input a wafer that has been completed with all the conventional steps (including passivation - etc.) and applies a further layer of dielectric having a thickness sufficient to protect the chip circuits and to insulate them electrically from signals being carried on the top surface of the dielectric. A pattern of metal leads is formed that extends from the contact pads on the previous chip to a standard array of contact pads on the top of the dielectric. The standard array is the same for all chips having the same number of pins, regardless of the size of the chip die. The wafer is then probe tested, in major step II with the results of the probe test being stored electrically, such as in a computer. The conventional ink-dot marking system for bad chips is not used. The wafer is then adhesively mounted on an adhesive film in a frame holder that is shaped to allow for automatic insertion and orientation in various fixtures further along in the process and cut apart in an automatic sawing process (Step III) that cuts through the entire thickness of the wafer.
The good dice are then removed from the wafer in an automatic sequence (Step IV) that presses from above against the tape to selectively pick a die down into a dedicated carrier where it rests circuit s ide down. This is not a problem since the active circuitry is protected by the standard pad dielectric and standard pads. The wafer and punch-out device are moved under computer control to put the dice into the correct positions in the carrier. The dice are transferred to a mating carrier simultaneously in an inversion operation that rotates the two-carrier "sandwich" by 180 degrees, so that the dice resting in the second carrier have contacts on the top side. A set of dice are transferred to a bonding fixture that holds a convenient number, illustratively 14 dice. Once loading is complete, a leadframe matching the spacing of the dice in the fixture is pos itioned above the dice in the soldering fixture and an upper bonding fixture is added to maintain lead to pad contact during the bonding process. The bonding fixture is heated to reflow the solder and form the interconnection (Step V).
The leadframe with dice attached is placed in a transfer or injection molding machine that encapsulates the die together with the interconnections to the leadframe (Step VI).
The molded strip of devices is then trimmed and formed conventionally (Step VII).
There is a representation in Figure 1 of data communication between the machines that perform the steps listed above and the controlling computer. Most data communication steps are optional. The step may indeed be performed under operator control and data may be written down manually. The benefits of automatic recording of data and error-free recall of data from a previous step will be evident to those skilled in the art.
The different steps of the invention are set forth in more detail below and in copending patent applications filed on the same date herewith and assigned to the assignee hereof.
Figure 2 sets out the steps in Figure 1 in more detail and also illustrates the material and data flow. A convention used in this figure is that a broken line indicates a material transport step of the sort of loading the material into a container and moving the container to another location and a double arrow indicates data flow into or out of a computer or other storage device. The three material inputs to the process are the wafers, leadframes and plastic for encapsulation. Two recirculation loops involve, respectively, a frame used to support the wafers during the sawing and die selection steps and a positioning fixture used to maintain a set of dice in alignment with a leadframe segment during the bonding operation.
Standard Contact Pads
Returning to the first major step, an integrated circuit according to the invention is illustrated in Figure 3A, in which integrated circuit 300 is any conventional integrated circuit with substrate, transistors and other active components, interconnections, passivation layer and the like, all indicated generally by the numeral 310. A protective isolating layer 320 serves to isolate the circuit below from electrical signals carried by the input and output leads as well as to provide physical and chemical protection for the circuit below. For example, protective layer 320 is chosen to provide a moisture-resistant seal as well as to provide electrical insulation.
The array of contact pads, indicated generally by the numeral 340, is located in the center of the die and has the same configuration for all dice that have the same pins count. Leads 326 extend from locations 330 at the edge of the die along paths that lead to array 340.
Illustrative dielectric layer 320 is a polyimide, such as Dupont 2525, applied with a thickness of 6 microns and cured at a temperature of greater than 260 degrees centigrade. There may be a nitride or other layer below the polyimide to improve adhesion to the reflow glass or other top layer. The electrical contact pads that have been previously formed in the integrated circuit chip by conventional processing techniques are exposed by applying a photoresist, either liquid or in the form of a tape, on top of the dielectric and etching down through it a passageway to the metal contact pad in the circuit in a conventional manner. A "via" will be formed by filling the contact holes with a metal or other conductor until the surface of the dielectric is reached. The photoresist is stripped off and a layer of metal is applied by any technique , such as sputtering , over the surface of the polyimide. In one example, the polyimide was back sputtered to prepare the surface, after which 600
Angstroms of 10% titanium +90% tungsten followed by 1000 Angstroms of copper and the titanium tungsten mixture sputtered simultaneously, followed by typically 3 microns of copper were sputtered on. A second layer of photoresist is applied and patterned to define a set of metal leads in the metal layer. The leads reach from the vias penetrating the dielectric to an area in the center of the chip which has a standard pad array of pad contacts that is the same for all the chips that have the same number of leads. For example, a 16 pin chip will have the same standard pad array, of size about .016" by .016" in a standard configuration having dimensions of .126" by .126", whether it is a memory or any other logic device. The standard pad array will be sized so that it fits on the smallest chip that is to be used with that leadframe. Optional versions of the invention employ a pad array that is arranged for some particular purpose. The exposed areas of the metal are plated with a solder composed of a standard mixture of lead and tin in a conventional electrolytic plating process that employs a mixture of 95% tin and 5% lead. The photoresist is stripped and the plated areas of the metal layer are used as an etching mask in the next step in which the remaining unwanted area of the metal layer is etched away in a bath of hydrogen peroxide plus ammonium hydroxide followed by hydrogen peroxide, which does not attack the solder.
There now remains a chip 300 of the form illustrated in Figure 3A, in which die 310 has on it a thick layer of polyimide 320 and a network of metal lines 326 leading from the contact areas 330 on the outside of the chip to the standard pad array 340. The metal lines 326 have lower inductance greater thermal conductivity and greater strength compared to the wires that were previously used.
In the example shown in Figure 3A, the first contacts and the vias through the polyimide layer are all formed on the perimeter of the chip. The term "perimeter" is used to refer to the area near the edge of the chip that is used in the prior art for the contact pads. This figure illustrates a chip in which the layout design was made for the old wire-bonding method in which the contact areas had to be on the perimeter of the chip. An advantage of retaining the old design, besides saving the expense of a new layout, is that it is possible to use conventional wirebonding processes when added capacity is required. To do this however, requires that the additional dielectric and metallizations for the standard pad process is not used.
It is also possible to use the invention and put the contact areas through the dielectric at any convenient location, as shown in Figure 3B. The vias for these leads are shown as originating at different locations on the chip surface, not exclusively at the edge as was the case in the prior art. Lead 348 is shown as connecting a via that is located within the standard pad array. Lead 343 is connected to a via-section 344 through a bridge, not shown in the drawing, that is placed on top of the passivation layer of the underlying chip below the polyimide. This illustrates an additional degree of freedom in routing leads and placing components that is provided by the invention.
A via 305 is shown in Figure 3A in a cut-away portion of the figure as extending from a lower contact area 304 to an upper contact 306 at an end of one of leads 326. The lower contact pads in current practice are typically 4 mils by 4 mils. With such a large area to make contact, the alignment tolerance for the formation and location of the vias and the placement of leads 326 are typically ± 2 mils to 3 mils, which is much greater than a typical tole rance of ± 1/2 mil to 1 mil for connecting leads in the precision processes that are used with conventional wirebonding. The steps of forming vias and putting down leads may be performed in the front-end using the standard machines for photolithography, if that is convenient. Since the requirements for putting down these metal leads are much less stringent in position alignment than the usual front-end work, it may be preferable to use thick-film technology, such as screen printing, to pattern the dielectric and top leads. Typically, the thick-film technique will be 1/4 to 1/2 the cost of the precision techniques. lt has been found that the polyimide layer 320 of Figure 3 does not adhere reliably if it is attached directly to the layer of oxide immediately below it. A cross section of a portion of a die is shown in Figure 6, in which substrate 6-100 is the silicon substrate and aperture 6-55 is the "street" that separates adjacent dice. The width of a street is typically 100 microns, to allow room for the saw kerf in the separation step that is performed with a diamond saw having a width of .001 inch.
A contact pad, 6-05, is shown with a series of apertures defined above it. Pad 6-05, which is typically aluminum and is connected by metallization strips, not shown, to the rest of the circuit, is surrounded by oxide 6-10, which has a conventional composition of SiO2 plus phosphorous and other additives and a thickness of 1 micron. Oxide 6-10 has a top surface 6-15 on which polyimide layer 6-50 was, at first, applied directly. Early tests showed significant difficulty, in that polyimide layer 6-50 (layer 320 in Figure 3) often disbonded, causing the leadframe to pull the polyimide away from the underlying layer.
Oxide 6-10 functions as the top dielectric layer in the circuit. It not only coats the substrate and contacts, as shown in Figure 16, but also the circuit elements and metallization.
Passivation of the active elements of the circuit is effected in the usual manner of silicon MOSFETS by the thin oxide over source, drain and active area so that oxide 6-10 functions purely as a dielectric, not as a passivating layer. Nitride layer 6-20 is deposited by plasma-assisted CVD at a temperature of 250 C, in a conventional manner, to a thickness of .3 micron after street 6-200 has been etched through oxide 6-10 to the substrate. A layer of 2525 polyimide from Dupont is applied and spun to produce a relatively flat top surface. Apertures 6-45 above contact 6-05 and 6-55 above street 6-200 are opened through the uncured polyimide by wet etching with a conventional basic solution such as Shipley 312 developer. Typical dimensions for the top of aperture 6-55 and 6-45 are 100 and 87 microns, respectively. After aperture 6-45 has been opened, aperture 6-40 is opened through nitride layer 6-20 by plasma etching in CF4. A typical dimension of aperture 6-40 is 75 microns, so that aperture 6-40 is surrounded by nitride 6-20 and does not expose any of oxide 6-10.
It has been found that the adhesion of polyimide to top surface 6-25 of nitride 6-20 is greatly improved over the adhesion of polymide to oxide 6-10 at surface 6-15. Nitride 6-20 adheres well to oxide at surface 6-15. The function of nitride 6-20 is thus to improve the adhesion of the polymide by means of a structure that totally encloses the oxide 6-10, not only at the vias but also at the saw cuts on the streets.
Probe Test
The next major step II is a test with the individual circuit dice still remaining in the wafer. A conventional wafer electrical test step could be performed in which small probes are attached to the contacts that will be used for the input/output and the individual chips are tested. An advantage of this invention is that the metal leads on top of the polyimide cover a much larger area than the old-style contact pads do, so that it is easier to make electrical contact at reduced pressure of the electrical contact probe or electrode with these large metal pads than it is with the small contact pads used in conventional techniques. It is also possible to make electrical contact to the leads before you reach the contact area, thus providing additional flexibility in the probe step. An important economic benefit from the invention is that only a single set of probe tips will be needed to match the standard pad array for the whole family of circuits that have the same number of pins. In the prior art, a different set of probe tips was typically needed for each chip design.
If the chip has optional electric contact pads outside the standard pad array, as shown by contact 350 in Figure 3B (which is a via formed to provide access to a point in a circuit that is to be tested, yet does not connect to one of the regular contacts), then a different set of probe pins will be needed in that case, of course. In conventional wafer tests, defective chips are marked by a small dot of ink so that, in manual assembly, they can be identified and discarded. In this process, the chips are identified electrically i.e. the wafer is oriented in a particular way and the chips are identified by their locations in an X-Y matrix. The test data for individual chips are stored in the central computer memory or in a floppy disk or other storage medium and defective chips are identified in the computer. This step is referred to in Figure 2 as wafer mapping.
If the chip has the feature of redundant or optional circuits that are connected or disconnected by blowing fuses by a laser (as is done in large scale memory arrays), then this step will have been done before the polyimide layer is put down, as is currently being done. It is possible, however, to provide for the enabling or disabling of optional subcircuits or the enabling of redundant circuits to be done electrically by means of access through additional contacts (similar to contact 350) that are placed through the polyimide layer outside of the metal strips, or by putting down the polyimide with a large opening over the redundant circuits that will be closed later. In that case, the central computer would identify optional circuits that are to be enabled or disabled and blow fuses appropriately through the test probes. The point in the sequence at which fuse-blowing is to be done is optional, of course.
If the wafers have not been given an identifying label before, it is now necessary to put a label on them in order to maintain the connection between the test data stored in the computer and the wafer the data came from. There are many ways of doing this correlation, of course, and no particular method is required. One preferred method is to put the identification on an identifying label, such as an optical bar code, that identifies the wafer. Another method is to form a programmable memory in the wafer in which the identities of defective chips may be stored. In that case, the wafer carries with it the necessary information so that there is no problem of getting the wafer separted from the test results.
The steps of sawing apart the dice and then selectively removing good dice by automatic processes are described in more detail in copending patent applications. These steps may be performed manually, rather than automatically, if the increased production rate afforded by automatic die selection is not required for some particular application.
Bond
The assembly for the final bonding step (Step V in Figure 1 and Leadframe Fixture Assemble, Bond, Disassemble in Figure 2) is shown in an exploded view in Figure 7, in which holder 7-110, represented schematically, holds 14 chips with the correct spacing, only two of the receptacles 7-225 being shown. Above receptacle 7-225, there is positioned chip 7-230 and, above the chip, a set of finger contacts 5-122 in leadframe 5-100, part of leadframe strip 5-125. The details of the leadframe will be described below. Cover 7-120 Dresses down on edge 5-110 of leadframe strip 5-125, which edges rest on shelves 7-112 to position the outer parts of the strip so that the contact tips will be deflected slightly. This deflection is done to compensate for inevitable fluctuations in the position of the tips during the manufacturing process, so that reliable contact is ensured during the bonding operation. The deflection is effected by making the depth of receptacle 7-225 such that the top of chip 7-230 projects above the plane of shelves 7-112 by a set amount. The amount of deflection, (.005 inch to .007 inch) is illustratively several standard deviations of the nominal fluctuation of the tip position to ensure reliable joint formation. The edges 5-110 of leadframe strip 5-125 will be forced on to shelves 7-112 by cover 7-120 and tips 5-122 will thus be pressed against the pads by the spring constant of the leads.
A typical leadframe used in the invention, is illustrated in Figure 5, in which half of an individual frame is shown. The individual leadframes are stamped out of a ribbon of metal that may be an inexpensive copper alloy, in contrast to the expensive alloy having the correct thermal properties that is used in the standard prior art process. For purposes of this application, the leadframe will be referred to as being "metallurgically continuous" in order to distinguish it from the prior art, in which a relatively thick frame is connected to a chip by a thin wire, so that the prior art electrical connection changes size and shape as well as composition. The use of solder does not affect whether a leadframe is metallurgically continuous. Strips 5-110 on either side of the ribbon serve to carry the actual leads 5-120 along. Leads 5-120 have an exterior end 5-123, shaped for insertion in a socket or for surface-mounting, and an interior portion 5-121 for attachment to a die. The two portions are joined by segments 5-124 that will be severed after the bonding step. Holes 5-112 are provided to give a reference in positioning the leadframe. At the end of each lead 5-120, there is a region, 5-122, in which the lead is bent in a quarter circle (or bent twice to form a parallel contact section) to form a standard dimension flat contact area. Each of the different leads 5-120, with its different length, has been shaped to provide substantially the same spring constant so that the contact areas 5-122 will be uniformly pressed against the mating pads on the die to give correct alignment for the soldering operation. The leads 5-120 have been tinned with solder in a previous step in the fabrication of the leadframe ribbon. Both the contact pads 342 of the die and the tips
5-122 have been tinned and are ready to be heated.
The bonding is done by a vapor phase reflow soldering technique or other means of heating the materials to reflow the fusible alloys. These alternative techniques include infra-red heating, conveyor ovens, hot gas heating or laser heating. In vapor phase reflow, a liquid such as Flourinert FC-71 is maintained at its boiling point, the liquid having been selected so that its boiling point is above the soldering temperature. The soldering assembly of holders 7-110 and 7-120, with chips plus leadframe maintained in alignment, is inserted into a container or oven that is filled with the vapor at the boiling-point temperature and held there until the solder has melted and flowed to form a bond. A typical length of time for the heating cycle is 5 to
15 seconds. This boiling point temperature is typically above 225 degrees C but below 300 degrees
C. In contrast, the present wire bonding and die attach steps are performed at temperatures of up to
460 degrees C and performed individually. In order to reduce the length of the heating cycle, the bonding fixture should have low mass and many apertures to permit the vapor to flow freely about the solder joints. Holders 7-110 and 7-120 have been shown schematically in order to reduce the complexity of the drawing. It is not necessary that all the lead tips 5-121 be used in a system. If there are unnecessary leads and it is desi red to use a standard leadframe, the extra lead tips 5-122 may be connected to dummy contacts in standard array 340 or simply rest on polyimide 320.
An important economic benefit of this invention is that all the leads are soldered at the same time. This is in contrast to the wire-bonding technique, in which the leads must be bonded one by one. The soldering step takes no longer for a 28 pin chip than it does for a 16 pin chip.
Mold
In the next major step, (Step VII in Figure 1), leadframe 5-100, with 14 chips attached, is placed into a transfer or injection molding machine to mold plastic about it, thus encapsulating and protecting the chip. The molding process will be done us i ng conventional techniques and equipment. It is an advantageous feature of this invention that the wide contact area between the leadframe and the contact pads is extremely rugged compared to the wire bonding technique that is in standard use so that a far smaller fraction of chips will be damaged during handling and the chips can be moved about at a greater rate and with less delicacy required. It is a further advantage that the leads conduct heat away from the chip during operation. After the encapsulated dice, (still in the leadframe) are removed from the molding machine, the optional labelling step of Figure 2 is performed.
The dice identity first appeared during probe test, when data were measured that applied to an individual die. That identity was preserved by the labels on the wafer, tape frame and leadframe, the computer being updated as required to log the die identity on the leadframe. Each chip may be marked by a laser branding process or any other convenient technique with an identifying label, test results, etc.
The conventional "dejunk" step, in which excess plastic is removed from the leads is also performed at this time.
Trim/Form
Next, in step VIII of Figure 1, the chip plus leadframe combination is separated from the ribbon and the spacing segments 5-124 that served to maintain the leads in correct alignment are severed. If the ribbon is formed from a sheet of copper or copper alloy, it is necessary to sever the connections 5-12 4 or else all the leads will be shorted together. If another version of the ribbon is used, in which a plastic backing is used for the portion 5-110 and to support leads 5-120, on top of which a plated copper lead has been formed, then it will be easy to maintain the sections 5-124 in plastic and it is not necessary to separate the leads. Discrete Component Attachment
Referring now to Figures 4A and 4B, there is shown a variation of a die using the standard pad layout. The standard pad array of Figures 3A and 3B used a square outline that was sized to fit on a very small chip, so that a single leadframe could be used for the complete size range. There may be other technical or economic considerations, however, that justify a different pad array (which may still be common to a number of integrated circuits).
For example. Figure 4A shows a die having the same substrate 310 and polyimide 320 as before, but in which the pad array comprises two rows 350 illustratively of eight pads each, set toward the outside of the chip. With the center clear, there is room for bus 353, which distributes the power supply voltage to various points in the circuit, one of which is a via indicated by the numeral 352 and positioned at one of the array positions to make contact with a lead. Compared with the prior art technique of using thin wires, bus 353 offers considerably less resistance and inductance. Similarly, bus 354 makes contact with pad 351 and distributes the ground terminal about the die. A further advantage of the sturdy polyimide layer 320 is that discrete electrical devices, active or passive, may be placed on top of layer 320 and connected to the circuit, either by vias or to the standard pads . In Figure 4A, device 368 is shown as being connected to vias 370 and 369. The device may be a thick-film resistor having a large magnitude (that is difficult to achieve with conventional integrated circuit techniques). It also may be a separately formed device, optionally with conventional surface-mounted-device packaging. Examples are resistors, inductors and capacitors. One useful example of a capacitor is shown as unit 355, a charge reserve capacitor connected between the power supply and ground using a conductive adhesive at point 367 and to strap 366. Such capacitors are conventionally attached to integrated-circuit sockets to maintain a stable supply voltage when circuits switch. The economic advantages of including the capacitor with the chip are evident. A device such as unit 355 may be connected to any point in the circuit, of course. One variation that is of great interest is the use of a separate device 355 that is an optical or other element that is difficult to fabricate on the same substrate. For example, device 355 could be a solid-state laser using a gallium arsenide subs t ra te and die 310 could be a conventional silicon integrated circuit. In that case, a fiber-optic pigtail would be included for communication to other optical devices.
Other devices that may be readily implemented are an R-C timing network, either fixed or having an adjustable element for which an access hole is formed in the encapsulating plastic; or a power transistor using the area of device 355 to spread the heat load. Heat sinks may also be attached directly to layer 320 or to vias that provide a low impedance thermal conduction path from high-power sections of substrate 310. These other devices may be attached in any convenient manner. They may be adhesively attached before or after the soldering of the leadframe (or they may be soldered and the leadframe adhesively attached). Alternatively, soldering or gluing of leadframe and discrete devices may be done simultaneously, with the leadframe maintained in position prior to bonding by an adhesive.
Figure 4B illustrates another variation of the invention that offers considerable reduction in inventory. There is now a two-chip assembly comprising a first chip 300' having substrate 310, polyimide 320 and surface pads as before, and asecond chip 380 comprising substrate 310', polyimide 320' and array of contacts 382' that mate with an array of contacts 382 on layer 320.
An alternate U-shaped contact array 350' is shown, which has the advantage of freeing up half of layer 320 for chip 380. In order to bring all the leads over to one half of chip 300', it may be necessary to permit some variation in the spring constant of the leads.
Only some connections between contacts 350' and 382 are shown, for power supply and ground. Chip 380 may connect directly to the leads for input/output, of course. In the case illustrated, chip 380 is a ROM that needs only power supply and ground and communicates only with the larger chip through vias in array 382 or through surface leads, such as lead 373.
One particular application of great commercial interest is that of a multi-purpose chip, such as a single-chip microcomputer that is customized by adding a ROM. If the ROM is a mask option, then there must be a reserve supply of customized microcomputers to allow for fluctuations in the yield, or rush orders and the manufacturer must maintain an inventory of chips that are good only for one customer. With the embodiment of Figure 4B, however, the inventory for each customer need only be his ROMs, which are much cheaper than microcomputers. The manufacturer will maintain a reserve of microcomputer chips sufficient to meet the needs of all his customers, of course. It is evident that the total value of inventory will be less with a central reserve, simply because of the laws of statistics.
A variation of the two-chip system is that in which the main chip 302 is a generalized system, such as an input controller and the second chip 380 is one of a number of alternatives, each customized for a particular application . For example , the main chip might be a 5-volt logic chip and chip 380 might be designed to withstand the high voltages of the telephone network in a telephone interface such as a modem or coder.
Many other applications of the second chip, such as interfaces to different manufacturers' computers for plug-compatible systems; or the implementation of one of a number of standard logical functions, such as a parallel output or a serial output, will be evident to those skilled in the art.
One convenient method of attaching chip 380 is to form pads 382 ' with a suff icient amount of high temperature solder to make reliable contact and to reflow that bond before bonding the leads at a lower temperature. Another method is to adhesively attach chip 380 in alignment and to solder both sets of contacts simultaneously.
Those skilled in the art will readily be able to devise further alternate embodiments of the invention in the light of this disclosure. In particular, the invention is not confined to any particular configuration of contact pads; square or rectangular arrays may be used; as may U-shaped arrays; rows of lines; or irregular configurations.

Claims

Claims
1. An integrated circuit comprising: a semiconductor substrate having a substrate length and width and at least one electrical circuit formed from a plurality of electrical devices fabricated on said substrate in a plurality of layers; a network of electrical conduction paths connecting said electrical devices within said circuit and a first array of input/output contacts for passing electrical signals into and out of said circuit; characterized in that: a layer of dielectric extends over that portion of the top surface of said integrated circuit exclusive of said first array of input/output contacts, covering said at least one electrical circuit and said network of electrical conduction paths, said layer of dielectric having a perimeter region and an interior region within said perimeter region; a second array of input/output contacts having a surface layer adapted for electrically conductive attachment is disposed in a predetermined pattern on said layer of dielectric within said interior region; and a second network of electrical conduction paths is disposed on said dielectric layer connecting said first array of input/output contacts and said second array of input/output contacts.
2. An integrated circuit according to claim 1, further characterized in that said predetermined pattern of said second array of input/output contacts has a contact pad array length and width each of which is less than said substrate length and width and in that said contact pad array is adapted to match a standard lead frame contact array pattern, whereby a standard lead frame may be used with more than one integrated circuit.
3. An integrated circuit according to claim 2 , further characterized in that said contact pad array is rectangular in configuration.
4. An integrated circuit according to claim 2 , further characterized in that said contact pad array comprises at least two parallel rows of contacts.
5. An integrated circuit according to claim 2 , further characterized in that said contact pad array is U-shaped in configuration.
6. An integrated circuit according to claim 2 , further characterized in that said second array of input/output contacts are plated with solder, whereby said surface layer adapted for electrically conductive attachment is a layer of solder.
7. An integrated circuit according to claim 2, further characterized in that a plurality of electrical leads are conductively connected to at least some of said second array of input/output contacts said leads being formed from a metallurgically continuous conductive material.
8. A method of at tachi ng electrical leads to an integrated circuit having a plurality of electrical devices connected in an electrical circuit by a network of electrical conduction paths to a first array of input/output contacts comprising the steps of: applying a layer of dielectric over said electrical circuit; opening apertures in said layer of dielectric above said first array of input/output contacts; applying a network of electrically conductive paths between said first array of input/output contacts and a second array of input/output contacts disposed in a predetermined pattern on said layer of dielectric; placing an array of electrically conductive leads having attachments tips in proximity to said second array of input/output contacts; and simultaneously forming an electrically conductive bond between at least some of said second array of input/output contacts and at least some of said attachment tips.
9. A method according to claim 8, in which said step of opening apertures in said dielectric includes the steps of applying a sheet of photosensitive material above said layer of dielectric, patterning said photosensitive material with aperture regions and chemically removing that portion of said dielectric below said aperture regions to form said apertures.
10 . A method according to claim 8, in which said step of applying a network of electrically conductive paths includes the step of applying a thick-film pattern of conductive material to form said network of electrically conductive paths.
EP19850901784 1984-03-22 1985-03-19 Integrated circuits with contact pads in a standard array. Withdrawn EP0179802A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59218684A 1984-03-22 1984-03-22
US592186 1984-03-22

Publications (2)

Publication Number Publication Date
EP0179802A1 true EP0179802A1 (en) 1986-05-07
EP0179802A4 EP0179802A4 (en) 1987-06-01

Family

ID=24369668

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19850901784 Withdrawn EP0179802A4 (en) 1984-03-22 1985-03-19 Integrated circuits with contact pads in a standard array.

Country Status (4)

Country Link
EP (1) EP0179802A4 (en)
JP (2) JPS61501538A (en)
KR (1) KR960009090B1 (en)
WO (1) WO1985004518A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2604029B1 (en) * 1986-09-16 1994-08-05 Toshiba Kk INTEGRATED CIRCUIT CHIP HAVING IMPROVED OUTPUT TERMINALS
JPH07111971B2 (en) * 1989-10-11 1995-11-29 三菱電機株式会社 Method of manufacturing integrated circuit device
EP1600249A1 (en) 2004-05-27 2005-11-30 Koninklijke Philips Electronics N.V. Composition of a solder, and method of manufacturing a solder connection
US8169081B1 (en) 2007-12-27 2012-05-01 Volterra Semiconductor Corporation Conductive routings in integrated circuits using under bump metallization
CN106604547B (en) * 2016-11-22 2018-12-11 深圳市洁简达创新科技有限公司 A kind of pollution-free electronic circuit board manufacturing process

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2357071A1 (en) * 1976-06-30 1978-01-27 Ibm METHOD FOR FORMING CONNECTIONS THROUGH AN INSULATING LAYER IN THE MANUFACTURE OF INTEGRATED CIRCUITS

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386008A (en) * 1964-08-31 1968-05-28 Cts Corp Integrated circuit
US3518751A (en) * 1967-05-25 1970-07-07 Hughes Aircraft Co Electrical connection and/or mounting arrays for integrated circuit chips
US3808475A (en) * 1972-07-10 1974-04-30 Amdahl Corp Lsi chip construction and method
US4197555A (en) * 1975-12-29 1980-04-08 Fujitsu Limited Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2357071A1 (en) * 1976-06-30 1978-01-27 Ibm METHOD FOR FORMING CONNECTIONS THROUGH AN INSULATING LAYER IN THE MANUFACTURE OF INTEGRATED CIRCUITS

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 15, no. 10, March 1973, pages 3027-3028, New York, US; H.M. DALAL et al.: "Multilevel interconnection metallurgy system for semiconductor devices" *
See also references of WO8504518A1 *

Also Published As

Publication number Publication date
KR960009090B1 (en) 1996-07-10
JPH0554694B2 (en) 1993-08-13
JPH06318615A (en) 1994-11-15
EP0179802A4 (en) 1987-06-01
WO1985004518A1 (en) 1985-10-10
JPS61501538A (en) 1986-07-24
JPH0719792B2 (en) 1995-03-06
KR860700074A (en) 1986-01-31

Similar Documents

Publication Publication Date Title
US4685998A (en) Process of forming integrated circuits with contact pads in a standard array
US4722060A (en) Integrated-circuit leadframe adapted for a simultaneous bonding operation
US5844317A (en) Consolidated chip design for wire bond and flip-chip package technologies
US6204074B1 (en) Chip design process for wire bond and flip-chip package
KR940000741B1 (en) Automatic assembly of integrated circuit
EP0459493B1 (en) A semiconductor device comprising a TAB tape and its manufacturing method
US6355981B1 (en) Wafer fabrication of inside-wrapped contacts for electronic devices
JPH04250641A (en) Semiconductor package by metal and its manufacture
JP3007497B2 (en) Semiconductor integrated circuit device, its manufacturing method, and its mounting method
EP0460131A1 (en) Testable ribbon bonding method and wedge bonding tool for microcircuit device fabrication
GB2274351A (en) I.C.Chip carriers
JP4094075B2 (en) Module package without wire bond and manufacturing method
JPS60194565A (en) Semiconductor device
US11211373B1 (en) Double-sided chip stack assembly
KR960009090B1 (en) Integrated circuit with contact pads in a standard array
US5898128A (en) Electronic component
EP0177560A1 (en) Integrated circuit add-on components
US5045639A (en) Pin grid array package
EP0495629A1 (en) Vertical lead-on-chip package
EP0177563A4 (en) Robot gripper for integrated circuit leadframes.
EP0176557B1 (en) Impedance-matched leads
WO1985004519A1 (en) Nitride bonding layer
EP0170022B1 (en) Semiconductor power device package for surface mounting
JP3210503B2 (en) Multi-chip module and manufacturing method thereof
JPH0740580B2 (en) Substrate for selecting semiconductor element and method for selecting semiconductor element

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB NL

17P Request for examination filed

Effective date: 19860407

A4 Supplementary search report drawn up and despatched

Effective date: 19870601

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: THOMSON COMPONENTS-MOSTEK CORPORATION

17Q First examination report despatched

Effective date: 19890322

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19890802

RIN1 Information on inventor provided before grant (corrected)

Inventor name: HELD, CHARLES, F.

Inventor name: TSITOVSKY, ILYA, L.

Inventor name: NGUYEN, YEN, T.

Inventor name: QUINN, DANIEL, J.

Inventor name: OLLA, MICHAEL, A.

Inventor name: CUPPLES, JERRY, S.

Inventor name: WILSON, LINDA, S.

Inventor name: BOND, ROBERT, H.

Inventor name: MOZDZEN, BARBARA, R.

Inventor name: MULHOLLAND, WAYNE, A.