EP0177889A2 - CRT display control apparatus - Google Patents
CRT display control apparatus Download PDFInfo
- Publication number
- EP0177889A2 EP0177889A2 EP85112487A EP85112487A EP0177889A2 EP 0177889 A2 EP0177889 A2 EP 0177889A2 EP 85112487 A EP85112487 A EP 85112487A EP 85112487 A EP85112487 A EP 85112487A EP 0177889 A2 EP0177889 A2 EP 0177889A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- character
- graphic
- display
- clock signal
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/40—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/18—Timing circuits for raster scan displays
Definitions
- 10-bit display data consisting of 8-bit dot font data from the generator 11 and a 2-bit ground signal (GND) is loaded in the register 12 in response to the signal $LOAD.
- the register 12 generates the display data as bit serial data in response to the signal $CDOT from the generator 19.
- the bit display data is supplied as a video signal (VIDEO) to a CRT monitor (not shown) through the OR gate 17 and the driver 18. Therefore, as shown in Fig. 5, in the character display mode, the right and left dots corresponding to the ground signal are not displayed, and the dot font data is displayed in the 8-dot area.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Multimedia (AREA)
- Human Computer Interaction (AREA)
- General Engineering & Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Digital Computer Display Output (AREA)
Abstract
Description
- The present invention relates to an improved CRT display control apparatus arranged by adding a graphic display function to a display system based on character display.
- CRT display units have been used as computer output devices in a variety of applications, and various software tools are available. Strong demand for superposed display by using a character display function conventionally provided in the CRT display unit of this type has arisen. In order to satisfy such a demand, one graphic function method is the mosaic graphic function. However, this method does not provide satisfactory results. Therefore, a conventional character/graphic display control apparatus with a graphic display function is proposed.
- Character display is normally controlled by a CRT controller, and graphic display, by a graphic controller. A dot clock signal $DOT and a character clock signal $CHAR are used to control the display timing. A character display output signal from one ,shift register is superposed on a graphic display output signal from the other shift register to constitute a video signal. The video signal is displayed on a CRT monitor.
- In a conventional CRT display of this type, the operation timing of the CRT and graphic controllers must be adjusted. For example, a block corresponding to a one-character display area of character display comprises 10 dots along the horizontal direction in the graphic display mode. Ten-bit pixel data must therefore be simultaneously processed. As compared with 8-bit processing, hardware and software are complicated, resulting in inconvenience. Furthermore, when a circle is displayed in the graphic display mode, the aspect ratio (i.e., a ratio of vertical length to horizontal length on the display screen) is not optimal. The circle is then displayed as an ellipse, resulting in poor display.
- It is an object of the present invention to provide a CRT display control apparatus with a graphic display function, which is compatible with conventional character display software and has an improved aspect ratio (vertical/horizontal ratio) and allows easy graphic processing.
- In order to achieve the above object of the present invention, there is provided a display control apparatus for displaying both character data and graphic data on a single screen by using a CRT character display unit, comprising:
- a character pattern generator for generating a character dot pattern corresponding to one character;
- a graphic memory for storing graphic data;
- means for generating a basic clock signal;
- means for generating a character clock signal by frequency-dividing the basic clock signal;
- means for generating a character dot clock signal having a period 1/n of a period of the character clock .signal so as to set a character display dot number to be n in a one-character display area along a scan direction;
- means for generating a graphic dot clock signal having a period 1/m of the period of the character clock signal so as to set a graphic display dot number to be m in the one-character display area along the scan direction; and
- means for superposing the character data on the graphic data which are generated in response to the character and graphic dot clock signals.
- According to the present invention, the graphic display function can be added to the conventional character display function, and the character display software is compatible even if the graphic display function is added.
- In addition, graphic data can be processed in units of 8 bits, the software operation can be simplified, and the aspect ratio (the vertical/horizontal ratio on the display screen) can be improved.
- Other objects and features of the present invention will be apparent from the following description taken in connection with the accompanying drawings, in which:
- Fig. 1 is a block diagram of a CRT display control apparatus according to an embodiment of the present invention;
- Fig. 2 is a circuit diagram of a display control clock signal generator (DSG) shown in Fig. 1;
- Figs. 3A through 3H and Figs. 4A through 4J are timing charts for explaining the operation of the DSG of Fig. 2, in which Fig. 3A shows a basic clock signal, Fig. 3B shows a character dot clock signal, Figs. 3C through 3F show outputs QO through Q3 from a
counter 93, Fig. 3G shows a load clock signal, Fig. 3H shows a character clock signal, Fig. 4A shows a basic clock signal, Fig. 4B shows a load clock signal, Fig. 4C shows a dot clock signal, Figs. 4D through 4H show outputs QO' through Q4' from ashift register 100, Fig. 4I shows an output Q from a flip-flop 101, and Fig. 4J shows a graphic dot signal; and - Fig. 5 is a representation showing a character and graphic display in a one-character display area.
- Fig. 1 is a block diagram of a CRT display control apparatus according to an embodiment of the present invention. A
character generator 11 receives code data (CD) and a slice address (SA) and generates dot font data for character display. The dot font data from thegenerator 11 is supplied to ashift register 12. Theregister 12 generates serial data in accordance with a character dot clock signal ($CDOT) generated by a display control clock signal generator (DSG) 19. The output from theregister 12 is supplied to an attribute controller 13 together with an attribute data bit from anattribute memory 21. - An output from a
graphic video memory 14 for storing graphic display data is supplied to abuffer register 15 for determining the graphic display timing with reference to the character display timing. A character clock signal ($CHAR) is supplied from thegenerator 19 to theregister 15. An output from theregister 15 is supplied to ashift register 16. Theregister 16 converts the graphic data to serial data in accordance with a graphic dot clock signal ($GDOT) from thegenerator 19. An ORgate 17 receives input data from the controller 13 and theregister 16 and superposes the character display signal on the graphic display signal. The resultant video signal is supplied to a video signal driver (DRV) 18. An output from thedriver 18 is supplied together with horizontal and vertical sync signals (HSYNC/VSYNC) to a display monitor. An internal arrangement of thegenerator 19 is shown in Fig. 2. - Fig. 2 is a block diagram showing the internal .arrangement of the
generator 19 of Fig. 1. A basic clock signal ($32M) from a quartz oscillator (OSC) 91 is supplied to clock input terminals (CK) of a flip-flop 92 and ashift register 100. The frequency of the basic clock signal ($32M) from theoscillator 91 is divided into halves by the flip-flop 92, and a 1/2 frequency- divided signal is supplied to a decimal counter (CNT) 93 and theregister 12 of Fig. 1. Outputs Q3 and Q2 from thecounter 93 are supplied to anOR gate 94. An output from theOR gate 94 is supplied as the character clock signal ($CHAR) to theregister 15 of Fig. 1. The output Q3 and an output QO from thecounter 93 are supplied to aNAND gate 102. An output from theNAND gate 102 is supplied as a load clock signal $LOAD to theregisters NAND gate 102 is supplied to a load input terminal LD of thecounter 93 and aninverter 95. An output (i.e., the Q output from the flip-flop 92) from theinverter 95 is supplied together with the signal $CDOT to an ANDgate 96. An output from the ANDgate 96 is supplied to the DO input terminal of theregister 100 through theOR gate 97. - Outputs Q0' through Q3' from the
register 100 are supplied to the input terminals D1 through D4, respectively, thereof. The output Q2' from theregister 100 is supplied to the D input terminal of the flip-flop 101, and the output QO' is supplied to one input terminal of anOR gate 99. An output Q23' from a flip-flop 101 is supplied to the other input terminal of theOR gate 99. An output from theOR gate 99 is supplied as the signal $GDOT to theregister 16 of Fig. 1. The signal $32M from theoscillator 91 is inverted by aninverter 98, and an inverted signal $32M is supplied to the clock terminal of the flip-flop 101. - Figs. 3A through 3H and Figs. 4A through 4J are respectively timing charts of the signals shown in Figs. 1 and 2. Fig. 5 shows a character and graphic .display in the one-character area. Referring to Fig. 5,
reference numeral 21 denotes a character display dot; and 23, a graphic display dot. - The operation of the CRT display control apparatus having the arrangement described above will be described hereinafter. 10-bit display data consisting of 8-bit dot font data from the
generator 11 and a 2-bit ground signal (GND) is loaded in theregister 12 in response to the signal $LOAD. Theregister 12 generates the display data as bit serial data in response to the signal $CDOT from thegenerator 19. The bit display data is supplied as a video signal (VIDEO) to a CRT monitor (not shown) through theOR gate 17 and thedriver 18. Therefore, as shown in Fig. 5, in the character display mode, the right and left dots corresponding to the ground signal are not displayed, and the dot font data is displayed in the 8-dot area. - Meanwhile, 8-bit graphic display data from the
memory 14 is temporarily stored in the 8-bit buffer register 15 in response to the signal $CHAR so as to adjust the graphic display timing with that of the character display data. The graphic display data obtained through theregister 15 is loaded in theregister 16 in response to the signal $LOAD. Theregister 16 generates bit serial data in response to the signal $GDOT. The graphic display serial output signal is superposed on the character display serial signal by theOR gate 17. The resultant signal is generated through thedriver 18. The period of the signal GDOT is 1/8 of the period of the signal $CHAR. As shown in Fig. 5, the 8-dot graphic display data is displayed in the one-character display area along the horizontal direction (i.e., the scan direction). - The operation of the
generator 19 will be described with reference to Fig. 2, Figs. 3A through 3H, and Figs. 4A through 4J. The 32-MHz basic clock signal $32M (Fig. 3A) from theoscillator 91 is supplied to the .termina1 CK of the flip-flop 92. The flip-flop 92 divides the frequency of the clock signal into halves and generates the 16-MHz character dot clock signal $CDOT shown in Fig. 4C. The signal $CDOT is supplied to the clock input terminal of thecounter 93, so that thecounter 93 is driven. Thecounter 93 generates bit signals QO through Q3, as shown in Figs. 3C through 3F. The signals Q3 and Q2 are supplied to theOR gate 94, and the signals Q3 and QO are supplied to the ANDgate 102. TheOR gate 94 generates the signal $CHAR shown in Fig. 3H. TheNAND gate 102 generates the signal $LOAD shown in Fig. 3G. The period of the signal $CHAR corresponds to the one-dot display time in the character display mode, and the 10 periods (equal to one period of the signal $CHAR) of the signal $CDOT correspond to the display time of the one-character display area along the horizontal direction. - When the AND
gate 96 receives the signal $LOAD of low level and the signal $CDOT of high level, it generates a high level signal. This signal is supplied to the DO input terminal of theregister 100 through theOR gate 97. Theregister 100 generates the signal QO' (Fig. 4D) in synchronism with the basic clock signal $32M. The signal QO' is fed back to the Dl input terminal of theregister 100, so that theregister 100 generates the signal Ql' (Fig. 4E). In the same manner as described above, theregister 100 generates outputs Q2' through Q4' shown in Figs. 4F through 4H. The output Q4' is fed back to the DO input terminal of theregister 100 through theOR gate 97. The shifting described above is repeated. The output Q2' from theregister 100 is supplied to the D input terminal of the flip-flop 101 and is reset by the basic clock signal $32M which is 180° out of phase. The flip-flop 101 generates a signal Q23' delayed by 1/2 of the basic clock period from the signal Q2'. The signal QO' from theregister 100 and the signal Q23' from the flip-flop .101 are supplied to theOR gate 99. TheOR gate 99 generates the signal $GDOT shown in Fig. 4J. The period of the graphic dot clock signal ($GDOT) corresponds to the one-dot display time, and 8 periods (equal to one period of the signal $CHAR) correspond to the display time of the one-character display area along the horizontal direction. As shown in Fig. 5, in the character display mode, 10 dots are displayed horizontally; and in the graphic display mode, 8 dots are displayed horizontally. In the graphic display mode, the display data is processed in byte units, so that the hardware configuration of the memory can be simplified. Software processing using a CPU such as a microprocessor can also be simplified. - In the above embodiment, characters can be displayed with a maximum of 80 characters x 25 lines (2,000 characters). The one-character display area consists of 10 dots x 14 slices. A maximum number of dots to be displayed on the entire screen is 800 x 350. However, in the graphic display mode, a maximum number of dots to be displayed is 640 x 350. In the normal character display mode, since the vertical length is longer than the horizontal length, an aspect ratio (vertical/horizontal ratio) is low. When a circle is to be drawn in the graphic display mode, an ellipse has the vertical major axis. Therefore, when the period of the signal $GDOT is prolonged, the graphic dot display time can be prolonged, thereby improving the aspect ratio and drawing a true circle.
Claims (2)
characterized in that there are provided:
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP207027/84 | 1984-10-04 | ||
JP59207027A JPS6186790A (en) | 1984-10-04 | 1984-10-04 | Crt display controller |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0177889A2 true EP0177889A2 (en) | 1986-04-16 |
EP0177889A3 EP0177889A3 (en) | 1988-11-23 |
EP0177889B1 EP0177889B1 (en) | 1991-09-04 |
Family
ID=16532988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP85112487A Expired - Lifetime EP0177889B1 (en) | 1984-10-04 | 1985-10-02 | Crt display control apparatus |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0177889B1 (en) |
JP (1) | JPS6186790A (en) |
KR (1) | KR900006290B1 (en) |
DE (1) | DE3583982D1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0324515A1 (en) * | 1988-01-11 | 1989-07-19 | Koninklijke Philips Electronics N.V. | Television receiver including a teletext decoder |
EP0525750A2 (en) * | 1991-07-30 | 1993-02-03 | Kabushiki Kaisha Toshiba | Display control apparatus |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5717990A (en) * | 1980-07-05 | 1982-01-29 | Fujitsu Ltd | Character and graphic screen superposition synchronizing system |
JPS5995589A (en) * | 1982-11-25 | 1984-06-01 | シャープ株式会社 | Crt display |
-
1984
- 1984-10-04 JP JP59207027A patent/JPS6186790A/en active Pending
-
1985
- 1985-09-30 KR KR1019850007226A patent/KR900006290B1/en not_active IP Right Cessation
- 1985-10-02 EP EP85112487A patent/EP0177889B1/en not_active Expired - Lifetime
- 1985-10-02 DE DE8585112487T patent/DE3583982D1/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
---|
COMPUTER DESIGN, vol. 23, no. 3, March 1984, pages 181-191, Winchester, Massachusetts, US; B.A. MAY et al.: "VLSI chips combine text and graphics" * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0324515A1 (en) * | 1988-01-11 | 1989-07-19 | Koninklijke Philips Electronics N.V. | Television receiver including a teletext decoder |
EP0525750A2 (en) * | 1991-07-30 | 1993-02-03 | Kabushiki Kaisha Toshiba | Display control apparatus |
EP0525750A3 (en) * | 1991-07-30 | 1995-03-22 | Tokyo Shibaura Electric Co | Display control apparatus |
US5473341A (en) * | 1991-07-30 | 1995-12-05 | Kabushiki Kaisha Toshiba | Display control apparatus |
Also Published As
Publication number | Publication date |
---|---|
KR860003549A (en) | 1986-05-26 |
EP0177889B1 (en) | 1991-09-04 |
KR900006290B1 (en) | 1990-08-27 |
DE3583982D1 (en) | 1991-10-10 |
EP0177889A3 (en) | 1988-11-23 |
JPS6186790A (en) | 1986-05-02 |
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