EP0158217A1 - Circuit arrangement for a danger-indicating installation - Google Patents

Abstract

1. Circuit arrangement for a danger-indicating installation with several indicators (4, 5), which are connected across a two-wire indicating line (2, 3) to a central means having evaluation electronics (20) and which associates the signals supplied by indicators (4, 5) with clearly defined states on the indicators, with a signal level applied to the indicators by the evaluation electronics (20) via indicating line (2, 3) and which is cyclicly keyed, with in each case one counter (43) providing in the indicators (4, 5) and which counts the logic states corresponding to this signal level keying and in the case of identity of the count with an address value in each case preset on each indicator supplies a signal characterizing its state across indicating line (2, 3) to evaluation electronics (20), all the counters (43) being resettable by a resetting signal, characterized in that the resetting signal for the counters (43) of indicators (4, 5) is in the form of a further signal level keying and that the signal characterizing the state, e.g. alarm of fault, of the individual indicator (4, 5) is supplied as a clearly defined, but different signal level to evaluation electronics (20) by the selected indicator (4, 5) within the time interval up to the selection of the next indicator.

Description

The invention relates to a circuit arrangement for a _G eHRMeldeanlage with several detectors, which are connected via a two-wire detection line to a control center having an evaluation electronics, which assigns certain signals supplied by the detectors each defined states on the detectors.

As is known, in the case of hazard detection systems, in general, a plurality of detectors are connected in a detection line to a control center, in which evaluation electronics are accommodated, which are able to evaluate the signals supplied by the individual detectors, in particular voltage levels. Sensors that respond to the hazard to be detected can be used as detectors.

In intrusion alarm systems and fire alarm systems, 20 or 30 individual detectors are connected in series to the control center in a two-wire detection line, whereby each detector is connected between the two wires of the detection line, which in turn is terminated by a line resistance.

A circuit arrangement constructed in this way can display two states at the control center, namely alarm and / or fault.

If, for example, the status "alarm" is displayed at the control center, then an observer does not know which detector, for example the thirty detectors in the detection line, is causing this state. An individual identification of the detector causing the alarm state can possibly only be carried out on site, for example by checking which detector a light emitting diode emits light if each detector is assigned such a light emitting diode which is excited in the alarm state.

It is obvious that the operator of a hazard detection system wants to obtain information from the control center as to which detector of a detection line indicates a certain status, i.e. the individual identification of the detectors should be possible at the control center.

The individual identification of peripheral devices connected to a central unit from industrial control technology and data processing is known per se. In principle, it is also possible to apply this individual identification to a hazard detection system with numerous detectors located in one detection line.

In practice, however, it has been shown that such a procedure is impractical, since the circuit arrangement then required for the hazard alarm system becomes extremely complex technically, so that it cannot be used economically.

Existing hazard detection systems without individual identification of the detectors at the control center can practically not be converted, since the two wires of the detection line have so far not been sufficient for individual identification at the control center.

It is therefore an object of the invention to provide a circuit arrangement for a hazard alarm system with a plurality of detectors which, in the case of only a two-wire alarm line, permits individual identification of the detectors at the control center, which is still compatible with existing hazard alarm systems and which ultimately only requires little effort.

This object is achieved according to the invention in a circuit arrangement according to the preamble of claim 1 in that a signal level applied to the detector by the evaluation electronics is cyclically reversed is keyed that in the detectors a counter corresponding to this voltage level shift keying counts logical states, that if the counter value is identical with an address value preset for each detector, the detector outputs a signal characterizing its state via the detector line to the evaluation electronics, and that the counters can all be reset by another signal level shift keying or by a reset signal with the same signal level as when counting and with a different pulse width.

Advantageous developments of the invention result in particular from the subclaims.

The circuit arrangement according to the invention is compatible with existing hazard alarm systems, i.e. the detectors provided for in the invention can be retrofitted into already installed hazard alarm systems without any great effort. A two-wire detector line is sufficient, since this detector line not only supplies the individual detectors with the operating voltage, but also handles all data traffic. Finally, the outlay for the circuit arrangement according to the invention is very low, which is also expressed in that the space requirement for the circuit arrangement is minimal.

In the inventive circuit arrangement the signal or voltage level of the transmitter eldelinie at the _M and cyclically shift keyed to the individual detectors or reduced. Logic signals with the value O or 1 are obtained from these voltage drops, for example by means of comparators in the individual detectors, which signals are then fed to a binary counter as counting pulses. This binary counter counts the logical signals in the individual detectors, for example from 1 to 32. This means that as often as the voltage on the detector line is reduced to the specified voltage value, the counter switches by the value 1. The voltage at the detector line could also be increased, in which case the counter would advance by the value 1 with each increase.

Once a particular count is reached in the individual counters, such as the count of 32, all counters are reset to the value 0 by a different, several of the above-mentioned voltage drop voltage reduction is performed on the _M eldelinie, said other voltage reduction as by the comparator Reset signal is evaluated. Instead of this other voltage drop, a reset signal can also be used which has the same voltage level as the counter pulses and differs from them by a larger or smaller pulse width.

In the inventive circuit arrangement that is, the counter "count" can (= _U mtasten to a first voltage level during a first time period) in all the detectors of the two control signals and "reset" (= keying second with a second, different from the first voltage value voltage value during a , time period different from the first time period) are counted up cyclically and reset together. Instead of the different voltage values, the reset signal can also have the same voltage value as the counter pulses and differ from them by the different pulse width.

Only if the counter content of the counter of each detector matches a value set in the detector by means of a coding switch, the so-called detector address, can the detector transmit information back to the control center. This means that if the detector address matches the meter reading, certain signals can be sent to the control center, for example a precisely defined current increase. the status of the relevant detector can be given via the detection line, which is evaluated accordingly by the control center.

So that the function of the detectors and the detection line is always monitored, each addressed detector reports back with a precisely defined current increase if the counter reading is the same as the detector address. If this feedback is not given, a sabotage and / or fault message is sent to the control center.

• _Fig. 1 ein Blockschaltbild einer bestehenden Gefahrenmeldeanlage,
• _Fig. 2 ein Blockschaltbild der erfindungsgemäßen Schaltungsanordnung und
• Fig. 3 Signaldiagramme zur Erläuterung des Betriebs der Schaltungsanordnung von Fig. 2.

The invention is explained in more detail below with reference to the drawing. Show it:

• _F ig. 1 shows a block diagram of an existing alarm system,
• _F ig. 2 shows a block diagram of the circuit arrangement according to the invention and
• 3 shows signal diagrams for explaining the operation of the circuit arrangement from FIG. 2.

1 shows an existing alarm system with a control center 1, to which a two-wire alarm line 2, 3 with individual detectors 4, 5, 6 and an alarm line terminating resistor 7 are connected. For example, 20 or even 32 different detectors 4, 5, 6,... Can be connected to the control center 1 in this way. Each detector 4,5,6 lies between the two wires of the detection line 2,3.

A display 8 is provided on the control center 1, in which, for example, an alarm can be reported by means of a light-emitting diode 9 and a fault can be reported by means of a light-emitting diode 10.

If, for example, the light emitting diode 10 lights up, an observer does not know which of the detectors 4, 5, 6 is malfunctioning. A check must therefore be carried out on site, which can be done by assigning a light emitting diode 14, 15, 16 to each detector 4, 5, 6, which emits light if the associated detector 4, 5 or 6 has a fault or an alarm is given. If the light-emitting diode 10 lights up, then it must be checked which of the light-emitting diodes 14, 15, 16 also emits light, which in the case of a large alarm system, for example with 32 different detectors can be extremely complex.

The same reference numerals are used in FIG. 2 for corresponding components as in FIG. 1

2 shows a block diagram of the circuit arrangement according to the invention. This consists of the control center 1, the detector line 2, 3, the two detectors 4, 5 and the detector line end resistor 7. The detector line end resistor 7 can be omitted in the present exemplary embodiment, since it works with cyclical feedback. Of course, 32 different detectors can also be connected between the detection line 2, 3 in this exemplary embodiment. For better clarity, only the detector 4 is shown in detail, while the detector 5 is only indicated schematically.

The control center 1 essentially consists of evaluation electronics 20 having a memory, to which voltage comparators K1, K2 and K3 or a commercially available analog / digital converter are connected, each of which is preceded by an operational amplifier IC1 for "lossless current measurement" (cf. EP- OS 0098326).

The operating voltage U _B is fed via a line 21 and a resistor 22 to the positive input of the operational amplifier IC1 and is also connected to the negative inputs of the voltage comparators K1, K2 and K3 via resistors 23, 24, 25. The positive inputs of the voltage comparators K1, K2 and K3 are connected to the output of the operational amplifier IC1, the negative input of which is fed back to the output thereof via a resistor R1.

The positive input of the operational amplifier IC1 is connected via resistors 26, 27, 28 to the ground wire 3 of the detection line 2, 3, the center bar between the resistors 26 and 27 or between the resistors 27 and 28 being connected to the collector Transistors T1 and _T 2 is connected. The emitters of these transistors T1 and _T 2 are connected to the wire 3, while the base connections are each connected to the evaluation electronics 20 via resistors 29, 30.

Finally, there is a resistor 31 between the negative input of the voltage comparator K1 and the wire 3 of the detection line 2, 3.

On the output side of the evaluation electronics 20 are a seven-segment display 32 for the detector number, a light-emitting diode 33 for the alarm display, a light-emitting diode 34 for the fault display and keys TA1 and TA2 for actuating the detector display 32 or Forwarding of the detector number provided.

A voltage UM + ΔUM is applied by the control center 1 between the wires 2, 3 of the detection line. The individual detectors 4, 5 report the respective state by increasing the current △ IM, i.e. the current IM flowing in the wire 2 is increased by △ IM when a certain state is detected, for example in the event of a fault.

The specific current increases aIM are converted in the control center 1 by the operational amplifier IC1 into a corresponding voltage UA1.

The comparator from the three voltage comparators K1, K2 and K3 then evaluates the voltage value UA1 output by the operational amplifier IC1, whereby there is a detector feedback if this voltage _value corresponds to a reference voltage U _Ref1 , while a detector alarm is given if the voltage UA1 is equal to a reference voltage U _Ref2 . Finally, there is a detector fault if the voltage value _{UA1 is} equal to the reference voltage value U _Ref3 . The voltage values from the operational amplifier IC1 could also be evaluated by means of a commercially available analog / digital converter, which converts an analog voltage value fed into it into an equivalent digital value, which is then processed in the evaluation electronics 20 in accordance with the criteria "alarm", "fault". and "feedback" is evaluated.

The current increase △ IM corresponding to a specific detector state is thus converted by the operational amplifier _IC1 into a voltage increase UA1, which in turn is compared with certain reference voltages, so that - depending on the determined voltage increase - an observer from via the displays 32, 33 and 34 can be reported to the evaluation electronics 20, which detector 4 5 which detector state is present.

The detector 4 (and likewise the other detectors 5, etc.) consists of detection and evaluation electronics 40 for detecting physical variables, such as smoke, heat, movement, etc. This evaluation electronics 40 supplies appropriate signals for the status of the detector 4, signals for alarm, malfunction, etc.

An input demodulator 41 consists of voltage comparators K4 and K5, which generate signals "counting" and "resetting" by comparing the _signaling line voltage UM offered in each case with reference values U _Ref4 and U _Ref5 and a downstream logic 42. These signals can differ in terms of different signal levels and / or pulse widths.

A 5-bit BCD counter 43 ählfolge with outputs Q1 to Q5 und.einer _Z "OOOOO" to "11111" is in each case incremented by the signal "Count" by the logic 42 by the value +1 and with the signal "Reset "reset by logic 42 to the value" OOOOO ".

The 5-bit BCD counter 43 is connected to a 5-bit comparator 44 via its outputs Q1 to Q5 and supplies it with input signals A. Furthermore, a 5-pin coding switch 45 is located on the 5-bit comparator 44, with which the detector number 1 to 32 can be set for a total of ₃₂ detectors. In this way, the coding switch 45 supplies the 5-bit comparator 44 with an input signal B. If the two input signals A and B are identical, the 5-bit comparator generates a logic 1 as an output signal a transistor output stage 46 is released from resistors 47, 48, 49, 50 and transistors T3 and T4. Ie, if signals A and B are identical, a current increase △ IM is passed on to signaling line 2, 3 through this transistor output stage, this current increase △ IM being dependent on the state of detector 4, which is detected by evaluation electronics 40.

In the event of a detector feedback, the transistor T4 is activated, while when the transistor T3 is activated there is an alarm and an activation of the two transistors T3 and T4 means a fault.

The detector 4 also has a voltage regulator 51 between the wire 2 and the evaluation electronics 40, a diode 52 and a capacitor 53 between the two wires 2, 3, resistors 54, 55 and 56 for setting the reference voltage _{en URef4} and _{U Ref5} between the output of the controller 51 or the input of the evaluation electronics 40 and the wire 3 and a resistor 57 between the wire 2 and the negative input of the voltage comparators K4 and K5. Finally, there is a logic 58 between the output of the evaluation electronics 40 and the resistors 47, 48 for generating the "fault" and "alarm" signals.

The evaluation electronics 20 cyclically control the transistors T1 or T2 via the resistors 29, 30, as a result of which the reference voltage value at the non-inverting input of the operational amplifier IC1 is also changed cyclically. As a result of the negative feedback of the operational amplifier IC1 given by the resistor R1, the signal line voltage UM then changes by the same voltage amount.

That is, at the beginning of each interrogation cycle of the transistor _T 1 is supplied with the time t ₁ is driven and conductive, whereby the _M elde- line voltage UM drops to a value UM3. The transistor T1 is then blocked and the signal line voltage rises again to its initial value UM1. This voltage value UM1 is maintained for a period of time t ₂ . Then, the transistor T2 is conducting, which means that the _M eldelinien- voltage UM during the time period t ₃ to a value UM2 decreases.

3 (A), these voltage values UM1, UM2 and UM3 are shown.

• Bei der Spannung UM3 werden die Zähler 43 der einzelnen Melder 4,5 rückgestellt.

The voltage key changes to the voltage values UM1, UM2 and UM3 mean the following states of the detectors:

• At the voltage UM3, the counters 43 of the individual detectors 4, 5 are reset.

The pulses corresponding to the voltage values UM2 are counted by the binary counters 43 of the individual detectors 4, 5 until, for example, the value 32 is reached.

The voltage value UM1 finally corresponds to normal operation, i.e. a polling cycle in which the status of the individual detectors 4, 5 is polled by the control center.

The voltage values UM1, UM2 and UM3 which are present at the detection line 2, 3 are registered, recorded and evaluated by all connected detectors 4, 5. The voltage comparators K4 and K5 derive from the voltage values whether the counter 43 should continue to count or whether this counter 43 should be reset. A working cycle begins with a reset signal, ie with the signal in which the voltage value UM3 is present during the time period t ₁ . Such a signal is shown e in Fig. 3 (B) ^g. This reset signal causes in all _M-fields 4.5, the counter 43, for example, reset to the counter reading "00000".

A voltage jump to the voltage value UM2 during the time period t ₂ generates a counting pulse, which means that in a hazard detection system with, for example, 30 detectors, the respective counters 43 are counted up cyclically from 1 to 30 ("OOOOO" to "11110"). These signals are in Fi ^g . 3 (C).

The 5-bit comparator 44 now statically compares the BCD value B set with the coding switch 45 with the counter content of the counter 43. If the counter reading of the counter 43 and the detector number set by the coding switch 45, ie the address, the output of the comparator 44 is activated, whereby the transistors T3 and T4 are switched on.

Depending on the state of the detector 4 detected by the evaluation electronics 40, a corresponding current increase is carried out at the detection line 2, 3 when the transistors T3 and T4 are switched on. If there is an alarm, transistor T3 is activated and the current increase △ IM is UM / R. In the event of a fault, the transistors T3 and T4 are activated and the current increase AIM is UM / 3R, since the resistor 49 is said to have twice the resistance value as the resistor 50.

3 (D), 3 (E) and 3 (F) each show the output signals of the comparator 44 (prerequisite: A = B) for the second, fourth and sixth detector of a detector line (cf. FIG. 3 in this regard) (C)).

3 (G) shows the corresponding signals which report to the control center 1 which state (detector feedback or alarm or fault) is present.

In order to also be able to check the function of the individual detectors and the detection line _{2, 3} , each detector must report back with a defined current increase △ IM = UM / 2R during its addressed time t ₃ . If there is no such feedback, a malfunction or sabotage is displayed on the control center 1.

The defined current increase related to each detector is evaluated in the control center 1 or in the evaluation electronics 20.

As already explained at the beginning, the output voltage UA1 of the operational amplifier IC1 changes in accordance with the current change △ IM in the detection line 2, 3. The output voltage UA1 of the operational amplifier IC1 is therefore proportional to the current change △ IM.

Depending on the level of the output voltage UA1 of the operational amplifier IC1, the comparators K1, K2 and K3 are then activated so that the information corresponding to the respectively addressed detector 4, 5 (alarm, fault, feedback) is present at the evaluation electronics 20. This information is evaluated and displayed 32, 33 and 34.

By pressing the TA1 key, the display 32 can be used to show which detector has triggered an alarm and / or a fault. The fault is indicated by the LED 34, while the LED 33 lights up when there is an alarm on one of the detectors.

Using the TA2 key, it is possible to successively advance the detector number by the amount +1, i.e. the display 32 is increased by the value +1. Pressing the TA1 key again can finally exit the display mode.

3 (H), 3 (I) and 3 (J) each show a signal which reports a "feedback", an "alarm" or a "fault" of the evaluation electronics 20. Fig. 3 (K) are ultimately the result of the evaluation by the evaluation unit 20 on: it is there namely, a feedback of the second detector the signal line 2.3, an alarm of the fourth _M elders the detection line 2.3 and disturbance of the sixth _M elders of the reporting line 2.3 shown.

Claims (12)

1. Circuit arrangement for a hazard detection system with a plurality of detectors (4, 5), which are connected via a two-wire detection line (2, 3) to a control center (1) having evaluation electronics (20), which determine the detectors (4, 5 ) assigns the delivered signals to defined states on the detectors (4,5),
characterized,
that a signal level applied to the detectors (4, 5) by the evaluation electronics (20) via the detection line (2, 3) is cyclically keyed,
that in the detectors (4, 5) each have a counter (43) corresponding to this signal level shift keying logical states that, if the counter value is the same as an address value preset by each detector (4, 5) on the detector (4, 5) its state characterizing signal is sent to the evaluation electronics (20) via the detection line (2, 3), and
that the counters (4,5) can all be reset by another signal level shift keying or by a reset signal with the same signal level as when counting and with a different pulse width. 2. Circuit arrangement according to claim 1, characterized in that the evaluation electronics (20) are connected to voltage comparators (K1, K2, K3) or analog / digital converters which compare the input signals supplied to the evaluation electronics (20) in each case with a reference voltage value. 3. Circuit arrangement according to claim 1 or 2, characterized in that in the center (1) between the input of the detection line (2,3) and the voltage comparators (K1, K2, K3) is an operational amplifier (IC1). 4. Circuit arrangement according to claim 3, characterized in that the operational amplifier (IC1) is negative-coupled via a resistor (R1) in a manner known per se. 5. Circuit arrangement according to one of claims 1 to 4, characterized in that the evaluation electronics (20) via a transistor stage (Tl, T2) and series resistors (26,27,28) to the detection line (2,3) defined voltage level (UM) sets. 6. Circuit arrangement according to one of claims 1 to 5, characterized in that the address value on each detector (4,5) by means of a coding switch (45) can be entered. 7. Circuit arrangement according to claim 6, characterized in that a comparator (44) is provided between the coding switch (45) and the counter (43). 8. Circuit arrangement according to one of claims 1 to 7, characterized in that each detector (4,5) is equipped with evaluation electronics (40) for the physical quantities to be detected. 9. Circuit arrangement according to claim 8, characterized in that the evaluation electronics (40) is followed by logic (58) and a transistor stage (T3, T4). 10. Circuit arrangement according to claim 9, characterized in that the transistors of the transistor stage (T3, T4) are released if the counter value in the counter (43) is the same as the address value preset on each detector (4, 5) by the coding switch (45). 11. Circuit arrangement according to one of claims 1 to 10, characterized by a comparator (41) upstream of the counter (43) comprising two comparators (K4, K5), which evaluate the signals from the control center (1) to the detection line (2, 3). 12. Circuit arrangement according to claim 11, characterized by logic (42) between the comparators (K4, K5) and the counter (43).

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