EP0151430B1 - Detector - Google Patents

Detector Download PDF

Info

Publication number
EP0151430B1
EP0151430B1 EP85100645A EP85100645A EP0151430B1 EP 0151430 B1 EP0151430 B1 EP 0151430B1 EP 85100645 A EP85100645 A EP 85100645A EP 85100645 A EP85100645 A EP 85100645A EP 0151430 B1 EP0151430 B1 EP 0151430B1
Authority
EP
European Patent Office
Prior art keywords
manchester
bit
data
signal
shift register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP85100645A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0151430A2 (en
EP0151430A3 (en
Inventor
Tony J. Kozlik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Publication of EP0151430A2 publication Critical patent/EP0151430A2/en
Publication of EP0151430A3 publication Critical patent/EP0151430A3/en
Application granted granted Critical
Publication of EP0151430B1 publication Critical patent/EP0151430B1/en
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/417—Bus networks with decentralised control with deterministic access, e.g. token passing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Definitions

  • This invention relates to a detector according to the preamble of claim 1, and more particularly to a detector of predetermined patterns of values corresponding to the voltage levels of the half-bit cells of a given sequence of Manchester bit cells, some of which Manchester bit cells represent code violations.
  • token-passing local-area networks In some token-passing local-area networks, a single communication medium is shared by many modules. Such a network is already disclosed in former European patent application 84 111 709.6 concerning a "Plant Management System". In such a token-passing local-area network, a module which has accepted the token from another module has exclusive access to the medium to transmit information to other modules, normally for a limited period of time, at the end of which period the module having the token must transfer the token to another successor module in the network.
  • both tokens and information frames include a start-of-frame delimiter (SFD) and an end-of-frame delimiter (EFD).
  • SFD start-of-frame delimiter
  • EFD end-of-frame delimiter
  • BIU bus interface unit
  • the informational content of a Manchester bit cell is deemed a logical zero if the signal voltage level is initially low, a logical zero, in the first half-bit cell of the Manchester cell, and high, a logical one, in the second half-bit cell of the Manchester bit cell.
  • a mid-bit low-to-high voltage transition thus occurs in the middle of a Manchester bit cell, the informational content of which is a logical zero.
  • the informational content of a Manchester bit cell is deemed a logical one if the signal voltage level initially is high, a logical one, in the first half-bit cell; and low, a logical zero, in the second half-bit cell of the Manchester bit cell.
  • a mid-bit high-to-low voltage transition thus occurs in the middle of a Manchester bit cell, the informational content of which is a logical one.
  • Manchester encoding requires that there is a voltage transition, high-to-low or low-to-high, in the middle of each Manchester bit cell, a mid-bit transition. If no such mid-bit transition occurs in a Manchester bit cell, a code violation (CV) occurs.
  • CV code violation
  • both start-of-frame delimiters (SFD) and end-of-frame delimiters (EFD) include code violations, four CV's each.
  • CV's By using CV's in such a manner, a four-bit error would have to occur to change valid Manchester encoded data into a frame delimiter.
  • bus interface unit BIU
  • each module of the network must be able to identify in real time the unique patterns of Manchester encoded data which denote a start-of-frame and an end-of-frame delimiter since the address of the module, or modules, to which each frame is addressed immediately follows an SFD; and an EFD denotes, particularly to the module to which a token frame is addressed, that that module has the token and must transmit an information frame or transmit a token frame addressed to a successor module.
  • the detector of this invention detects in real time predetermined patterns of Manchester encoded data signals as applied serially to the detector, which signals include data signals representing Manchester code violations.
  • the voltage level of each half-bit cell of each Manchester bit cell is clocked into a shift register capable of storing the voltage levels, or logic signals, of "n" Manchester bit cells, or 2 "n” half-bit cells, where "n", in the preferred embodiment, is eight.
  • a receive clock signal from a decoder, which receive clock signal has a voltage transition of the desired polarity, or direction, substantially in the center of each half-bit cell of each Manchester bit cell of Manchester encoded data signals is applied to the detector.
  • the logic values of the 2 "n" outputs of the shift register are applied to a programmable logic array device which produces an output signal every time the logic values of the 2 "n” outputs of the shift register have values satisfying the predetermined pattern.
  • Outputs of the programmable logic array device can be stored in latches for use by other components of the module of which the bus interface unit is a part as long as needed.
  • Manchester decoder 10 has applied to it Manchester encoded data signals such as are transmitted over the communication medium of a local-area network, which medium, in the preferred embodiment, is a pair of coaxial cables, or channels, over both of which the data signals are transmitted.
  • One such channel is designated as the primary channel and is used as the source of the data signals PRICHL+ applied to decoder 10.
  • the data signals PRICHL+ are also applied to data input terminal B of serial-in parallel-out shift register 12-1.
  • Decoder 10 produces a receive clock signal RCVCLK+ having the desired type of voltage transition substantially in the center of each half-bit cell of each Manchester bit cell of PRICHL+ applied thereto.
  • Decoder 10 also produces the signal RCVCLK+E, which is the RCVCLK+ signal delayed for a predetermined period of time for a reason that will be set forth below.
  • RCVCLK+E is delayed by substantially 50 nanoseconds.
  • the RCVCLK+ signals are applied to the clock terminals CK of shift registers 12-1 and 12-2.
  • the master reset terminals MR and data input terminals A of registers 12-1 and 12-2 are both tied to a source of high voltage, a logic one.
  • the B data input terminal of shift register 12-2 is connected to output 8 of register 12-1, the output of which is identified on Figure 1 as signal RECV4A.
  • shift registers 12-1 and 12-2 are type F164's, a high-speed 8-bit serial-in parallel-out shift register. Serial data is entered through a two-input terminal AND gate synchronously with the low-to-high transition of the RCVCLK+ applied to the clock inputs CK. By connecting registers 12-1 and 12-2 as illustrated in Figure 1, a serial-in parallel-out shift register with 16 outputs, the number of half-bit cells found in eight Manchester encoded bit cells is produced.
  • each of the wave forms 14, 16 are located indicia which divide the wave forms 14, 16 into Manchester bit cells with the informational content, or value, of each Manchester bit cell being identified.
  • the values of each Manchester bit cell from left to right are 0, CV, CV, 0, 1, CV, CV, 1, where CV represents a code violation that occurs in a Manchester bit cell; i.e., one that is not encoded as required by the Manchester coding convention in that no mid-bit code transition occurs.
  • the values of each Manchester bit cell from left to right is 1, CV, CV, 1, 0, CV, CV, 0.
  • each half-bit cell of each of the Manchester bit cells forming an SFD 14 and an EFD 16 is the logical values, or the voltage levels, of each half-bit cell of each of the Manchester bit cells forming an SFD 14 and an EFD 16.
  • the logical values for the half-bit cells of SFD 14 are from left toright 0,1,1,1,0,0,0,1,1,0,0,0,1,1,1,0, and for EFD 16,1,0,0,0,1,1,1,0,0,1,1,1,0,0,0,0,1.
  • the 16 outputs of registers 12-1 and 12-2 are applied to programmable array logic device 18, a type 16H2 programmable logic array.
  • Device 18 is, in the preferred embodiment, programmed to produce a receive start-of-frame delimiter RCVSFD+ when the following logic equation is true: and will produce a receive end-of-frame delimiter RCVEFD+ when the following equation is true:
  • the signal RCVSFD+ is applied to one input of two input NAND gate 20.
  • the other input to NAND gate 20 is the signal RCVCLK+E.
  • RCVCLK+E enables gate 20 and is delayed with respect to the RCVCLK+ signal to compensate for the time it takes to produce the signal RCVSFD+ from the outputs of registers 12-1 and 12-2.
  • latch 22 is set and produces the signal start-of-frame delimeter detected, SFDDET+.
  • the signals RCVEFD+, RCVCLK+E and SFDDET+ are applied as inputs to three-input NAND gate 24.
  • latch 26 When all three inputs to NAND gate 24 are high, or true, at the same time, latch 26 is set and produces as its outputs a signal representing that the end-of-frame delimiter has been detected, EFDDET+.
  • the signal RCVABRT+ is applied to both latches 22, 24 to clear or reset them whenever a frame is detected, for example, which is not addressed to a given module of a local-area network, or after the frame has been received by the module to which it has been addressed.
  • a token-passing frame 28 includes from 8-10 bytes of a preamble.
  • Preamble 32 consists of signals of the same type, such as logical ones.
  • Preamble 32 is followed by a start-of-frame delimiter, SFD 14 of one byte, destination address field 34 of two bytes, a source address field 36 of two bytes, a frame check sequence 38 which is used to detect errors in token frame 28, and an end-of-frame delimeter EFD 16 of one byte.
  • the format of information frame 40 which is illustrated in Figure 4, differs from that of token frame 28 only by including an information field 42 of from 100-4,088 bytes in the preferred embodiment.
  • all frames of the local-area network include a start-of-frame delimiter SFD 14 and an end-of-frame delimiter EFD 16, the importance of the bus interface units of the modules of a local-area network being able to detect the unique and predetermined patterns of logic values of each half-bit cell of an SFD 14 and an EFD 16 is apparent.
  • the detector of this invention has the capability of detecting in real time predetermined patterns of Manchester encoded data signals and, in particular, the capability of detecting such patterns when the encoded data signal includes code violations.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
EP85100645A 1984-01-26 1985-01-23 Detector Expired EP0151430B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/573,899 US4631695A (en) 1984-01-26 1984-01-26 Detector of predetermined patterns of encoded data signals
US573899 1984-01-26

Publications (3)

Publication Number Publication Date
EP0151430A2 EP0151430A2 (en) 1985-08-14
EP0151430A3 EP0151430A3 (en) 1987-08-26
EP0151430B1 true EP0151430B1 (en) 1990-05-16

Family

ID=24293835

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85100645A Expired EP0151430B1 (en) 1984-01-26 1985-01-23 Detector

Country Status (6)

Country Link
US (1) US4631695A (enrdf_load_stackoverflow)
EP (1) EP0151430B1 (enrdf_load_stackoverflow)
JP (1) JPS60217751A (enrdf_load_stackoverflow)
AU (1) AU571921B2 (enrdf_load_stackoverflow)
CA (1) CA1237816A (enrdf_load_stackoverflow)
DE (1) DE3577790D1 (enrdf_load_stackoverflow)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4542420A (en) * 1984-01-24 1985-09-17 Honeywell Inc. Manchester decoder
US4766569A (en) * 1985-03-04 1988-08-23 Lattice Semiconductor Corporation Programmable logic array
US4752841A (en) * 1986-12-19 1988-06-21 Eastman Kodak Company Address mark encoding for a record storage medium
US4847831A (en) * 1987-03-30 1989-07-11 Honeywell Inc. Bidirectional repeater for manchester encoded data signals
GB2303263A (en) * 1995-07-08 1997-02-12 Measurement Tech Ltd Conversion of pulse stream into Fieldbus data stream.
US5682405A (en) * 1995-09-29 1997-10-28 Dallas Semiconductor Corporation Ones density monitor
US6064705A (en) 1997-08-20 2000-05-16 Sarnoff Corporation Manchester encoding and decoding system
JP2003526222A (ja) * 1997-08-20 2003-09-02 サーノフ コーポレイション 遠隔車両データインタフェースタグシステム
US7170870B2 (en) * 2002-05-07 2007-01-30 Microsoft Corporation Data packet transmission for channel-sharing collocated wireless devices
JP2007221655A (ja) * 2006-02-20 2007-08-30 Oki Electric Ind Co Ltd 無線装置およびその電力制御方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818348A (en) * 1971-05-17 1974-06-18 Communications Satellite Corp Unique word detection in digital burst communication systems
US3747067A (en) * 1971-08-30 1973-07-17 American Multiplex Syst Inc Method and apparatus for data transmission
US3760355A (en) * 1972-03-08 1973-09-18 Motorola Inc Digital pattern detector
GB1425033A (en) * 1972-03-10 1976-02-18 Hendrickson A E Data signal recogniion apparatus
US3855576A (en) * 1973-05-29 1974-12-17 Motorola Inc Asynchronous internally clocked sequential digital word detector
SE384115B (sv) * 1973-11-22 1976-04-12 Ericsson Telefon Ab L M Anordning for verifiering av att en mottagen signal innehaller ett visst pulsmonster
US3979746A (en) * 1975-04-28 1976-09-07 The United States Of America As Represented By The Secretary Of The Navy High-speed Manchester code demodulator
US4246569A (en) * 1977-07-14 1981-01-20 Independent Broadcasting Authority Digital recognition circuits
US4205302A (en) * 1977-10-28 1980-05-27 Einar Godo Word recognizing system
US4404542A (en) * 1980-12-05 1983-09-13 Rca Corporation Digital sequence detector
US4542420A (en) * 1984-01-24 1985-09-17 Honeywell Inc. Manchester decoder

Also Published As

Publication number Publication date
CA1237816A (en) 1988-06-07
AU3807885A (en) 1985-08-01
DE3577790D1 (de) 1990-06-21
JPS60217751A (ja) 1985-10-31
US4631695A (en) 1986-12-23
EP0151430A2 (en) 1985-08-14
JPH0462503B2 (enrdf_load_stackoverflow) 1992-10-06
EP0151430A3 (en) 1987-08-26
AU571921B2 (en) 1988-04-28

Similar Documents

Publication Publication Date Title
EP0150072B1 (en) Decoder
US5781129A (en) Adaptive encoder circuit for multiple data channels and method of encoding
CA1193687A (en) Circuitry for allocating access to a demand-shared bus
EP0443754A2 (en) Method and apparatus for detecting a frame alignment word in a data stream
US20030007514A1 (en) Relay-to-relay direct communication system in an electric power system
EP0151430B1 (en) Detector
EP0735729B1 (en) 5B4T coding scheme
US4563546A (en) Method for preventing "compromising radiation"
CN107786471B (zh) 多fpga芯片间数据处理方法及转换装置
EP0735728B1 (en) 5B4T coding scheme
US5142556A (en) Data transfer system and method of transferring data
KR0150211B1 (ko) 네트워크 전송 매체로부터 네트워크상의 스테이션으로 데이타를 전송하기 위한 코드 포인트
US4823305A (en) Serial data direct memory access system
EP0155058A2 (en) A method of, and a circuit for, estimating true data from distorted digital data signals
US3747067A (en) Method and apparatus for data transmission
US4658399A (en) Circuit arrangement designed to pick up the error rate in numerical transmission systems
US4967193A (en) Digital loop carrier system having CPU to channel unit protocol
US5101198A (en) Method and device for the transmission of data between stations of a communications network, in particular for motor vehicles
US4553129A (en) Data transmission by subrate grouping
JPH0143499B2 (enrdf_load_stackoverflow)
US4788605A (en) Receive Manchester clock circuit
US6049571A (en) Encoding circuit with a function of zero continuous-suppression in a data transmission system
EP1419629B1 (en) Crosstalk equalization for digital transmission lines
US5859857A (en) Method for the integration of additional data in digital data packets
CA2020343C (en) Time-division multiplex communication system with a synchronizing circuit at the receiving end which responds to the coding of words inserted in the transmitted information

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): BE DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): BE DE FR GB

17P Request for examination filed

Effective date: 19880204

17Q First examination report despatched

Effective date: 19891025

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): BE DE FR GB

REF Corresponds to:

Ref document number: 3577790

Country of ref document: DE

Date of ref document: 19900621

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19931214

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19931220

Year of fee payment: 10

Ref country code: DE

Payment date: 19931220

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 19931222

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19950123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Effective date: 19950131

BERE Be: lapsed

Owner name: HONEYWELL INC.

Effective date: 19950131

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19950123

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19950929

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19951003

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST