EP0148191A1 - Systeme de communications numeriques - Google Patents

Systeme de communications numeriques

Info

Publication number
EP0148191A1
EP0148191A1 EP19840901719 EP84901719A EP0148191A1 EP 0148191 A1 EP0148191 A1 EP 0148191A1 EP 19840901719 EP19840901719 EP 19840901719 EP 84901719 A EP84901719 A EP 84901719A EP 0148191 A1 EP0148191 A1 EP 0148191A1
Authority
EP
European Patent Office
Prior art keywords
lines
communication
data
nodes
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19840901719
Other languages
German (de)
English (en)
Inventor
Clifford Bellamy
Neil Clarke
Peter Gordon
Keith Heale
Patrick Miller
Barry Treloar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Monash University
Original Assignee
Monash University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Monash University filed Critical Monash University
Publication of EP0148191A1 publication Critical patent/EP0148191A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
    • H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
    • H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Definitions

  • the present invention relates to a system of communication with between at least two computers devices and more particularly a digital data communication system incorporating one or more communication bus adaptors consisting of two or more micro-processors and communication interfaces to the bus pathway and to serial communication lines to terminals, computers and to remote bus adaptors forming part of the other local networks.
  • CSMA-C0 Carrier- sense Multiple Access with Collision-detection
  • each node Before transmitting, each node monitors the state of the bus. A node begins to transmit only if the bus is sensed to be idle. 2. While transmitting a node tests the signal on the bus to detect interference from other nodes. This can occur if two or more nodes begin transmitting almost simultaneously. When this happens a "collision" is said to have occurred; i.e. two (or more) messages have "collided” on the bus.
  • the Carrier-sense Multiple-access method imposes certain requirements on the encoding and decoding sections of the transmitters and receivers used in the nodes:
  • the receiver must be able to proces both the transmissions from nearby nodes (large signal amplitude), and the most distant nodes on the bus (small signal amplitude); i.e. the receiver is required to have adequate cynamic range.
  • the receiver In order to detect collisions the receiver must be able to detect a distant (weak) signal in the presence of a strong signal.
  • the receiver be able to detect unequivocally whether the bus is busy or idle.
  • a principal objective of the present invention is the simple recovery of a timing reference signal (received clock) in a receiver
  • the operation of the receiver is not affected by the polarity of the received signal; (i.e. the two wires of a balanced medium such as a twisted-wire pair can be reversed without affecting the ability of the receiver to operate) ;
  • the transmitted signal has not direct current components. This allows transformer-coupling between the nodes and the bus.
  • a local area network data communications system of the type providing communication between at least a pair of computer devices interfaced with associated communication nodes 52, said nodes including a transceiver 50, 51, wherein said nodes are commonly connected to a pair of communication lines 53, 54, said lines extending throughout the local area network, said lines carrying transmitted signals, each node being adapted to transmit or receive said data to and from said lines. More specifically one communication line carries binary one signals and the other line carried binary zero signals.
  • the data communication lines include non-interacting twisted wire pairs, as a pair of co-axial or twin-axial cables.
  • the nodes perform the encoding of benary data into a form suitable for transmitting on the communication lines having equal signal capacity as bandwidth, and the decoding of data received from both lines.
  • the line coding method of the present invention does not require a "preamble" thus representing a saving in overheads particularly with short messages.
  • the two communication lines which are preferably balanced such as a twisted wire pair can be reversed without affecting the ability of the receiver or transmitter to operate.
  • the nodes include means to detect and signal the existence of
  • Figure 1 is a schematic block diagram showing cable pairs and node connections.
  • Figures 2 and 4 are a schematic diagram of a transmitter and receiver in a node respectively.
  • Figures 3 and 5 show pulse diagrams.
  • Each node 52 is connected to non-interacting cables 53 and 54-
  • the cables may be twisted pairs, co- or twin- axial cables.
  • Each node is controlled by one or more micro processors (not shown) to manage the storage of data in the node, the sequencing of packets of data and the control of the transmitter and receiver sections. For example, when a collision is indicated a node micro-processor is intercepted and a re-transmission procedure is commenced according to a program executed by the micro-processor. Transmitter in the node.
  • Inputs to the transmitter 50 are a clock signal, serial non-return-to-zero (NRZ) binary data synchronous with the clock signal, and optionally an enable signal.
  • NRZ serial non-return-to-zero
  • the timing reference or clock signal is a symmetrical square wave signal of period T seconds whose positive transitions delimit each serial data bit; i.e, the data signal only changes state on positive transitions of the clock.
  • the clock signal is HIGH for the first half (T/2 seconds) of each data bit period and LOW for the second half.
  • serial data signal as constituted by any arbitrary sequence of binary ones and zeros.
  • the • transmitter comprises two main sections: a ONES section 2,4 and 6, and a ZEROS section 3,5 and 7.
  • the two sections are very similar.
  • the HIGH level pulse of width T/2 occurs at the
  • the ZEROS section of the transmitter operates in similar fashion when the input data is LOW. Input data passes through inverter 1 to gate 3 where it is combined with the clock signal to form a HIGH level pulse of width T/2 for each ZERO bit in the data. These are called ZEROS
  • the receiver 51 shown in Figure 4 comprises three main sections: a ONES section 10, 11, 12 and 13, a ZEROS section 16, 17, 18 and 19, very similar to the ONES section, and an output section 14, 15 and 20 through 25 in which 0 signals recovered in the two preceding sections are processed in various ways to produce the required outputs.
  • Input signals to the receiver are RECEIVED ONES (a ternary signal coupled from the ONES line by transformer winding 8b), and RECEIVED ZEROS (likewise a ternary signal 5 but coupled from the ZEROS line by transformer winding 9b).
  • Primary output signals from the receiver are. RECEIVED CLOCK, RECEIVED DATA, and COLLISION.
  • Secondary outputs from the receiver (used by the transmitter) are RECEIVED POSITIVE ONE, RECEIVED NEGATIVE ONE, RECEIVED POSITIVE ZERO, and RECEIVED NEGATIVE ZERO.
  • ONES received ONES which may have suffered attenuation and dispersion during transmission over the bus, are first amplified in a limiting differential amplifier 10.
  • the output signal from amplifier 10 is still in basically a ternary form, i.e. alternating positive and negative polarity pulses around a reference level.
  • Output pulses from the amplifier pass to comparator 11 which has balanced threshholds for detecting both positive and negative pulses.
  • the output from comparator 11 changes from LOW to HIGH only when the output of amplifier 10 goes more . positive than the positive threshhold, and likewise changes from HIGH to LOW when the output of amplifier 10 goes more negative than the negative threshhold.
  • the output from comparator 11 drives signal edge-detection circuitry 12 which produces a short positive pulse on each transition of its input waveform (both HIGH to LOW and LOW to HIGH transitions). These pulses trigger monostable multivibrator 13 whose monostable period typically is set to a value between 0.3T and 0.5T, where T is the period of one bit time.
  • T is the period of one bit time.
  • the out- put of 13 is combined with the output of comparator 11 in gates 14 and 15 to form the secondary output signals RECEIVED POSITIVE ONE and RECEIVED NEGATIVE ONE which are ' used by the encoder.
  • ZEROS are similarly amplified by ampifier 16 and compared with fixed threshholds in comparator 17.
  • the transition of comparator 17 output signal are extracted by edge detection circuit 18 and used to trigger monostable multivibrator 19 which is set to the same period as multivibrator 13.
  • the signal RECEIVED ZEROS at the output of multivibrator 19 is passed to the output section and is also combined with the output of comparator 17 in gates 20 and 21 to form the secondary output signals
  • RECEIVED ONES and RECEIVED ZEROS are logically OR'ed together to recover the RECEIVED CLOCK signal.
  • Cross-coupled gates 23 and 24 form a set-reset flip- flop.
  • RECEIVED ONES is the set input
  • RECEIVED ZEROS the reset input
  • RECEIVED DATA is the output.
  • RECEIVED ONES and RECEIVED ZEROS can be HIGH at any instant of time. If both signals are HIGH this condition is detected by gate 25 and signalled as COLLISION.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Small-Scale Networks (AREA)

Abstract

Système de communication de données à réseau local du type permettant une communication entre au moins une paire d'ordinateurs interfacés avec des points nodaux de communication associés (52), ces points nodaux comprenant un émetteur/récepteur (50, 51) et étant généralement reliés à une paire de lignes de communication (53, 54) qui s'étendent au travers du réseau local et véhiculent les signaux transmis, chaque point nodal étant conçu pour transmettre ou recevoir les données au travers desdites lignes.
EP19840901719 1983-04-29 1984-04-30 Systeme de communications numeriques Withdrawn EP0148191A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AU9118/83 1983-04-29
AU911883 1983-04-29

Publications (1)

Publication Number Publication Date
EP0148191A1 true EP0148191A1 (fr) 1985-07-17

Family

ID=3699833

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19840901719 Withdrawn EP0148191A1 (fr) 1983-04-29 1984-04-30 Systeme de communications numeriques

Country Status (2)

Country Link
EP (1) EP0148191A1 (fr)
WO (1) WO1984004437A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19702536A1 (de) * 1997-01-24 1998-07-30 Siemens Ag Langgestrecktes Element mit mindestens einem elektrischen und/oder optischen Leiter
AU2001296074A1 (en) * 2000-11-06 2002-05-15 Josuya Technology Corp. Data communication system for compensating the attenuation of transmission signal

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1168476A (en) * 1966-05-17 1969-10-29 British Telecomm Res Ltd Improvements in or relating to data transmission systems
US3886524A (en) * 1973-10-18 1975-05-27 Texas Instruments Inc Asynchronous communication bus
US4063220A (en) * 1975-03-31 1977-12-13 Xerox Corporation Multipoint data communication system with collision detection
US4099024A (en) * 1977-02-16 1978-07-04 Xerox Corporation Communications network repeater
US4149238A (en) * 1977-08-30 1979-04-10 Control Data Corporation Computer interface
US4320502A (en) * 1978-02-22 1982-03-16 International Business Machines Corp. Distributed priority resolution system
US4282512A (en) * 1980-02-04 1981-08-04 Xerox Corporation Data communication system
US4377852A (en) * 1980-03-31 1983-03-22 Texas Instruments Incorporated Terminal emulator
US4619425A (en) * 1981-07-17 1986-10-28 American Standard Inc. Pulse code system for railroad track circuits
DE3142683A1 (de) * 1981-10-28 1983-05-11 Hubert I. 4423 Gescher Eing Steuerverfahren fuer lokale datennetze mit bus-struktur
AU552312B2 (en) * 1982-02-08 1986-05-29 Racal-Milgo Limited Communication system
JPS58146145A (ja) * 1982-02-25 1983-08-31 Toshiba Corp マイクロコンピユ−タネツトワ−ク方式
US4481626A (en) * 1982-05-05 1984-11-06 Xerox Corporation Transceiver multiplexor

Non-Patent Citations (1)

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Title
See references of WO8404437A1 *

Also Published As

Publication number Publication date
WO1984004437A1 (fr) 1984-11-08

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Effective date: 19850305

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Inventor name: TRELOAR, BARRY

Inventor name: CLARKE, NEIL

Inventor name: BELLAMY, CLIFFORD

Inventor name: MILLER, PATRICK

Inventor name: HEALE, KEITH

Inventor name: GORDON, PETER