Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Definitions

• This invention relates generally to a buffer circuit suitable for implementation in an integrated circuit, and / in particular, to a buffer circuit which provides a current limiting protection to the output transistors.
• output buffer circuits between signals internal to the integrated circuit and signals off-chip. Since it is generally undesirable to have large .current signals within the integrated circuit, as large currents can inhibit the ability of the chip to dissipate heat as well as the operational speed of the circuits internal to the chip, a significant function performed by output buffer circuits is to translate the relatively low current on-chip signals into relatively large current off-chip signals.
• FIG. 1 there is shown a prior art short-protected output buffer.
• the circuit comprises a constant current source in the form of depletion mode transistor T7, whose drain is connected to a supply voltage, whose source is connected to its gate, to the drain of inverter transistor T8. and to the gate of source current output transistor Tl.
• the input at lead 5 is connected to the gate of inverter T8 and to the gate of sink current output transistor T2. The output is taken off
• OMFI lead 10 A large on-chip diffused resistor R is connected between the drain of transistor Tl and the supply voltage.
• An input signal at a given logic level (binary 1 or 0) is inverted by transistors T8 and T2. For example, if the input is 1, then T8 and T2 will be conductive. The gate voltage on Tl will be low, rendering it non-conductive, and output lead 10 will be shunted to ground through T2. If the input is 0, then T8 and T2 will be non-conductive. The gate voltage on Tl will be high, so that Tl will be conductive, and thus output lead 10 will be high.
• enhancement mode transistors such as T1,T2, and T8
• the transistor is rendered conductive when the gate-to-source voltage is equal to or exceeds the threshold voltage ⁇ jj E .
• the gate-to-source voltage is just equal to V-pg
• the transistor is soft conducting, i.e. just beginning to conduct.
• the drain-to-source current increases until eventually a limit is reached beyond which the transistor is damaged due to current flow beyond its limits.
• V TE of Tl is 1.0 volts
• the input is a logical 0.
• the output voltage on lead 10 is 5.0 volts
• transistor T7 is supplying a full 5.0 volts on lead 7 to- the gate of Tl.
• the gate-to-source voltage across Tl is 0.0 volts
• Tl is non-conductive. If the output voltage on lead 10 is 4.0 volts, then the gate-to-source voltage across Tl is 1.0 volts, and Tl just begins to turn on.
• the source current output -transistor Tl is protected against excessive drain-to-source current by resistor R.
• resistor R limits the drain-to-source current of Tl, so that the output current is also limited.
• very large output transistors Tl and T2 and a very large resistor R must be provided. But these large devices result in a large, expensive integrated circuit. Also the resultant integrated circuit has high power consumption.
• FIG. 2 shows another prior art short-protected buffer circuit.
• the circuit shown in FIG. 2 is identical to that shown in FIG. 1, except that bypass transistors T3 and T4 are series-connected between the gate of transistor Tl and the output lead 10.
• T3 and T4 are connected as diodes, with their gates connected to- their respective drains.
• the drain-to-source voltage drop across both T3 and T4 i.e. between the gate of Tl and output lead 10
• T3 and T4 are both turned on. That is, the forward voltage is equal to the sum of their threshold voltages, so each diode turns on.
• the gate-to-source voltage on Tl cannot exceed a voltage which is equal to the 5.0 volt supply voltage less two times V-jg.
• a limit is imposed on the gate-to-source voltage on Tl, and as a consequence a limit is imposed on the maximum output current.
• a major disadvantage of the prior art circuit shown in FIG. 2 is that the protective action begins while the output voltage is still at too high a value. As mentioned above, certain applications require a relatively high output current at a relatively low output voltage, while still maintaining a limit on the output current. To achieve this result using the circuit shown in FIG. 2, output transistor Tl would have to be greatly enlarged, and the resulting integrated circuit would also be greatly enlarged and therefore more expensive.
• the present invention overcomes the disadvantages associated with the above-described prior art output buffer circuits.
• a short-protected buffer circuit having an input and an output, the circuit comprising a voltage source, the voltage source being at a certain potential relative to ground; a source current output transistor having a drain coupled to the voltage source, a source coupled to the output, and a gate; a sink current output transistor having a drain coupled to the output, a source coupled to ground, and a gate; and a protection circuit for protecting the output transistors from excessive current, the protection circuit comprising a voltage reference; a third transistor having a drain coupled to the gate of the source current output transistor, a source, and a gate coupled to its drain; and a fourth transistor having a drain coupled to the source of the third transistor, a source coupled to the output, and a gate coupled to the voltage reference.
• FIG. 1 shows a prior art short-protected buffer circuit.
• FIG. 2 shows another prior art short-protected buffer circuit.
• FIG. 3 shows a circuit diagram of a preferred embodiment of the short-protected buffer circuit of the present invention.
• FIG. 4 shows an equivalent circuit to that shown in FIG. 3 for ease in understanding the operation of the FIG. 3 circuit.
• FIG. 5 shows a graph of output current versus output voltage regarding the preferred embodiment.
• FIG. 6 shows a graph of the gate voltage on transistor Tl of the preferred embodiment versus the output voltage.
• FIG. 3 shows a circuit diagram of a preferred embodiment of the short-protected buffer circuit of the present invention.
• transistor T4 is not connected as a diode, as in FIG. 2, but rather is operated as a transistor to whose gate is applied a reference voltage.
• the reference voltage is provided by transistor pair T5 and T6.
• T5 is a depletion mode transistor whose drain is connected to a voltage source, which in the preferred embodiment is 5.0 volts.
• the source and gate of T5 are connected together and to the gate of T4.
• Transistor T6 is an enhancement mode transistor whose drain is connected to its gate and to the source of T5, and whose source is coupled to ground.
• FIG. 4 shows an equivalent circuit to that shown in FIG. 3 for ease in understanding the operation of the FIG. 3 circuit.
• T3 is operating as a diode, whose equivalent diode D is shown in FIG. 4.
• T5 and T6 are operating as a voltage source, represented by voltage source 12 in FIG. 4.
• diode D has a forward voltage V-j-g, which is defined as the voltage required to just start conduction in the forward direction (i.e. from the gate of Tl to the drain of T4) through D.
• Voltage source 12 is regulated to V TE , where V TE is defined as the threshold voltage of an enhancement mode transistor, such as T4.
• Tl will not be conductive unless its gate-to-source voltage is equal or greater than V T .
• T4 r transistor Tl will just start to conduct when its gate-to- source voltage is approximately 1.0 volts, and it will be fully conductive when the gate-to-source voltage reaches 1.4 volts.
• variable voltage source 14 Before we begin changing the variable voltage source 14 to explore the operation of the protection circuit, let us look at FIGS. 5 and 6, which will also aid in under ⁇ standing the operation of the preferred embodiment.
• FIG. 5 shows a graph of output current versus output voltage, the output current being plotted on the Y-axis and the output voltage being plotted along the X-axis.
• the solid line 20 represents the plot for the present invention, while the dashed line 30 represents that for the FIG. 2 prior art circuit. From FIG. 5 it will easily be seen that in the present invention the output current is significantly higher, at low output voltages than for the FIG. 2 prior art circuit.
• FIG. 6 shows a graph of how the gate voltage on transistor Tl of the preferred embodiment varies with the output voltage.
• the output voltage is plotted along the X-axis.
• the gate voltage on Tl is plotted on the Y-axis.
• the solid line 40 represents the curve for the present invention
• the dashed line 50 represents that for the FIG. 2 prior art circuit.
• the output current limiting action in the present invention doesn't begin to occur until the output voltage drops to approximately 0.4 volts, as shown at point 41 on curve 40, whereas the limiting action in the FIG. 2 prior art circuit begins at approxi ⁇ mately 2.6 volts, as shown by point 51 on curve 50.
• T4 is 1.4 volts
• the gate-to-source voltage on T4 is 1.4 volts minus 5.0 volts, or -3.6 volts, so T4 is definitely non-conducting, since, as mentioned above, T4 conduction begins when its gate-to-sour ⁇ e voltage is approximately +1.0 volts.
• the gate voltage on Tl is 5.0 volts
• the gate-to-source voltage on Tl is 0.0 volts, so Tl is non-conducting. This is confirmed in FIG. 5, which indicates no output current when the output voltage is 5.0 volts. If voltage VS is now reduced to 4.0 volts, T4 is still non-conductive. However, Tl just begins to turn on, since its gate-to-source voltage is approximately 1.0 volts.
• the gate-to-source voltage across T4 is 1.4 minus 0.4, or approximately 1.0 volts, so T4 is just starting to turn on.
• the forward voltage across diode D is greater than its threshold voltage, so it too becomes conductive.
• the potential on the gate of Tl is decreased.
• 0.4 volts is the value of the output voltage where the current limiting protection starts.
• T4 turns on harder and harder, and the gate-to-source voltage on Tl is reduced still further, thus causing the output current to decrease, as shown by curve 20 in FIG. 5.
• the gate-to-source voltage on T4 is equal to the reference voltage on the gate of T4, or 1.4 volts.
• the potential on the drain of T4 is 1.4 volts, and the potential on the anode of D is also 1.4 volts. So the maximum potential on the gate of Tl is twice V TE , or 2.8 volts, as shown in FIG 6.
• the fact that the maximum potential on the gate of Tl is limited to twice V TE limits the output source current.
• the output voltage at which the current limiting protection starts can be changed. This may be done by changing the voltage reference supplied to the gate of T4 by T5/T6 by changing the size (i.e. the gate length and width) of T5.
• the protection starting voltage is changed. For example, if the output current level of the circuit is found to be too high at 0.4 output volts, then the reference voltage can simply be changed from 1.4 volts to 1.5 volts, thereby increasing the protection starting voltage from 0.4 output volts to 0.5 output volts.
• the protection starting voltage is determined by the difference between the reference voltage (approximately 1.4 volts) and the T4 threshold voltage (approximately 1.0 volt). Even if the threshold voltages are shifted, as a result of process variations, the reference voltage supplied by T5/T6 will shift in the same direction, so that the difference will remain constant. Thus the protection starting voltage will remain constant despite minor process variations which result in different thresholds on different wafers.
• the operating characteristics are not affected by variations in temperature, since such variations affect the reference voltage supplied by T5/T6 and the T4 threshold to the same extent, so that the difference again remains constant.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Computing Systems (AREA)
• General Engineering & Computer Science (AREA)
• Mathematical Physics (AREA)
• Theoretical Computer Science (AREA)
• Logic Circuits (AREA)
• Amplifiers (AREA)
• Control Of Electrical Variables (AREA)
• Protection Of Static Devices (AREA)

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• 1983
  • 1983-12-12 JP JP84500457A patent/JPS60500437A/ja active Pending
  • 1983-12-12 WO PCT/US1983/001966 patent/WO1984003181A1/en not_active Application Discontinuation
  • 1983-12-12 EP EP19840900356 patent/EP0141819A4/de not_active Withdrawn
  • 1983-12-16 CA CA000443506A patent/CA1191560A/en not_active Expired
• 1984
  • 1984-01-12 IT IT47534/84A patent/IT1178355B/it active
  • 1984-02-04 KR KR1019840000525A patent/KR900001812B1/ko not_active IP Right Cessation

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