EP0135559A1 - Integrated self-firing thyristor structure for on/off switching of high currents, and control circuit thereof - Google Patents

Integrated self-firing thyristor structure for on/off switching of high currents, and control circuit thereof

Info

Publication number
EP0135559A1
EP0135559A1 EP84900993A EP84900993A EP0135559A1 EP 0135559 A1 EP0135559 A1 EP 0135559A1 EP 84900993 A EP84900993 A EP 84900993A EP 84900993 A EP84900993 A EP 84900993A EP 0135559 A1 EP0135559 A1 EP 0135559A1
Authority
EP
European Patent Office
Prior art keywords
thyristor
main
trigger
auxiliary
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP84900993A
Other languages
German (de)
French (fr)
Inventor
Jacques Emile Thire
Georges Souques
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telemecanique SA
Original Assignee
La Telemecanique Electrique SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by La Telemecanique Electrique SA filed Critical La Telemecanique Electrique SA
Publication of EP0135559A1 publication Critical patent/EP0135559A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/725—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for ac voltages or currents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7428—Thyristor-type devices, e.g. having four-zone regenerative action having an amplifying gate structure, e.g. cascade (Darlington) configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/79—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar semiconductor switches with more than two PN-junctions, or more than three electrodes, or more than one electrode connected to the same conductivity region

Definitions

  • the invention relates to self-ignition "thyristor" type structures.
  • These intrinsically self-igniting structures comprise successive semiconductor layers forming a first emitter region (preferably of type N), a first base region, or inhibition base (preferably of type P), a second base region (main base, preferably type N) and a second emitter region (preferably type P), the first emitter region being provided with at least one cathode contact, the first base region being connected to at least one inhibit trigger contact, the second emitter region being provided with an ano ⁇ contact, and at least one switch means arranged to create a first emitter region (preferably of type N), a first base region, or inhibition base (preferably of type P), a second base region (main base, preferably type N) and a second emitter region (preferably type P), the first emitter region being provided with at least one cathode contact, the first base region being connected to at least one inhibit trigger contact, the second emitter region being provided with an ano ⁇ contact, and at least one switch means arranged to create a first emitter region (preferably of type N), a first base region, or inhibition base (preferably
  • WIPO A WIPO short circuit between the inhibit trigger and the cathode and thus inhibit the self-ignition faculty of the thyristor, and are characterized in that said base and emitter regions are produced so as to constitute xi very large thyristor sensitivity.
  • the thicknesses and dopings of the first emitter and base regions are chosen so that the intrinsic gain of the first NPN transistor is high at a low level and the passivation of the junctions is particularly careful, in accordance with the indications given in the patent 82 19728.
  • the present invention proposes to solve this problem by means of an amplifier trigger structure comprising an assisted thyristor, small in size and very large.
  • the high sensitivity is however not sufficient to obtain "intrinsic" self-ignition, that is to say without assistance assistance.
  • the main object of the invention is to produce such an amplifier-type structure of the integrated type, which has particular advantages. It will be noted that such a structure, in spite of its analogies with the structures of known amplifying trigger thyristors, is radically distinguished therefrom by its operation, which follows from its particularities and from its control mode.
  • the main thyristor of said amplifying trigger structure is of the "mesa” type, while the pilot thyristor is constituted by a small central portion of the “mesa” structure, and delimited according to the "planar” technique, with no edge effect, the main base of the pilot thyristor " being isolated from that of the main thyristor, unlike the known structure of a thyristor with an amplifying trigger, the structure with an amplifying trigger of the invention being further characterized, with respect to said known structure, in that its control is carried out by trigger-cathode short-circuit of the pilot and main thyris ⁇ tors, that the main thyristor has its own trigger and a high sensitivity and that the resistance between the inhibition base of the pilot thyristor and that of the main thyristor is very high (more than one egohm).
  • the pilot and main thyris ⁇ tors are arranged so that the apparent shunt resistance relative to the corresponding emitter-base junction is very low, for example, for a cris-
  • This characteristic advantageously obtained by conforming the emitter and / or trigger region of the main thyristor to obtain a high surface area ratio, ensures an efficient flow of the displacement current in blocked mode and, consequently, provides excellent resistance to blocking, even in the event of high parasitic dV / dt.
  • an impedance of self-ignition assistance preferably a resistance of a few megohms, or even a capacitor of the order of 10 nF, connects the common anode. of the two thyristors in contact with the pilot trigger and the ignition is obtained by eliminating a short circuit normally established between the trigger and the cathode of the pilot thyristor.
  • Such a structure in which the area for injecting the assistance current into the pilot thyristor (surface of its emitter) is reduced, has the advantage that the pilot thyristor, which has a significant gain even at very low level, s for the very small control current provided by the assistance resistor, while, thanks to the large surface of the main thyristor, the structure can conduct a high current and, consequently, command a large power.
  • this structure differs radically from the conventional amplifier thyristor structure, in which, in particular, the pilot thyristor is primed by applying a control voltage to its trigger. It has significant advantages over it, and in particular
  • the structure will have to withstand reverse voltages of approximately 750 V. It will be noted that the trigger-cathode short-circuit transforms the voltage withstand BV CE0 into a 0 with in V CES voltage, which facilitates obtaining the desired result.
  • the thyristor structure comprising the abovementioned particularities will, however, be incapable of operating on a 380 Veff network.
  • the passage of a supply voltage from 220 Veff to 380 Veff would in fact lead, in particular, to multiplying the life of minority carriers in the base N by a factor of 3.6, which would require obtaining a duration life of more than 90 microseconds instead of 26 0 microseconds; such a characteristic is currently impracticable.
  • O PI realizes its transmitter in the form of a double layer structure N + N—.
  • Figure 1 is a block diagram of an integrated structure of assisted self-ignition thyristor in accordance with the invention.
  • FIG. 2 illustrates a first embodiment of this structure, of which
  • Figure 3 illustrates a variant
  • a thyristor structure comprising an inhibition base 1 of type P, a main base 2 of type N and a second emitter region 3 of type P, which are common to the two thyristors that is the structure.
  • first N-type emitter regions were formed designated by 4 for the main thyristor, by 5 for the pilot or auxiliary thyristor.
  • the region 5 is located in the center of the silicon wafer and has for example 1 mm in diameter, for a wafer of 1 cm for example. These values are not limiting, and the actual values will depend on the desired power.
  • An anode contact is shown in 6, in Kp of the cathode contacts of the main thyristor, connected to the cathode terminal K of the assembly, in Gp of the gate contacts of the main thyristor, in Ga of the gate contacts of the auxiliary thyristor, connected to the anode terminal A of the assembly through an assistance resistance of a few megohms or, in the illustrated example, by a Cass capacitor of the order of 10 nF, in Ka le cathode contact of the auxiliary thyristor, connected to the contacts Gp, and to the terminal K by means of a switch I ,.
  • the point common to Cass and Ga is connected to terminal K via a switch I- and switch I, in series.
  • the concentrations of impurity atoms per cm are:
  • a groove 7 cutting the entire thickness of the layer 1 and completely surrounding the emitter 5 is produced according to the technique, known per se, called "planar-furrow", which consists of a deep pickling of the entire layer 1, followed by 'additional stripping of the entire surface to eliminate the sharp angle created by deep stripping, and finally, thermal oxidation for "planar” passivation.
  • Complementary stripping must be carried out by a technique ensuring a very good surface condition (absence of crystalline micro ⁇ defects and very low trap density), for example by reactive ion etching. This quality of
  • O P1 surface preparation of the groove is indeed necessary if we want to find the characteristics of very low density of recombination centers on the surface which made adopt the "planar" technique to obtain very high sensitivities.
  • This planar-groove technique makes it possible to maintain low rates of surface recombination and, consequently, a high sensitivity of the pilot thyristor. It avoids a short circuit through the emitter junction of the pilot thyristor, which would hinder its ignition.
  • the trigger 8 and the transmitter 7 preferably have a highly interdigitated structure (or any other equivalent structure), so that, as explained above, the apparent shunt resistance with respect to the emitter-base junction of the main thyristor is, for a crystal of 1 cm, a few hundredths of Ohms for example, thanks to a layer resistance of layer P which will be for example of the order of 10 ohms per square (which is generally noted 10 ⁇ / CB).
  • a layer resistance of layer P which will be for example of the order of 10 ohms per square (which is generally noted 10 ⁇ / CB).
  • Such a structure will generally not be essential for the junction of the auxiliary thyristor emitter, due to its very small size.
  • the main structure is of the "mesa" type (that is to say isolated by running-in and chemical attack at the periphery of the wafer, followed by a passivation).
  • a supply voltage of 220 Veff for example is applied to the anode terminal A, terminal K being at zero voltage (when I-_ and I 2 are open), the same is true of region 5, and the low current injected into the trigger Ga through the capacitor Cass is sufficient to cause the ignition of the auxiliary thyristor shortly after the first zero crossing of the supply voltage, according to the operating principle of auto - assisted ignition described in the request for aforementioned patent.
  • the emitter junction of the auxiliary thyristor is protected from short circuit by the resistance which exists between the corresponding base inhibition portions of the two thyristors.
  • the common base P being at a potential close to that of the anode, and the short circuit between the trigger Gp and the emitter 4 being eliminated since I, is still open, the main current of the thyristor auxiliary goes into the first transmitter junction of the main thyristor, and it starts quickly.
  • the ignition spreads very quickly over the entire surface of the transmitter contact. This ignition surface can occupy approximately 80% of the total surface of the wafer.
  • the amplifier trigger structure according to this first embodiment of the invention is capable of switching currents ranging for example from several tens to several hundreds of amps.
  • the gain of the PNP transistor of such a structure is relatively low, since its base N must have a relatively large thickness to ensure the voltage withstand.
  • the structure will no longer be able to self-ignite for supply voltages of 380 Veff for example, unless we succeed in giving the NPN transistor a very high gain. raised to very low level.
  • the structure is produced with double-layer emitters, advantageously according to the following method, given without limitation:
  • a thin N-type epitaxy (a few microns) is carried out over the entire surface of the chip with a
  • the contacts are then made in a conventional manner.
  • peripheral isolation of the two PN junctions is made in a conventional manner and various known devices are used
  • operation (b) may also include a diffusion P on the front face, and step (c) will then be deleted.
  • FIG. 3 a third embodiment of the structure is illustrated, consisting in producing ultra-thin emitters doped from deposited polycrystalline silicon. More difficult to implement than the method in accordance with the second embodiment described above, this method presents, in return, the following advantages:

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)

Abstract

Structure de thyristor à gâchette amplificatrice dont la commande est réalisée par court-circuits (interrupteurs I1 et I2) entre la gâchette et la cathode des thyristors auxiliaire et principal respectivement, ce dernier étant à grande sensibilité. Un condensateur (Cass) d'assistance à l'allumage relie l'anode commune (A) au contact de gâchette (Ga) du thyristor auxiliaire. Le contact de gâchette (Gp) du thyristor principal est placé à l'extérieur de l'émetteur (4), et un sillon d'isolement (7), coupant toute l'épaisseur de la base (P) et réalisé suivant la technologie "planar-sillon", est pratiqué autour de l'émetteur (5), pour éviter un court-circuit à travers la jonction d'émetteur du thyristor auxiliaire, qui gênerait son auto-amorçage. Application à la commutation de courants forts (100 à 1000A).Thyristor structure with amplifying gate, the control of which is carried out by short circuits (switches I1 and I2) between the gate and the cathode of the auxiliary and main thyristors respectively, the latter being highly sensitive. An ignition assistance capacitor (Cass) connects the common anode (A) to the trigger contact (Ga) of the auxiliary thyristor. The gate contact (Gp) of the main thyristor is placed outside the emitter (4), and an insulation groove (7), cutting the entire thickness of the base (P) and made according to the technology "planar-groove", is practiced around the emitter (5), to avoid a short circuit across the emitter junction of the auxiliary thyristor, which would hinder its self-priming. Application to switching high currents (100 to 1000A).

Description

STRUCTURE INTEGREE DE THYRISTOR A AUTO-ALLUMAGE POUR COMMUTATION PAR TOUT OU RIEN DE COURANTS FORTS, ET SON CIRCUIT DE COMMANDE. INTEGRATED SELF-IGNITION THYRISTOR STRUCTURE FOR SWITCHING BY ANY OR NOTHING OF STRONG CURRENTS, AND ITS CONTROL CIRCUIT.
L'invention se rapporte aux structures du genre "thyristor" à auto-allumage.The invention relates to self-ignition "thyristor" type structures.
Dans la demande de brevet déposée le 25 Novembre 1982, sous le No 82 19728, pour : "Structure de thyristor à allumage intrinsèque et son application à la réalisation d'un dispo¬ sitif bidirectionnel", on a décrit des structures de thyris¬ tor à auto-allumage intrinsèque, c'est-à-dire s'amorçant au zéro de tension sous le seul effet du courant de déplacement interne CdV/dt, cet auto-allumage étant inhibé à l'aide d'un court-circuit gâchette-cathode, et on en a exposé les avan¬ tages.In the patent application filed on November 25, 1982, under No. 82 19728, for: "Intrinsic ignition thyristor structure and its application to the production of a bidirectional device", thyris¬ tor structures have been described with intrinsic self-ignition, i.e. starting at zero voltage under the sole effect of the internal displacement current CdV / dt, this self-ignition being inhibited by means of a trigger short-circuit -cathode, and we have exposed the advantages.
Ces structures à auto-allumage intrinsèque comportent des couches semi-conductrices successives formant une première région d'émetteur (de préférence de type N) , une première région de base, ou base d'inhibition (de préférence de type P) , une seconde région de base (base principale, de préfé¬ rence de type N) et une seconde région d'émetteur (de préfé- rence de type P) , la première région d'émetteur étant munie d'au moins un contact de cathode, la première région de base étant reliée à au moins un contact de gâchette d'inhibition, la seconde région d'émetteur étant munie d'un contact d'ano¬ de, et au moins un moyen interrupteur agencé pour créer unThese intrinsically self-igniting structures comprise successive semiconductor layers forming a first emitter region (preferably of type N), a first base region, or inhibition base (preferably of type P), a second base region (main base, preferably type N) and a second emitter region (preferably type P), the first emitter region being provided with at least one cathode contact, the first base region being connected to at least one inhibit trigger contact, the second emitter region being provided with an ano¬ contact, and at least one switch means arranged to create a
OMPI A, WIPO court-circuit entre la gâchette d'inhibition et la cathode et inhiber ainsi la faculté d'auto-allumage du thyristor, et sont caractérisées en ce que lesdites régions de bases et d'émetteurs sont réalisées de manière à constituer xi thyristor de très grande sensibilité.WIPO A, WIPO short circuit between the inhibit trigger and the cathode and thus inhibit the self-ignition faculty of the thyristor, and are characterized in that said base and emitter regions are produced so as to constitute xi very large thyristor sensitivity.
A cet effet, les épaisseurs et les dopages des premières régions d'émetteur et de base sont choisis de façon que le gain intrinsèque du premier transistor NPN soit élevé à bas niveau et la passivation des jonctions est particulièrement soignée, conformément aux indications données dans le brevet 82 19728.To this end, the thicknesses and dopings of the first emitter and base regions are chosen so that the intrinsic gain of the first NPN transistor is high at a low level and the passivation of the junctions is particularly careful, in accordance with the indications given in the patent 82 19728.
Comme il s'est avéré très difficile de réaliser industriel- lement des structures à auto-allumage "intrinsèque", on a prévu ensuite d*initialiser l'auto-allumage à l'aide d'une faible admittance (résistance d'assistance de quelques mégoh s, ou condensateur de l'ordre de la dizaine de nF) .As it has proved very difficult to produce structures with "intrinsic" self-ignition on an industrial scale, provision has then been made to initialize the self-ignition by means of a low admittance (resistance of assistance of a few megohs, or capacitor of the order of ten nF).
Lorsque ces structures à auto-allumage sont assistées par un condensateur, le temps d'allumage est fortement réduit par rapport à l'assitance par résistance, si bien que leur commande par transistor MOS, qui a été envisagée et se révèle très pratique dans les applications aux relais stati- ques, devient difficile à cause de la constante de temps de charge de la grille du MOS. Par contre, lorsque lesdites structures sont assistées par une résistance, le courant d'assistance ne dépasse pas quelques micro-ampères et est très localisé, ce qui limite les possibilités de commutation de courants élevés.When these self-ignition structures are assisted by a capacitor, the ignition time is greatly reduced compared to the resistance assistance, so that their control by MOS transistor, which has been envisaged and proves to be very practical in applications to solid state relays, becomes difficult because of the charging time constant of the MOS grid. On the other hand, when said structures are assisted by a resistance, the assistance current does not exceed a few micro-amps and is very localized, which limits the possibilities of switching high currents.
Si on augmente l'aire de gâchette, la densité du courant d'assistance devient faible et l'assistance inefficace.If the trigger area is increased, the density of the assistance current becomes low and the assistance ineffective.
La présente invention se propose de résoudre ce problème au moyen d'une structure à gâchette amplificatrice comportant un thyristor assisté, de petite taille et de très grandeThe present invention proposes to solve this problem by means of an amplifier trigger structure comprising an assisted thyristor, small in size and very large.
v . IPO sensibilité, qui devient alors le pilote d'un transistor principal ayant lui-même une très grande sensibilité.v. IPO sensitivity, which then becomes the driver of a main transistor which itself has a very high sensitivity.
Dans cette structure à gâchette amplificatrice, la grands sensibilité n'est toutefois pas suffisante pour obtenir l'auto-allumage "intrinsèque", c'est-à-dire sans ad ittance d'assistance.In this amplifying trigger structure, the high sensitivity is however not sufficient to obtain "intrinsic" self-ignition, that is to say without assistance assistance.
L'objet principal de l'invention est de réaliser une telle structure à gâchette amplificatrice du type intégré, qui présente des avantages particuliers. On notera qu'une telle structure, malgré ses analogies avec les structures de thyristors à gâchette amplificatrice connues, s'en distin¬ gue radicalement par son fonctionnement, qui découle de ses particularités et de son mode de commande.The main object of the invention is to produce such an amplifier-type structure of the integrated type, which has particular advantages. It will be noted that such a structure, in spite of its analogies with the structures of known amplifying trigger thyristors, is radically distinguished therefrom by its operation, which follows from its particularities and from its control mode.
Suivant une première particularité de l'invention, le thyristor principal de ladite structure à gâchette amplifi¬ catrice est du type "mesa", tandis que le thyristor pilote est constitué par une portion centrale de petite dimension de la structure "mesa", et délimité suivant la technique "planar", avec absence d'effet de bord, la base principale du thyristor pilote "étant isolée de celle du thyristor principal, contrairement à la structure connue d'un thyris- tor à gâchette amplificatrice, la structure à gâchette amplificatrice de l'invention étant en outre caractérisée, par rapport à ladite structure connue, en ce que sa commande est réalisée par court-circuit gâchette-cathode des thyris¬ tors pilote et principal, que le thyristor principal a une gâchette propre et une grande sensibilité et que la résis¬ tance entre la base d'inhibition du thyristor pilote et celle du thyristor principal est très élevée (plus d'un égohm) .According to a first feature of the invention, the main thyristor of said amplifying trigger structure is of the "mesa" type, while the pilot thyristor is constituted by a small central portion of the "mesa" structure, and delimited according to the "planar" technique, with no edge effect, the main base of the pilot thyristor " being isolated from that of the main thyristor, unlike the known structure of a thyristor with an amplifying trigger, the structure with an amplifying trigger of the invention being further characterized, with respect to said known structure, in that its control is carried out by trigger-cathode short-circuit of the pilot and main thyris¬ tors, that the main thyristor has its own trigger and a high sensitivity and that the resistance between the inhibition base of the pilot thyristor and that of the main thyristor is very high (more than one egohm).
Cette dernière caractéristique, avantageusement obtenue en réalisant un sillon d'isolement coupant toute l'épaisseur de la diffusion de base P, sillon lui-même passive par oxyda¬ tion thermique suivant la technique dite "planar-sillon" quiThis last characteristic, advantageously obtained by producing an isolation groove cutting the entire thickness of the base diffusion P, itself groove passive by thermal oxidation according to the so-called "planar-groove" technique which
OMPI permet de maintenir de faibles taux de reco biπaison en surface et, par suite, une grande sensibilité du thyristor pilote, évite un court-circuit à travers la jonction d'émet¬ teur du thyristor pilote qui gênerait son auto-amorçage.WIPO allows to maintain low biπaison reco rates on the surface and, consequently, a high sensitivity of the pilot thyristor, avoids a short circuit through the junction of emitter of the pilot thyristor which would interfere with its self-priming.
Suivant une autre particularité de l'invention, les thyris¬ tors pilote et principal sont agencés pour que la résistance apparente de shunt par rapport à la jonction émetteur-base correspondante soit très faible, par exemple, pour un cris-According to another feature of the invention, the pilot and main thyris¬ tors are arranged so that the apparent shunt resistance relative to the corresponding emitter-base junction is very low, for example, for a cris-
• tal de 1 cm , une résistance de quelques centièmes à quel¬ ques dixièmes d'Ohms au plus, grâce à une faible résistance de couche de la couche P (par exemple de l1ordre de 10 Ω /a et une forte interdigitation avec des bandes d'émetteur étroites.• tal of 1 cm, a resistance of a few hundredths to tenths of Ohms quel¬ c at most, with a low sheet resistance of the P layer (e.g. of 1 order of 10 Ω / a and a strong interdigitation with narrow transmitter bands.
Cette caractéristique, avantageusement obtenue en confor¬ mant la région d'émetteur et/ou de gâchette du thyristor principal pour obtenir un rapport périmètre à surface élevé, assure un écoulement efficace du courant de déplacement en régime bloqué et, par suite, apporte une excellente tenue du blocage, même en cas de dV/dt parasites élevés.This characteristic, advantageously obtained by conforming the emitter and / or trigger region of the main thyristor to obtain a high surface area ratio, ensures an efficient flow of the displacement current in blocked mode and, consequently, provides excellent resistance to blocking, even in the event of high parasitic dV / dt.
Suivant une autre particularité de l'invention, une impédan¬ ce d'assistance à l'auto-allumage, de préférence une résis- tance de quelques mégohms, ou encore un condensateur de l'ordre de 10 nF, relie l'anode commune des deux thyristors au contact de gâchette du pilote et l'amorçage est obtenu en supprimant un court-circuit normalement établi entre la gâchette et la cathode du thyristor pilote.According to another particular feature of the invention, an impedance of self-ignition assistance, preferably a resistance of a few megohms, or even a capacitor of the order of 10 nF, connects the common anode. of the two thyristors in contact with the pilot trigger and the ignition is obtained by eliminating a short circuit normally established between the trigger and the cathode of the pilot thyristor.
Une telle structure, dans laquelle la surface d'injection du courant d'assistance dans le thyristor pilote (surface de son émetteur) est réduite, présente l'avantage que le thyristor pilote, qui possède un gain notable même à très bas niveau, s'amorce pour le très petit courant de commande fourni par la résistance d'assistance, tandis que, grâce à la grande surface du thyristor principal, la structure peut conduire un courant élevé et, par suite, commander une puis¬ sance importante.Such a structure, in which the area for injecting the assistance current into the pilot thyristor (surface of its emitter) is reduced, has the advantage that the pilot thyristor, which has a significant gain even at very low level, s for the very small control current provided by the assistance resistor, while, thanks to the large surface of the main thyristor, the structure can conduct a high current and, consequently, command a large power.
Comme on l'a indiqué ci-dessus, cette structure se distingue 5 radicalement de la structure classique de thyristor à gâchette amplificatrice, dans laquelle, en particulier, l'amorçage du thyristor pilote se fait en appliquant une tension de commande à sa gâchette. Elle présente, par rapport à celle-ci, des avantages importants et, en particu-As indicated above, this structure differs radically from the conventional amplifier thyristor structure, in which, in particular, the pilot thyristor is primed by applying a control voltage to its trigger. It has significant advantages over it, and in particular
10 lier : une plus grande résistance du composant du fait que l'allumage est bien homogène sur une grande partie de sa surface ; une simplification du circuit de commande, qui doit simplement écouler un faible courant dans un court- circuit ; une meilleure tenue en tension et en dV/dt.10 to bind: greater resistance of the component because the ignition is very homogeneous over a large part of its surface; a simplification of the control circuit, which simply has to flow a small current in a short circuit; better resistance to tension and dV / dt.
15.15.
Dans les applications de puissance, sur les réseaux indus¬ triels de 220 V, la structure devra tenir des tensions inverses d'environ 750 V. On notera que le court-circuit gâchette-cathode transforme la tenue en tension BVCE0 en une 0 tenue en tension VCES, ce qui facilite l'obtention du résultat recherché.In power applications, on 220 V industrial networks, the structure will have to withstand reverse voltages of approximately 750 V. It will be noted that the trigger-cathode short-circuit transforms the voltage withstand BV CE0 into a 0 with in V CES voltage, which facilitates obtaining the desired result.
En pratique, la structure de thyristor comportant les parti¬ cularités susvisées sera cependant inapte à fonctionner sur 5 réseau 380 Veff. Le passage d'une tension d'alimentation de 220 Veff à 380 Veff conduirait en effet, en particulier, à multiplier la durée de vie des porteurs minoritaires dans la base N par un facteur de 3,6, ce qui obligerait à obtenir une durée de vie de plus de 90 microsecondes au lieu de 26 0 microsecondes ; une telle caractéristique est irréalisable actuellement.In practice, the thyristor structure comprising the abovementioned particularities will, however, be incapable of operating on a 380 Veff network. The passage of a supply voltage from 220 Veff to 380 Veff would in fact lead, in particular, to multiplying the life of minority carriers in the base N by a factor of 3.6, which would require obtaining a duration life of more than 90 microseconds instead of 26 0 microseconds; such a characteristic is currently impracticable.
Suivant une autre particularité de l'invention, pour augmen¬ ter le gain à bas niveau du transistor NPN qui fait partie 5 de la structure du thyristor pilote et* compenser ainsi la perte de gain du transistor PNP résultant de l'augmentation d'épaisseur de sa base N qui est nécessaire si l'on veut tenir des tensions inverses de 1200 V par exemple, onAccording to another feature of the invention, to increase the gain at low level of the NPN transistor which is part 5 of the structure of the pilot thyristor and * thus compensate for the loss of gain of the PNP transistor resulting from the increase in thickness of its base N which is necessary if one wants to hold reverse voltages of 1200 V for example, one
O PI réalise son émetteur sous la forme d'une structure à double couche N + N—.O PI realizes its transmitter in the form of a double layer structure N + N—.
Il a déjà été proposé de réaliser des émetteurs à doubla couche dans des transistors bipolaires (voir, en particu¬ lier, l'article intitulé : "Nouveau dispositif bipolaire à structure à faible concentration d'impuretés d'émetteur" : IEDM Technical Digest 1971, pages 262 à 265). Ces structu¬ res, dites "LEC", sont destinées à des utilisations à haute fréquence ou à faible puissance et il n'a pas été suggéré jusqu'ici d'appliquer un tel procédé à la réalisation de structures de thyristors et, a fortiori, de structures à gâchette amplificatrice.It has already been proposed to produce double-layer transmitters in bipolar transistors (see, in particular, the article entitled: "New bipolar device with structure with low concentration of emitter impurities": IEDM Technical Digest 1971 , pages 262 to 265). These structures, called "LEC", are intended for high frequency or low power uses and it has not been suggested so far to apply such a process to the production of thyristor structures and, a fortiori , of trigger trigger structures.
D'autres particularités, ainsi que les avantages de l'inven¬ tion, apparaîtront clairement à la lumière de la description ci-après.Other particularities, as well as the advantages of the invention, will become clear in the light of the description below.
Au dessin annexé :In the attached drawing:
La figure 1 est un schéma de principe d'une structure intégrée de thyristor à auto-allumage assisté confor¬ me à l'invention ; etFigure 1 is a block diagram of an integrated structure of assisted self-ignition thyristor in accordance with the invention; and
La figure 2 illustre un premier mode d'exécution de cette structure, dontFIG. 2 illustrates a first embodiment of this structure, of which
La figure 3 illustre une variante.Figure 3 illustrates a variant.
A la figure 1, on a représenté une structure de thyristor comprenant une base d'inhibition 1 de type P, une base prin¬ cipale 2 de type N et une deuxième région d'émetteur 3 de type P, qui sont communes aux deux thyristors que constitue la structure.In FIG. 1, a thyristor structure is shown comprising an inhibition base 1 of type P, a main base 2 of type N and a second emitter region 3 of type P, which are common to the two thyristors that is the structure.
Par une technique "planar", on a formé des premières régions d'émetteur de type N désignées par 4 pour le thyristor principal, par 5 pour le thyristor pilote ou auxiliaire. La région 5 est située au centre de la plaquette de silicium et a par exemple 1 mm de diamètre, pour une plaquette de 1 cm par exemple. Ces valeurs ne sont pas limitatives, et les va¬ leurs réelles dépendront de la puissance désirée. On a représenté en 6 un contact d'anode, en Kp des contacts de cathode du thyristor principal, reliés à la borne de cathode K de l'ensemble, en Gp des contacts de gâchette du thyristor principal, en Ga des contacts de gâchette du thyristor auxi¬ liaire, reliés à la borne d'anode A de l'ensemble à travers une résistance d'assistance de quelques mégohms ou, dans l'exemple figuré, par un condensateur Cass de l'ordre de 10 nF, en Ka le contact de cathode du thyristor auxiliaire, relié aux contacts Gp, et à la borne K par l'intermédiaire d'un interrupteur I,. Le point commun à Cass et Ga est relié à la borne K par l'intermédiaire d'un interrupteur I- et de l'interrupteur I, en série.By a "planar" technique, first N-type emitter regions were formed designated by 4 for the main thyristor, by 5 for the pilot or auxiliary thyristor. The region 5 is located in the center of the silicon wafer and has for example 1 mm in diameter, for a wafer of 1 cm for example. These values are not limiting, and the actual values will depend on the desired power. An anode contact is shown in 6, in Kp of the cathode contacts of the main thyristor, connected to the cathode terminal K of the assembly, in Gp of the gate contacts of the main thyristor, in Ga of the gate contacts of the auxiliary thyristor, connected to the anode terminal A of the assembly through an assistance resistance of a few megohms or, in the illustrated example, by a Cass capacitor of the order of 10 nF, in Ka le cathode contact of the auxiliary thyristor, connected to the contacts Gp, and to the terminal K by means of a switch I ,. The point common to Cass and Ga is connected to terminal K via a switch I- and switch I, in series.
A titre d'exemple, dans un premier mode d'exécution où l'émetteur N est à une seule couche,, les concentrations en atomes d'impuretés par cm , sont :For example, in a first embodiment where the emitter N is a single layer, the concentrations of impurity atoms per cm, are:
10 19 à 1020 A/cm3 pour les régions 4 et 5, 10 17 A/cm3 pour la région 1,10 19 to 1020 A / cm3 for regions 4 and 5, 10 17 A / cm3 for region 1,
10 A/cm pour la région 2,10 A / cm for region 2,
1017 A/cm"3 pour la région 3.1017 A / cm "3 for region 3.
Un sillon 7 coupant toute l'épaisseur de la couche 1 et entourant complètement l'émetteur 5 est réalisé suivant la technique, connue en soi, dite "planar-sillon", qui consiste en un décapage profond de toute la couche 1, suivi d'un décapage complémentaire de toute la surface pour supprimer l'angle vif créé par le décapage profond, et enfin, d'une oxydation thermique pour passivation "planar". Le décapage complémentaire sera impérativement réalisé par une techni- que assurant un très bon état de surface (absence de micro¬ défauts cristallins et très faible densité de pièges) , par exemple par gravure ionique réactive. Cette qualité deA groove 7 cutting the entire thickness of the layer 1 and completely surrounding the emitter 5 is produced according to the technique, known per se, called "planar-furrow", which consists of a deep pickling of the entire layer 1, followed by 'additional stripping of the entire surface to eliminate the sharp angle created by deep stripping, and finally, thermal oxidation for "planar" passivation. Complementary stripping must be carried out by a technique ensuring a very good surface condition (absence of crystalline micro¬ defects and very low trap density), for example by reactive ion etching. This quality of
O P1 préparation de surface du sillon est en effet nécessaire si l'on veut retrouver les caractéristiques de très faible densité de centres de recombinaison en surface qui ont fait adopter la technique "planar" pour obtenir de très grandes sensibilités.O P1 surface preparation of the groove is indeed necessary if we want to find the characteristics of very low density of recombination centers on the surface which made adopt the "planar" technique to obtain very high sensitivities.
Cette technique planar-sillon permet de maintenir de faibles taux de recombinaison en surface et, par suite, une grande sensibilité du thyristor pilote. Elle évite un court-circuit à travers la jonction d'émetteur du thyristor pilote, qui gênerait son amorçage.This planar-groove technique makes it possible to maintain low rates of surface recombination and, consequently, a high sensitivity of the pilot thyristor. It avoids a short circuit through the emitter junction of the pilot thyristor, which would hinder its ignition.
La gâchette 8 et l'émetteur 7 ont, de préférence, une struc¬ ture fortement interdigitée (ou toute autre structure équi- valente) , pour que, comme on l'a expliqué ci-dessus, la résistance apparente de shunt par rapport à la jonction émetteur-base du thyristor principal soit, pour un cristal de 1 cm , de quelques centièmes d'Ohms par exemple, grâce à une résistance de couche de la couche P qui sera par exemple de l'ordre de 10 ohms par carré (ce qui se note généralement 10 Ω/CB) . Une telle structure ne sera en général pas indis¬ pensable pour la jonction d'émetteur du thyristor auxiliai¬ re, du fait de sa très faible dimension.The trigger 8 and the transmitter 7 preferably have a highly interdigitated structure (or any other equivalent structure), so that, as explained above, the apparent shunt resistance with respect to the emitter-base junction of the main thyristor is, for a crystal of 1 cm, a few hundredths of Ohms for example, thanks to a layer resistance of layer P which will be for example of the order of 10 ohms per square ( which is generally noted 10 Ω / CB). Such a structure will generally not be essential for the junction of the auxiliary thyristor emitter, due to its very small size.
On donnera plus loin des procédés d'exécution préférés de la structure qui vient d'être décrite, procédés qui permettent notamment de réaliser un thyristor principal très sensible. La structure principale est du type "mesa" (c'est-à-dire isolée par rodage et attaque chimique à la périphérie de la plaquette, suivis d'une passivation) . Lorsqu'une tension d'alimentation de 220 Veff par exemple est appliquée sur la borne d'anode A, la borne K étant à une tension nulle (lors¬ que I-_ et I2 sont ouverts) , il en est de même de la région 5, et le faible courant injecté dans la gâchette Ga à travers le condensateur Cass suffit à provoquer l'amorçage du thyristor auxiliaire peu après le premier passage par zéro de la tension d'alimentation, suivant le principe de fonc¬ tionnement à auto-allumage assisté décrit dans la demande de brevet susvisée. On notera que la jonction d'émetteur du thyristor auxiliaire est protégée du court-circuit par la résistance qui existe entre les portions dé base d'inhibi¬ tion correspondantes des deux thyristors.Preferred methods of executing the structure which has just been described will be given below, methods which make it possible in particular to produce a very sensitive main thyristor. The main structure is of the "mesa" type (that is to say isolated by running-in and chemical attack at the periphery of the wafer, followed by a passivation). When a supply voltage of 220 Veff for example is applied to the anode terminal A, terminal K being at zero voltage (when I-_ and I 2 are open), the same is true of region 5, and the low current injected into the trigger Ga through the capacitor Cass is sufficient to cause the ignition of the auxiliary thyristor shortly after the first zero crossing of the supply voltage, according to the operating principle of auto - assisted ignition described in the request for aforementioned patent. It will be noted that the emitter junction of the auxiliary thyristor is protected from short circuit by the resistance which exists between the corresponding base inhibition portions of the two thyristors.
A ce moment, la base commune P étant à un potentiel voisin de celui de l'anode, et le court-circuit entre la gâchette Gp et l'émetteur 4 étant supprimé puisque I, est encore ou¬ vert, le courant principal du thyristor auxiliaire passe dans la première jonction d'émetteur du thyristor principal, et celui-ci s'amorce rapidement. L'allumage se propage très rapidement à l'ensemble de la surface du contact d'émetteur. Cette surface d'allumage peut occuper 80 % environ de la surface totale de la plaquette.At this time, the common base P being at a potential close to that of the anode, and the short circuit between the trigger Gp and the emitter 4 being eliminated since I, is still open, the main current of the thyristor auxiliary goes into the first transmitter junction of the main thyristor, and it starts quickly. The ignition spreads very quickly over the entire surface of the transmitter contact. This ignition surface can occupy approximately 80% of the total surface of the wafer.
La structure à gâchette amplificatrice conforme à ce premier mode d'exécution de l'invention est apte à commuter des courants allant par exemple de plusieurs dizaines à plu¬ sieurs centaines d'ampères.The amplifier trigger structure according to this first embodiment of the invention is capable of switching currents ranging for example from several tens to several hundreds of amps.
On notera toutefois que le gain du transistor PNP d'une telle structure est relativement faible, car sa base N doit avoir une épaisseur relativement grande pour assurer la tenue en tension. Il en résulte que, telle que décrite ci- dessus, la structure ne sera plus susceptible de s'auto- allumer pour des tensions d'alimentation de 380 Veff par exemple, sauf si l'on réussit à donner au transistor NPN un gain très élevé à très bas niveau.It will be noted, however, that the gain of the PNP transistor of such a structure is relatively low, since its base N must have a relatively large thickness to ensure the voltage withstand. As a result, as described above, the structure will no longer be able to self-ignite for supply voltages of 380 Veff for example, unless we succeed in giving the NPN transistor a very high gain. raised to very low level.
C'est pourquoi, selon un second mode d'exécution, illustré par la figure 2, la structure est réalisée avec des émet¬ teurs à double couche, avantageusement suivant le procédé suivant, donné à titre non limitatif :This is why, according to a second embodiment, illustrated in FIG. 2, the structure is produced with double-layer emitters, advantageously according to the following method, given without limitation:
a) on part d'un substrat 2 de silicium N~ faiblement dopé (par exemple 10 A/cm ) pour tenir la haute tension.a) we start from a silicon substrate N ~ lightly doped (for example 10 A / cm) to hold the high voltage.
-CREAI OMPI-CREAI WIPO
« °*O b) on effectue une diffusion P+ sur la face arrière, pour constituer la seconde région d'émetteur 3,"° * O b) a P + diffusion is carried out on the rear face, to constitute the second emitter region 3,
c) on effectue une épitaxie épaisse de type P sur la face avant,' avec une concentration en impuretés dec) a thick P-type epitaxy is carried out on the front face, with a concentration of impurities of
10 A/c par exemple, suivie d'une exo-diffusion destinée à réduire la concentration d'impuretés en surface, afin de réduire le risque de migrations d'im¬ puretés dans la couche N qui sera réalisée à l'étape (d) . On obtient ainsi la première région de base P de la structure,10 A / c for example, followed by an exo-diffusion intended to reduce the concentration of impurities on the surface, in order to reduce the risk of migrations of purities in the N layer which will be carried out in step (d ). The first base region P of the structure is thus obtained,
d) on effectue, sur toute la surface de la puce, une épitaxie mince (quelques microns) de type N avec uned) a thin N-type epitaxy (a few microns) is carried out over the entire surface of the chip with a
15 3 concentration en impuretés de 10 A/cm par exemple,15 3 impurity concentration of 10 A / cm for example,
e) on effectue, sur toute la face des contacts de gâchet¬ te, une diffusion mince ou une implantation ionique de type P , à température réduite, pour recevoir les contacts de gâchette ; cette couche de base superfi¬ cielle fortement dopée permet d'obtenir une résistan¬ ce interne de base très réduite (quelques dixièmes d'ohms) ce qui garantit une très bonne tenue en dV/dt,e) a thin diffusion or a P-type ion implantation is carried out on the entire face of the gate contacts, at reduced temperature, to receive the gate contacts; this highly doped superficial base layer makes it possible to obtain a very reduced internal resistance (a few tenths of an ohm), which guarantees very good resistance in dV / dt,
f) on réalise le sillon 7 de la manière qui a été indi¬ quée précédemment,f) the groove 7 is produced in the manner which has been indicated previously,
g) on effectue localement, dans les régions d'émetteur 4 et 5, une diffusion très mince (1 micron par exemple) , de type N + (concentration : 1019 A/cm3 par exemple) , à température réduite, ou une implantation ionique,g) a very thin diffusion (1 micron for example), of the N + type (concentration: 1019 A / cm 3 for example) is carried out locally, in the emitter regions 4 and 5, at reduced temperature, or an ion implantation ,
h) on effectue un dépôt d'oxyde de silicium.h) depositing silicon oxide.
Les contacts sont ensuite réalisés de façon classique.The contacts are then made in a conventional manner.
L'isolement périphérique des deux jonctions PN est fait de manière classique et divers artifices connus sont utilisésThe peripheral isolation of the two PN junctions is made in a conventional manner and various known devices are used
OMPI_ pour accroître la tenue en tension. Toutefois on peut aussi, indépendamment de l'objet du brevet, effectuer un isolement du type PLANAR.WIPO_ to increase the tensile strength. However, it is also possible, independently of the subject of the patent, to carry out isolation of the PLANAR type.
Toutes les opérations critiques en surface (croissance ou dépôt d'oxyde, passivations, et autres) sont réalisées avec un très grand soin de propreté, comme indiqué dans la deman¬ de de brevet français susvisée No 82 19728. Cette technolo¬ gie à double couche d'émetteur permet d'obtenir des gains bêta de l'ordre de 1000 à 1 mA, du fait qu'elle réduit le courant de recombinaison des porteurs minoritaires à travers la région de charge d'espace émetteur-base.All critical surface operations (growth or deposition of oxide, passivations, and others) are carried out with great care of cleanliness, as indicated in the above-mentioned French patent application No 82 19728. This dual technology emitter layer provides beta gains of the order of 1000 to 1 mA, since it reduces the recombination current of minority carriers across the emitter-base space charge region.
En variante, l'opération (b) pourra comporter en outre une diffusion P sur la face avant, et l'étape (c) sera alors supprimée.As a variant, operation (b) may also include a diffusion P on the front face, and step (c) will then be deleted.
A la figure 3, on a illustré un troisième mode d'exécution de la structure, consistant à réaliser des émetteurs ultra- minces dopés à partir de silicium polycristallin déposé. Plus délicat à mettre en œuvre que le procédé conforme au second mode d'exécution décrit ci-dessus, ce procédé présen¬ te, en contre-partie, les avantages suivants :In FIG. 3, a third embodiment of the structure is illustrated, consisting in producing ultra-thin emitters doped from deposited polycrystalline silicon. More difficult to implement than the method in accordance with the second embodiment described above, this method presents, in return, the following advantages:
- il permet la réalisation d'un isolement "planar", grâce à l'auto-alignement de la zone diffusée par rapport à la fenêtre de diffusion,- it allows the realization of a "planar" isolation, thanks to the self-alignment of the broadcast area with respect to the broadcast window,
- il permet de réduire la résistance latérale parasite de base par une couche enterrée P ,- it makes it possible to reduce the basic parasitic lateral resistance by a buried layer P,
- il réduit le risque de dégradation de la couche d'émetteur N par rétro-diffusion d'ions de type P lors de l'élaboration de la couche P .- It reduces the risk of degradation of the emitter layer N by backscattering of P-type ions during the development of the P layer.
Bien qu'il fournisse une tenue en tension inférieure pour les émetteurs, celle-ci est suffisante pour le bon fonction¬ nement du dispositif et n'est donc pas un inconvénient dans l'application décrite ici. Le procédé sera identique à celui qui est décrit ci-dessus en ce qui concerne les opérations, a - b - c.Although it provides a lower voltage withstand for the transmitters, this is sufficient for the proper functioning of the device and is therefore not a drawback in the application described here. The process will be identical to that described above with regard to operations, a - b - c.
On effectuera ensuite :Then we will do:
d - une implantation locale, sur la face avant, de bases enterrées de type P ,d - local installation, on the front face, of P-type buried bases,
e - une deuxième épitaxie mince (par exemple 2 microns) de type N, avec par exemple une concentration en impure- tés de 10 15 A/cm3, effectuée sur toute la face avant,e - a second thin epitaxy (for example 2 microns) of type N, with for example a concentration of impurities of 10 15 A / cm 3, carried out on the entire front face,
f - une'diffusion mince P locale, effectuée au niveau des implantations locales P enterrées, ou une deuxième implantation ionique ? cette opération est destinée à former des régions de prise des contacts Gp et Ga,f - a thin local P diffusion, carried out at the level of local buried P implantations, or a second ion implantation? this operation is intended to form contact regions Gp and Ga,
g - la réalisation du sillon 7 de la manière déjà décrite,g - making the groove 7 in the manner already described,
h - une réoxydation mince à température réduite, avec photogravure pour mettre à nu les régions d'émetteurs,h - a thin reoxidation at reduced temperature, with photoetching to expose the regions of the emitters,
i - le dépôt d'une couche de silicium polycristallin dopé N , puis la photogravure pour délimiter les régions d'émetteurs,i - the deposition of a layer of N-doped polycrystalline silicon, then photogravure to delimit the regions of emitters,
j - la diffusion très mince (1 micron) de cette couche polycristalline N+ à l'état solide, par traitement thermique à température réduite (800 à 900°C) .j - the very thin diffusion (1 micron) of this polycrystalline N + layer in the solid state, by heat treatment at reduced temperature (800 to 900 ° C).
Cette diffusion donne la couche N des émetteurs à double couche.This diffusion gives the layer N of the transmitters with double layer.
Les prises de contact et l'isolement périphérique des jonc- tions se feront comme expliqué ci-dessus et toutes les opérations critiques en surface seront également réalisées avec les précautions indiquées. Il va de soi que divers autres modes d'exécution pourront être imaginés, sans s'écarter de l'esprit de l'invention. Si l'on désire réaliser une structure de thyristor susceptible de débiter à des puissances encore plus élevées, il peut être envisagé d'utiliser la structure décrite dans la pré¬ sente demande comme le pilote d'une structure de thyristor de plus grande dimension dont elle déclencherait l'auto- amorçage. Contact and peripheral isolation of junctions will be as explained above and all critical operations on the surface will also be carried out with the precautions indicated. It goes without saying that various other embodiments can be imagined, without departing from the spirit of the invention. If it is desired to produce a thyristor structure capable of delivering at even higher powers, it may be envisaged to use the structure described in the present application as the pilot of a larger dimension thyristor structure, of which it would trigger self-priming.

Claims

Revendications de brevet Patent claims
1. Structure intégrée de thyristor . comportant un thyristor principal de type "mesa" et un thyristor auxiliai¬ re constitué par une portion centrale de petite dimension de la structure "mesa" et délimité suivant la technique "planar" avec absence d'effet de bord, caractérisée en ce que la base principale du thyristor auxi¬ liaire est isolée de celle du thyristor principal, que le thyristor principal a une gâchette propre (Gp) et une grande sensibilité, que la résistance entre la base d'inhibition du thyristor auxiliaire et celle du thyristor principal est au moins de l'ordre du mégohm et que la commande est réalisée par court-circuit (I2) entre gâchette (Ga) et cathode (Ka) du thyristor auxiliaire et par court-circuit (I,) entre gâchette (Gp) et cathode (Kp) du thyristor principal.1. Integrated thyristor structure. comprising a main thyristor of the "mesa" type and an auxiliary thyristor constituted by a central portion of small dimension of the "mesa" structure and delimited according to the "planar" technique with no edge effect, characterized in that the main base of the auxiliary thyristor is isolated from that of the main thyristor, that the main thyristor has its own trigger (Gp) and a high sensitivity, that the resistance between the inhibition base of the auxiliary thyristor and that of the main thyristor is at less on the order of megohm and that the control is carried out by short circuit (I 2 ) between trigger (Ga) and cathode (Ka) of the auxiliary thyristor and by short circuit (I,) between trigger (Gp) and cathode (Kp) of the main thyristor.
2. Structure selon la revendication 1, caractérisée par un sillon d'isolement (7) coupant toute l'épaisseur de la diffusion de base (P) , sillon lui-même passive par oxydation thermique suivant la technique "planar-sillon".2. Structure according to claim 1, characterized by an isolation groove (7) cutting the entire thickness of the base diffusion (P), itself groove passive by thermal oxidation according to the "planar-groove" technique.
3. Structure selon la revendication 2, caractérisée en ce que le contact de gâchette (Gp) du thyristor principal .est placé à l'extérieur de l'émetteur (4) dudit thyristor.3. Structure according to claim 2, characterized in that the trigger contact (Gp) of the main thyristor .is placed outside of the transmitter (4) of said thyristor.
4. Structure selon l'une des revendications 1 à 3, caractérisée en ce que les thyristors pilote et principal sont agencés pour que la résistance apparente de shunt par rapport à la jonction émetteur-base correspondante soit très faible, avantageusement de l'ordre de quelques centièmes à quelques dixièmes d'ohms.4. Structure according to one of claims 1 to 3, characterized in that the pilot and main thyristors are arranged so that the apparent shunt resistance relative to the corresponding emitter-base junction is very low, advantageously of the order of a few hundredths to a few tenths of an ohm.
5. Structure selon l'une des revendications 1 à 4, caractérisée par un thyristor auxiliaire de grande sensibi¬ lité et par une admittance d'assistance à l'allumage reliant l'anode (A) commune aux deux thyristors au contact de gâchette (Ga) du thyristor auxiliaire. 5. Structure according to one of claims 1 to 4, characterized by an auxiliary thyristor of great sensitivity and by an ignition assistance admittance connecting the anode (A) common to the two thyristors in trigger contact ( Ga) of the auxiliary thyristor.
6. Structure selon l'une des revendications 1 à 5, caractérisée en ce que la première région d'émetteur (5) du thyristor auxiliaire est réalisée sous la forme d'une struc¬ ture à double couche N N~ (figures 2 ou 3) de concentration de dopeurs.6. Structure according to one of claims 1 to 5, characterized in that the first emitter region (5) of the auxiliary thyristor is produced in the form of a structure with double layer NN ~ (Figures 2 or 3 ) of doping concentration.
7. Structure selon la revendication 6, caractérisée en ce que la première région d'émetteur (5) du thyristor auxiliaire est réalisée par dopage à partir d'une couche de silicium polycristallin déposée (figure 3) dopée N et par diffusion très mince de cette couche à l'état solide.7. Structure according to claim 6, characterized in that the first emitter region (5) of the auxiliary thyristor is produced by doping from a deposited layer of polycrystalline silicon (Figure 3) doped N and by very thin diffusion of this layer in the solid state.
OMPIWIPO
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EP84900993A 1983-03-01 1984-03-01 Integrated self-firing thyristor structure for on/off switching of high currents, and control circuit thereof Withdrawn EP0135559A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8303306 1983-03-01
FR8303306A FR2542148B1 (en) 1983-03-01 1983-03-01 CONTROL CIRCUIT OF A THYRISTOR OR TRIAC TYPE SENSITIVE SEMICONDUCTOR DEVICE WITH SELF-IGNITION ASSISTANCE IMPEDANCE AND ITS APPLICATION TO THE PRODUCTION OF A SWITCH ASSEMBLY COMBINING A SENSITIVE THYRISTOR WITH A LESS SENSITIVE THYRISTOR

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EP0135559A1 true EP0135559A1 (en) 1985-04-03

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US (1) US4599633A (en)
EP (1) EP0135559A1 (en)
JP (1) JPS60501282A (en)
FR (1) FR2542148B1 (en)
IT (1) IT1173414B (en)
WO (1) WO1984003588A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2586141B1 (en) * 1985-08-06 1987-11-20 Thomson Csf SENSITIVE THYRISTOR WITH INTEGRATED TRIGGER-CATHODE DECOUPLING
DE3941932A1 (en) * 1989-12-19 1991-06-20 Eupec Gmbh & Co Kg METHOD FOR PRODUCING ANODE-SIDE SHORT CIRCUITS IN THYRISTORS
FR2683946B1 (en) * 1991-11-15 1997-05-09 Sgs Thomson Microelectronics SEMICONDUCTOR COMPONENT FOR PROTECTION AGAINST OVERVOLTAGES.
JP2831516B2 (en) * 1992-09-21 1998-12-02 株式会社日立製作所 Superconducting energy storage device
JP4188428B2 (en) * 1998-09-10 2008-11-26 三菱電機株式会社 Semiconductor device and driving method thereof
US9171977B2 (en) 2011-06-17 2015-10-27 Cree, Inc. Optically assist-triggered wide bandgap thyristors having positive temperature coefficients

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3524114A (en) * 1968-02-29 1970-08-11 Jearld L Hutson Thyristor having sensitive gate turn-on characteristics
SE320729B (en) * 1968-06-05 1970-02-16 Asea Ab
FR2222801A2 (en) * 1973-03-22 1974-10-18 Crouzet Sa Thyristor controlled electronic switch - having thyristor switching circuit connected across diode bridge
JPS5629458B2 (en) * 1973-07-02 1981-07-08
GB1499845A (en) * 1975-03-26 1978-02-01 Mullard Ltd Thyristors
DE2534703C3 (en) * 1975-08-04 1980-03-06 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Switchable thyristor
NL7604951A (en) * 1976-05-10 1977-11-14 Philips Nv GLASS FOR PASSIVING SEMICONDUCTOR DEVICES.
DE2633324C2 (en) * 1976-07-24 1983-09-15 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Process for the production of semiconductor components with high reverse voltage loading capacity
JPS5942991B2 (en) * 1977-05-23 1984-10-18 株式会社日立製作所 thyristor
DE2739187C2 (en) * 1977-08-31 1981-10-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Controllable semiconductor rectifier with a plurality of layers of different conductivity types
DE2748316C2 (en) * 1977-10-27 1986-09-04 Siemens AG, 1000 Berlin und 8000 München Circuit arrangement for reducing the release time of a thyristor
US4314266A (en) * 1978-07-20 1982-02-02 Electric Power Research Institute, Inc. Thyristor with voltage breakover current control separated from main emitter by current limit region
JPS5574168A (en) * 1978-11-28 1980-06-04 Oki Electric Ind Co Ltd Pnpn switch
DE2913572A1 (en) * 1979-04-04 1980-10-16 Siemens Ag Phase controlled thyristor triggering circuit - reduces bulk by eliminating isolating transformer whilst keeping galvanic isolation between control element and thyristor power circuit
JPS55133569A (en) * 1979-04-06 1980-10-17 Hitachi Ltd Semiconductor device
US4278705A (en) * 1979-11-08 1981-07-14 Bell Telephone Laboratories, Incorporated Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide
US4261001A (en) * 1980-05-23 1981-04-07 General Electric Company Partially isolated amplifying gate thyristor with controllable dv/dt compensation, high di/dt capability, and high sensitivity
DE3112940A1 (en) * 1981-03-31 1982-10-07 Siemens AG, 1000 Berlin und 8000 München THYRISTOR WITH CONNECTABLE INTERNAL POWER AMPLIFIER AND METHOD FOR ITS OPERATION

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8403588A1 *

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Publication number Publication date
JPS60501282A (en) 1985-08-08
FR2542148B1 (en) 1986-12-05
IT1173414B (en) 1987-06-24
IT8419866A0 (en) 1984-03-01
FR2542148A1 (en) 1984-09-07
US4599633A (en) 1986-07-08
WO1984003588A1 (en) 1984-09-13

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