EP0122984A1 - Circuit de mesure de temps - Google Patents

Circuit de mesure de temps Download PDF

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Publication number
EP0122984A1
EP0122984A1 EP83302263A EP83302263A EP0122984A1 EP 0122984 A1 EP0122984 A1 EP 0122984A1 EP 83302263 A EP83302263 A EP 83302263A EP 83302263 A EP83302263 A EP 83302263A EP 0122984 A1 EP0122984 A1 EP 0122984A1
Authority
EP
European Patent Office
Prior art keywords
clock pulses
signal
gate
pulse signal
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP83302263A
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German (de)
English (en)
Other versions
EP0122984B1 (fr
Inventor
Tadao Hiramatsu
Sunao Katayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hagiwara Electric Co Ltd
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Hagiwara Electric Co Ltd
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Filing date
Publication date
Application filed by Hagiwara Electric Co Ltd filed Critical Hagiwara Electric Co Ltd
Priority to EP83302263A priority Critical patent/EP0122984B1/fr
Priority to DE8383302263T priority patent/DE3377748D1/de
Publication of EP0122984A1 publication Critical patent/EP0122984A1/fr
Application granted granted Critical
Publication of EP0122984B1 publication Critical patent/EP0122984B1/fr
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Definitions

  • the present invention relates to a time measuring circuit for meters of the pulse reflection type such as an ultrasonic axial force meter, an ultrasonic thickness meter or the like.
  • a primary object of the present invention to provide an improved time measuring circuit which is capable of effecting accurate measurement of a time of substantially 1 nS without provision of a high speed counter.
  • a time measuring circuit for meters of the pulse reflection type which includes a pulse oscillator means for applying a transmission pulse signal to an object to be measured, a receiving amplifier for receiving an echo pulse signal reflected from the object, a gate signal generator connected to receive the transmission pulse signal from the oscillator means and the echo pulse signal from the amplifier so as to produce a gate pulse signal the duration of which is proportional to a value of the object to be measured, first means for producing first and second output pulses at a predetermined frequency during appearance of the gate pulse signal, second means for measuring a value of the first output pulses from the first means and for producing an output signal indicative of the measured value, third means responsive to the first and second output pulses from the first means for converting the duration of the gate pulse signal into the corresponding voltage value, fourth means for converting the finally converted voltage value into a digital value and for producing an output signal indicative of the digital value, and a measuring means for measuring a sum of the measured value and the digital value in response to the output signals from the second and fourth means.
  • the first means comprises an oscillator for producing clock pulses at a predetermined frequency, a complementary-output element responsive to the gate pulse signal from the gate signal generator for producing first and second clock pulses which are the same at their phase and relatively inverted, gate means responsive to the gate pulse signal from the gate signal generator for passing therethrough the first and second clock pulses during appearance of the gate pulse signal, and a flip-flop for applying the first clock pulses to the second means and for applying the first and second clock pulses to the third means.
  • the second means is in the form of a counter connected to the flip-flop to count the first clock pulses
  • the third means is in the form of a pair of integration circuits connected to the flip-flop to selectively integrate the first and second clock pulses in response to the gate pulse signal
  • the fourth means is in the form of an analog-to-digital converter connected to the integration circuits to convert the finally integrated value into a digital value.
  • Fig. 1 illustrates a time measuring circuit adapted to an ultrasonic axial force meter of the pulse reflection type.
  • the time measuring circuit includes a crystal oscillator 1 for producing clock pulses A in the form of rectangular waves at a frequency of 100 KHz - 10 MHz, and a JK flip-flop 2 connected at its clock terminal CK to the output terminal of oscillator 1 and at its other input terminals J and K to a DC voltage source Vcc.
  • the time measuring circuit further includes an RS flip-flop 3 which is applied at its set terminal S with a transmission pulse signal TTP from the ultrasonic axial force meter and at its reset terminal R with a reflection echo pulse RTP from the axial force meter.
  • RS flip-flop 3 is connected at its output terminal Q to a clear input terminal CLR of flip-flop 2, each first input terminal of NAND gates 4 and 5, and the input terminal of a timer 8.
  • the output terminal Q of RS flip-flop 3 is further connected to each set terminal S of first and second integration circuits 11 and 12 respectively through inverters 9 and 10.
  • NAND-gates 4 and 5 are connected at their second input terminals to output terminals Q and Q of. JK flip-flop 2 and at their output terminals to reset and set terminals R and S of a second flip-flop 6 respectively.
  • a first output terminal Q of RS flip-flop 6 is connected to the input terminal of a counter 7, a microcomputer 14 and a reset terminal R of the second integration circuit 12, while a second output terminal Q of RS flip-flop 6 is connected to a reset terminalRof the first integration circuit 11.
  • Each output terminal of integration circuits 11 and 12 is connected to an analog-to-digital or A-D converter 13.
  • the microcomputer 14 is commercially available the interface of which is connected at its input terminals to respective output terminals of counter 7, timer 8 and A-D converter 13.
  • the ultrasonic axial force meter includes a frequency divider 21 in the form of a counter for dividing the frequency of the clock pulses A from oscillator 1, and a pulse width adjustor 22 in the form of a one-shot circuit or a differentiation circuit for forming rectangular impulse waves from the divided clock pulses.
  • the rectangular impulse waves are transmitted to a trigger circuit 23 and also transmitted as the transmission pulse signal TTP to RS flip-flop 3.
  • the ultrasonic axial force meter further includes a probe 30 connected to trigger circuit 23 for producing an ultrasonic pulse wave, which is transmitted to an object to be measured, a receiving amplifier 31 for receiving an echo pulse train output from probe 30, and a comparator 32 for comparing an output of the amplifier 31 with a predetermined value to produce the reflection echo pulse RTP.
  • the ultrasonic axial force meter includes a reset circuit 24 connected to a reset terminal R of counter 7 and responsive to the divided clock pulses from frequency divider 21 for producing a reset signal in accordance with the clock pulses from oscillator 1, a ten- key board 41 for applying an input signal indicative of a constant of the object such as a bolt to the computer 14, a select-key board 42 for selecting input data for the computer 14, an indicator 43 for indicating a value measured by the computer 14, and a thermometer 44 for measuring a temperature of the object and the ambient temperature.
  • RS flip-flop 3 is set in response to the transmission pulse signal TTP to produce a gate signal D at a high level and is reset in response to the reflection echo pulse RTP to make the gate signal low level.
  • the duration of gate signal D is proportional, for instance, to an axial length of the bolt to be measured.
  • JK flip-flop 2 divides clock pulses A from oscillator 1 to produce at its terminals Q and Q output signals B, C in the form of rectangular waves which are relatively inverted at half the frequency of the clock pulses.
  • the level of gate signal D becomes low, the output signal B from terminal Q is maintained at a high level, while the output signal C from terminal Q is maintained at a low level.
  • NAND gates 4 and 5 are responsive to the high level gate signal D to permit the output signals B and C applied to the second RS flip-flop 6 from JK flip-flop 2.
  • the timer 8 produces a high level signal therefrom after lapse of a time t
  • the computer 14 is responsive to the high level signal from timer 8 to receive output signals from counter 7 and A-D converter 13, as is described in detail later.
  • each wave form of the output signals E and F from NAND gates 4 and 5 is relatively inverted during appearance of the high level gate signal D.
  • the output signals E and F are maintained at a high level respectively.
  • the second RS flip-flop 6 is applied at its terminals S and R with the relatively inverted output signals E and F to produce relatively inverted output signals G and H at its terminals Q and Q.
  • the second RS flip-flop 6 Upon disappearance of the high level gate signal D, the second RS flip-flop 6 acts to memorize each level of the output signals E and F.
  • the coumputer 14 is responsive to the output signal G from RS flip-flop 6 to discriminate the operation of integration circuit 11 or 12 so as to produce an output signal therefrom for activation of A-D converter 13.
  • the first integration circuit 11 When applied with the high level output signal G from RS flip-flop 6, the first integration circuit 11 operates to produce an output signal I in the form of saw tooth waves.
  • A-D converter 13 is responsive to the output signal from computer 14 to convert the final voltage level of output signal I into a digital value indicative of a time T 2' In the case that the full scale of each saw tooth wave of signal I represents a time defined by one-fourth the frequency of the clock pulses, the time T 2 is measured by a digital value converted from the final saw tooth wave of signal I.
  • the second integration circuit 12 When applied with the low level output signal G from RS flip-flop 6, as is illustrated in (b) of Fig. 3, the second integration circuit 12 operates to produce an output signal J in the form of saw tooth waves.
  • A-D converter 13 is responsive to the output signal from computer 14 to convert the final voltage level of output signal J into a digital value indicative of a time T 3 .
  • each of integration circuits 11 and 12 starts to integrate the high level input signal G or H applied to its reset terminal R during appearance of the high level gate signal D and discharges when the level of the input signal becomes low.
  • each of integration circuits 11 and 12 acts to hold therein the finally integrated voltage, and subsequently A-D converter 13 is activated in response to the output signal from computer 14 to convert the integrated voltage into the digital value and produces an output signal indicative of the digital value upon completion of the voltage conversion.
  • the computer 14 receives an output signal from counter 7 to measure a sum of the time T1 and the time T 2 and/or T 3 , and the counter 7 is reset by a reset signal from reset circuit 24.
  • Fig. 4 there is illustrated a modification of the time measuring circuit described above, in which JK flip-flop 2 in Fig. 1 is replaced with a complementary-output element 200, and the integration circuits 11 and 12 are replaced with a voltage generator 90, a selector 100 and a single integration circuit 110.
  • the complementary-output element 200 is arranged to produce relatively inverted clock pulses A and A at the same phase in response to input clock pulses from oscillator 1.
  • the voltage generator 90 is arranged to produce positive and negative voltage signals +V s , -V which are the same at their voltage levels and different at their polarity
  • the selector 100 is, for example, in the form of an analog switch which is connected to voltage generator 90 to produce a positive voltage signal +V s in response to the high level signal H from RS flip-flop 6 and to produce a negative voltage signal -V s in response to the high level signal G from RS flip-flop 6, and the integration circuit 110 is arranged to charge in response to the positive voltage signal + V s and discharge in response to the negative voltage signal -V thereby to produce an output signal I a in the form of triangular waves as is illustrated in Fig. 5.
  • the other arrangements are substantially the same as those in the time measuring circuit of Fig. 1.
  • A-D converter 13 of the above embodiment may be replaced with a voltage-frequency converter with a counter.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
EP83302263A 1983-04-21 1983-04-21 Circuit de mesure de temps Expired EP0122984B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP83302263A EP0122984B1 (fr) 1983-04-21 1983-04-21 Circuit de mesure de temps
DE8383302263T DE3377748D1 (en) 1983-04-21 1983-04-21 Time measuring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP83302263A EP0122984B1 (fr) 1983-04-21 1983-04-21 Circuit de mesure de temps

Publications (2)

Publication Number Publication Date
EP0122984A1 true EP0122984A1 (fr) 1984-10-31
EP0122984B1 EP0122984B1 (fr) 1988-08-17

Family

ID=8191127

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83302263A Expired EP0122984B1 (fr) 1983-04-21 1983-04-21 Circuit de mesure de temps

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EP (1) EP0122984B1 (fr)
DE (1) DE3377748D1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0277638A2 (fr) * 1987-02-04 1988-08-10 Advantest Corporation Appareil de conversion successive de période de temps en tension
EP0578150A2 (fr) * 1992-07-10 1994-01-12 BODENSEEWERK GERÄTETECHNIK GmbH Appareil de mesure du temps de vol d'impulsions
US20160041529A1 (en) * 2014-08-05 2016-02-11 Denso Corporation Time measuring circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112358A (en) * 1976-04-09 1978-09-05 Takeda Riken Kogyo Kabushikikaisha Digital frequency measuring device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112358A (en) * 1976-04-09 1978-09-05 Takeda Riken Kogyo Kabushikikaisha Digital frequency measuring device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 4, no. 5, October 1961, New York (US) *
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, vol. IM-21, no. 4, November 1972 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0277638A2 (fr) * 1987-02-04 1988-08-10 Advantest Corporation Appareil de conversion successive de période de temps en tension
EP0277638A3 (en) * 1987-02-04 1989-08-09 Advantest Corporation Successive period-to-voltage converting apparatus
EP0578150A2 (fr) * 1992-07-10 1994-01-12 BODENSEEWERK GERÄTETECHNIK GmbH Appareil de mesure du temps de vol d'impulsions
EP0578150A3 (en) * 1992-07-10 1995-11-02 Bodenseewerk Geraetetech Apparatus for measuring the time of flight of pulses
US20160041529A1 (en) * 2014-08-05 2016-02-11 Denso Corporation Time measuring circuit
US9964928B2 (en) * 2014-08-05 2018-05-08 Denso Corporation Time measuring circuit

Also Published As

Publication number Publication date
EP0122984B1 (fr) 1988-08-17
DE3377748D1 (en) 1988-09-22

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