EP0110956A1 - Method for manufacturing a semiconductor device - Google Patents

Method for manufacturing a semiconductor device

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Publication number
EP0110956A1
EP0110956A1 EP83902037A EP83902037A EP0110956A1 EP 0110956 A1 EP0110956 A1 EP 0110956A1 EP 83902037 A EP83902037 A EP 83902037A EP 83902037 A EP83902037 A EP 83902037A EP 0110956 A1 EP0110956 A1 EP 0110956A1
Authority
EP
European Patent Office
Prior art keywords
layer
source
strip
polysilicon
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP83902037A
Other languages
German (de)
French (fr)
Other versions
EP0110956A4 (en
Inventor
Eliezer Kinsbron
William Thomas Lynch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of EP0110956A1 publication Critical patent/EP0110956A1/en
Publication of EP0110956A4 publication Critical patent/EP0110956A4/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon

Definitions

  • This invention relates to a method for manufacturing a semiconductor device comprising the steps of preparing a se iconductive body of a first conductivity type and lightly doped; forming on a surface of the body a relatively thick insulating layer covering the surface except for one or more selected areas thereof; forming a relatively thin insulating layer covering a portion of each selected area and leaving exposed a first region therein; and forming a first conducting layer in each selected area overlying the relatively thin insulating layer therein.
  • IGFET insulated-gate field-effect transistor
  • MOS metal-oxide-semiconductor
  • source and drain regions of such a transistor must be relatively low (e.g., less than 70 ohms per square) so as not to reduce the current conduction capability of the transistor. Therefore, the fabrication of submicron channel length IGFETs requires the formation of source and drain regions which are extremely shallow and which have low sheet resistances.
  • source and drain regions of IGFETs are most frequently formed by either conventional diffusion or by ion implantations.
  • the source and drain regions are formed by diffusing an appropriate dopant impurity into selected areas of a semiconductor surface from an appropriate gas dopant source or from a predeposition source such as a doped semiconductor oxide layer or a doped polycrystalline semiconductor layer in contact with the surface.
  • the impurity is then thermally driven to a desired depth below the surface.
  • the source and drain regions are formed by bombarding selected areas of the semiconductor surface with an energetic beam of an appropriate ionized dopant impurity.
  • ion implantation can provide extremely shallow impurity regions having very high impurity levels, such regions tend to have high sheet resistances owing to lattice damage in the implanted region caused by the ion implantation. Such lattice damage ordinarily results in a significant portion of the dopant impurity not being in proper substitutional lattice sites and a lowering of the carrier mobility in the - 3 -
  • ion implantation has the disadvantage in that a post-implantation annealing treatment for repairing the lattice damage is ordinarily required to lower the sheet resistance of an implanted region. Such an annealing treatment ' ends to cause the region to diffuse to an excessive depth. For that reason, ion implantation cannot ordinarily be used to provide low sheet resistance source and drain regions of less than 2000 Angstroms in depth. Therefore, a need exists for a method for manufacturing IGFET devices which provides transistors having extremely shallow source and drain regions of low sheet resistance.
  • MOS transistors are preferably fabricated by a * self-aligned gate technology in which a patterned gate electrode serves as a diffusion or implantation mask for the formation of the source and drain regions.
  • the gate to source and drain overlap capacitances arise primarily from the lateral diffusion of the source and drain regions under the gate electrode. Since the extent of lateral diffusion of the source or drain region is proportional to the depth of such a region, using shallower source and drain regions generally contributes to reducing the overlap capacitances. However, even in a self-aligned gate MOS technology, it is generally desirable to achieve further reductions in the overlap capacitances.
  • Such reductions are preferably achieved by providing appropriate offsets between the edges of the gate electrode and the masks for the source and drain regions.
  • a prior art technique for providing such offsets is to reduce the width of the gate electrode by oxidation after the formation of the source and drain regions.
  • this technique has the disadvantage in that the thermal treatment required for oxidizing the gate electrode drives the source and drain regions to excessive depths.
  • the gate electrode can be oxidized before the implant. But in that case, as well as in the case where oxidation occurs after the formation of the source and drain regions, the length of the gate will be reduced, and the channel length will be variable. Also, in either case the surfaces of the source and drain regions are unavoidably displaced below the surface of the channel.
  • Another prior art technique for providing the above-described offset is to over-etch the gate electrode during patterning to form an overhanging photoresist layer above the gate electrode.
  • the overhanging photoresist layer is then used, directly or indirectly, to mask the formation of the source and drain regions.
  • this technique has the disadvantage in that the extent of the over-etching of the gate electrode is difficult to control, and the gate electrode acquires undesirable nonvertical sidewalls. Therefore, a need also exists for a method for manufacturing an IGFET which provides an offset between the gate electrode and the mask for forming the source and drain regions but which does not require oxidation or over-etching of the gate electrode.
  • the gate electrodes of the transistor are provided by a layer of polycrystalline silicon (polysilicon) .
  • the polysilicon layer also provides a first level of interconnection for the transistors and other components of the device.
  • a second level of interconnection is typically provided by a layer of an appropriate metal. Since the sheet resistance of even a heavily doped polysilicon layer is typically several orders of magnitude greater than that of the metal layer, it is desirable, for the purpose of increasing device speed, to reduce the sheet resistance of the polysilicon layer.
  • a known technique for reducing the sheet resistance of the polysilicon layer is to form a layer of an appropriate metal silicide, such as tantalum silicide, on a surface of the polysilicon layer. In the prior art, the silicide layer is formed over the entire polysilicon layer prior to patterning. However , in some - 5 -
  • metal silicide layers are also required as contact layers for the source and drain regions. In those instances, it is desirable from the standpoint of reducing manufacturing cost to form the silicide layers for the polysilicon layer and the source and drain regions in the same processing step. Therefore, a need exists for a method for manufacturing an IGFET device which forms those silicide layers in a single processing step.
  • the proble of providing suitable impurity regions is solved in a method of manufacturing a semiconductor device as described above characterized in that there are included the steps of forming a source layer of an appropriate material covering at least the first region the source layer containing a suitable dopant impurity of a second conductivity type; heating the source layer at an appropriate temperature in the presence of an appropriate reactant to cause a reaction which consumes the source layer at a rate exceeding the rate at which the impurity diffuses into the body, the reaction producing a reaction product and the impurity having a source-layer-material/reaction-product segregation coefficient significantly greater than unity; and forming electrical connections to selected ones of the first regions in each selected area.
  • FIGS. 1 through 3 are respectively schematic cross-sectional views illustrating successive fabrication steps in the manufacture of an IGFET device according to alternative embodiments of the present invention.
  • FIGS. 1 through 3 there are shown schematic cross-sectional views representing a portion of a partially completed IGFET device 10 illustrating successive fabrication steps in the manufacture of the device according to alternative embodiments of the present invention.
  • the same reference numerals are used throughout FIGS. 1 through 3 to denote like parts or regions of the device.
  • a 6-8 ⁇ -cm p-type (boron doped) single crystalline silicon body 11 is first prepared.
  • the body may, for example, be a portion of a substrate wafer or a portion of an epitaxial layer grown on a substrate wafer.
  • Layer 12 will also be referred to as the field oxide layer.
  • the field oxide layer is removed from at least one selected area 14 of the surface in which a transistor is to be formed (step 2) . There will typically be many such transistor areas in a device such as an integrated circuit.
  • the field oxide is etched by reactive sputter etching (RSE) in CHF ⁇ - H3 to produce nearly vertical sidewalls 15 at the boundaries of the transistor area.
  • RSE reactive sputter etching
  • a silicon dioxide layer 16, approximately 250 Angstroms thick, is then thermally grown in each selected area (step 3) .
  • Layer 16 will also be referred to as the gate oxide layer.
  • the present embodiment of the invention uses RSE of a nonselectively grown field oxide layer followed by a subsequent thermal oxidation to provide a gate oxide layer in each transistor area and a field oxide layer outside of the transistor areas
  • other techniques such as the one known as selective oxidation, may also be used to provide similar oxide patterns.
  • CVD chemical vapor deposition
  • a metallic silicide layer is deposited on the polysilicon layer 17. This is not shown in the drawing.
  • the polysilicon layer and any overlying silicide is patterned by known lithographic and anisotropic etching techniques to define a gate electrode 18 in each transistor area and interconnection paths (not shown) outside of the transistor areas.
  • the polysilicon layer is etched by RSE in Cl 2 to provide gate electrodes and interconnection paths with nearly vertical sidewalls 40.
  • Each gate electrode 18 is formed in the shape of a strip extending across the transistor area 14 and covering a central portion * thereof.
  • the gate oxide layer in each transistor area is partially removed to expose a first and a second portion 19 and 20 thereof in which the source and drain regions are to be formed.
  • the gate oxide removal is masked by the gate electrode. Therefore, the remaining gate oxide 16 under the gate electrode also has substantially the same shape as the gate electrode.
  • the gate oxide is partially removed by RSE in CHF3 + NH3 (step 6A) . It is advantageous to perform the RSE at a relatively low power (e.g., less than 400 Watts) to minimize polymer deposition on the first and second portions. Such polymer deposition can increase the contact resistances of the source and drain regions which are subsequently formed in those portions.
  • the uncovered gate oxide is removed by sputtering with oxygen ions at a power of approximately 500 Watts for approximately 30 minutes (step 6B) .
  • the sputtering of the gate oxide causes regions of silicon dioxide 21 to be deposited by backsputte ing on the sidewalls of the gate electrode and the field oxide layer.
  • the exposed first and second portions of surface 19 and 20 are preferably cleaned in a
  • a layer of silicon dioxide 22 approximately 700 Angstroms thick is formed to cover substantially the entire surface of the body (step 5 ) .
  • Oxide layer 22 is advantageously formed by CVD from a tetraethyl orthosilicate (TEOS) source.
  • TEOS tetraethyl orthosilicate
  • the RSE should be performed at low power (e.g., less than 400 Watts) to avoid excessive polymer deposition.
  • the oxide regions 42 which remain on the sidewalls of the gate electrode provide offsets between the edges of the gate electrode and the mask for the source and drain regions. It will be noted that in order to use anisotropic etching to provide the offset oxide regions 42, the gate electrode 18 must be formed with substantially vertical sidewalls.
  • the exposed portions are cleaned in a 100:1 solution of HF and a source layer 23 of polysilicon, approximately 500 Angstroms thick, is formed by CVD over the entire surface of the body (step 7) .
  • the source layer is doped by ion implantation with arsenic to a concentration of approximately 1 x 10 21 cm----'.
  • deposition of the source layer or conventional diffusion after deposition may be substituted for the ion implantation.
  • the energy of the implant must be such that the ions do not penetrate through the source layer.
  • An energy of 30 KeV was found to be satisfactory for implanting a 500 Angstrom thick polysilicon layer with arsenic. No annealing of the source layer is necessary after the implant.
  • the composite structure 10 is then heated at a temperature of approximately 900 degrees C in the presence of steam (water vapor) to effect oxidation of the polysilicon source layer (step 8) .
  • the source layer is permitted to be completely consumed by oxidation in approximately 20 minutes.
  • the arsenic in the source layer diffuses into the silicon body to form source and drain regions 24 and 25 which extend approximately 400 Angstroms below the surface of the body.
  • the oxidation time may vary depending on the method of doping. For example, under the same conditions complete oxidation of an in situ doped source layer of the same thickness requires approximately 40 minutes.
  • the oxidation of the source layer produces a layer of silicon dioxide 26 which is in contact with the source and drain regions upon completion of the oxidation.
  • Silicon dioxide has a tendency to reject arsenic, which preferentially segregates in the unoxidized portion of the polysilicon.
  • the ratio of the equilibrium concentration of an impurity in the silicon to that in the silicon dioxide is denoted by the term silicon/silicon-dioxide segregation coefficient and is defined as
  • arsenic has a silicon/silicon-dioxide segregation coefficient of approximately 800, nearly all of the arsenic
  • the oxidation rate of the polysilicon layer at 900 degrees C in steam is greater than the rate at which arsenic diffuses in the polysilicon layer and the body at that temperature, there is an accumulation of arsenic at the silicon-dioxide/silicon interface which increases with oxidation time. To a lesser extent, there is also an accumulation of arsenic at the polysilicon/single-crystal-silicon interface due to grain boundary diffusion and segregation of the arsenic. After the polysilicon layer is completely oxidized, the arsenic concentrations at the surfaces of the source and drain regions are nearly twice the solid solubility of arsenic in silicon at 900 degrees C.
  • the oxidation of the arsenic doped polysilicon source layer provides extremely shallow source and drain regions having considerably higher surface concentrations of arsenic than that which can be provided by conventional diffusion.
  • Steam oxidation of the polysilicon source layer may also be performed at other temperatures, advantageously in the range of 800 to 950 degrees C.
  • the source layer does not oxidize uniformly. Owing to the negligibly small diffusivity of arsenic in silicon dioxide as compared with that in silicon, the accumulation of arsenic at the silicon-dioxide/silicon interface is greater in the regions of the polysilicon layer above the field oxide layer 12 than in the regions above the exposed areas of the silicon body 19 and 20. Since the oxidation rate of silicon decreases as the arsenic concentration therein increases, it is necessary to "over-oxidize" the regions of the source layer above the exposed areas and consume approximately - 11
  • the source and drain regions 24 and 25 After oxidation of the layer, the source and drain regions 24 and 25 have relatively high sheet resistances of approximately 140 ohms per square, owing to 0 a significant portion of the arsenic impurities in those regions not occupying proper substitutional lattice sites.
  • the oxidation of the source layer causes relatively little lattice damage in those regions. Therefore, a relatively short annealing treatment of 5 approximately 30 minutes at approximately 950 degrees C in nitrogen is used to activate substantially all the arsenic in the source and drain regions. A separate annealing step is not required if subsequent processing steps include heat treatments sufficient for activating the arsenic. 0 Turning now to FIG.
  • the silicon dioxide layer resulting from the oxidation of the source layer is anisotropically etched with RSE in CHF3 + NH3 to expose surface portions 27 and 28 of the source and drain areas 24 and 25, respectively (step 9) . Also exposed by the 5 anisotropic etching is the top surface 29 of the gate electrode 18 in each transistor area and the top surfaces of the -lysilicon interconnection paths (not shown) .
  • a layer o cobalt approximately 200 Angstroms thick is formed by conv-: .itional sputtering techniques over the entire 0 surface of the body (step 10) .
  • the composite structure 10 is then heated at approximately 450 degrees C for approximately 90 minutes to initiate a sintering reaction between the cobalt layer and the silicon and polysilicon surfaces in contact therewith.
  • the unreacted cobalt is 5 then removed by etching in a 5:3:1:1 volume mixture of
  • Each cobalt silicide layer is approximately 700 Angstroms thick.
  • the sintering reaction also produces cobalt silicide layers over the polysilicon interconnection paths (not shown) .
  • the contact silicide layers for 0 the source and drain regions and the resistance lowering silicide layers for the polysilicon gate electrodes and interconnection paths are formed in the same processing step. It will be noted that the simultaneous formation of the silicide layers is made possible by the formation of 5 the silicon-dioxide layer 34 on the sidewalls of the gate electrodes and on the polysilicon interconnection paths (not shown) by the oxidation of the source layer and the anisotropic etching of the resulting silicon dioxide layer.
  • the combined heating of the annealing treatment 0 and the sintering of the cobalt causes the source and drain regions 24 and 25 to diffuse to a depth of approximately 1000 Angstroms and acquire sheet resistances of less than 7 ohms per square. These regions also diffuse laterally by approximately 700 Angstroms causing the gate to overlap 5 these regions.
  • the overlap is virtually eliminated in those embodiments where offset oxide regions of at least 700 Angstroms in thickness are formed on the sidewalls of the gate electrode by one of the above-described techniques prior to the deposition of the source layer.
  • the overlap between the gate electrode and the source or drain region is less than the extent of the lateral diffusion of the source and drain regions if the source layer is doped by ion implantation.
  • the energy of the implant is adjusted 5 so that the ions do not penetrate the thickness of the source layer, the vertical regions of the source layer adjacent to the sidewalls of the gate electrode are not implanted. Consequently, the diffusion of dopants from the source layer is offset from the edges of the gate electrode.
  • successive layers of undoped and phosphorus doped silicon dioxide glass 35 and 43, respectively, are deposited by CVD at approximately 630 degrees C from a TEOS and phosphine source.
  • the phosphorus doped glass layer is planarized by a known plasma technique, and contact windows 36 and 37 to selected source and drain contact layers 31 and 32, respectively, are opened by conventional lithography and anisotropic RSE with CHF3 (step 12) .
  • contact windows to selected polysilicon interconnection paths are also formed.
  • a layer of aluminum 38 is then formed by a conventional deposition technique and patterned to form metal contacts to the selected source and drain regions and polysilicon interconnection paths and to form metal and interconnection paths.
  • the aluminum layer is patterned hy conventional lithography and anisotropic etching with RSE in BCI3 + Cl 2 (step 13) .
  • arsenic for forming the source and drain regions by oxidation of an arsenic doped polysilicon source layer
  • other suitable species of impurities as well as other source-layer materials may be substituted.
  • other donor impurities for silicon such as phosphorus and antimony, have silicon/silicon-dioxide segregation coefficients which are significantly greater than unity and may therefore be substituted for arsenic for forming N-type source and drain regions in silicon.
  • arsenic has the advantages of a relatively high segregation coefficient and a relatively low diffusivity. For the formation of extremely shallow source and drain regions having high surface concentrations, it is advantageous to select an impurity which has the highest segregation coefficient and the
  • the depth and surface concentration of the source and drain regions formed by oxidation of the source layer is a function of the thickness and impurity concentration of the source layer and the rate of oxidation.
  • the conditions of the oxidation i.e., temperature and ambient, should be selected to provide an oxidation rate which exceeds the rate at which the impurities diffuse in the silicon body at the oxidation temperature and which provide for complete oxidation of the source layer in a time not longer than that required for the impurity in the source layer to diffuse into the body to form source and drain regions of desired depths.
  • the device is to be subjected to further heating treatments after oxidation, such as annealing or silicide formation, the extent of further diffusion of the source and drain regions during such heating treatments should be taken into account.
  • Steam is advantageously used over other oxidizing ambients for silicon, since a steam ambient provides a faster oxidation rate at a given temperature.
  • the present invention provides particular advantages for the formation of IGFETs with extremely shallow source and drain regions, it is also applicable to the formation of IGFETs with deeper source and drain regions by making appropriate changes in the thickness of the source layer and the conditions of oxidation.
  • ion implantation is used to dope the source layer, it may be advantageous, from the standpoint of obtaining shallower source and drain regions to implant only a surface portion of the source layer adjacent to the target surface.
  • the implanted impurity must first diffuse through the unimplanted portion of the source layer before entering the bulk region. Therefore, for a given - 15 -
  • the partially completed device is heated in an oxidizing ambient to cause oxidation of the source layer
  • another appropriate reactant may be substituted to cause another reaction that would consume the source layer at a rate exceeding the rate 0 at which the impurity in the source layer diffuses in the body and that would provide a reaction product in which the source-layer-material/reaction-product segregation coefficient is signif cantly greater than unity.
  • a polysilicon source layer doped with boron may be 5 heated at an appropriate temperature in the presence of platinum to cause a sintering reaction which consumes the source layer at a rate exceeding the rate at which boron diffuses in silicon.
  • the reaction replaces the polysilicon layer with a layer of platinum silicide, and boron has a 0 platinum-silicide/silicon segregation coefficient which is significantly greater than unity.
  • the platinum may be deposited in a layer over the polysilicon layer or may be sputter deposited simultaneously with the deposition of the polysilicon layer. 5
  • the need may arise in practice for relatively thin silicide layers overlying the source and drain regions and a relatively thick silicide layer overlying the polysilicon gate. In accordance with the procedures described herein, this can conveniently be achieved in at least two different ways. First, a relatively thick layer of a silicide may be formed on top of the polysilicon layer and then patterned with the polysilicon to form the gate structure.
  • a relatively thick layer of a silicide may be selectively formed on the polysilicon gate.
  • the coped polysilicon may then be deposited and oxidized over the silicide-polysilicon structure. Further processing is then carried out as described in detail above.
  • the source layer may be of a single crystal material, such as an epitaxially grown material, instead of a polycrystalline material, and the source layer material may be different from that of the body.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Procédé de fabrication d'un dispositif à IGFET permettant d'obtenir des IGFETs présentant des régions de source (24) et de drain (25) de profondeur extrêmement faible ainsi que des capacitances réduites de chevauchement entre la porte et la source et le drain. Dans le cas de dispositif MOS au silicium, le procédé permet également de former des couches de siliciure métallique (33) sur des électrodes de porte de polysilicium (18), sur les chemins d'interconnexion et sur les régions de source et de drain pendant la même étape de fabrication. Des régions de source et de drain sont formées par oxydation d'une couche de source de polysicilicum (17) dopée à l'arsenic formée de manière à être en contact avec les zones de la surface du silicium où ces régions doivent être formées. L'épaisseur de la couche de source et les conditions d'oxydation sont telles que la vitesse d'oxydation de la couche de source dépasse la vitesse à laquelle l'arsenic se diffuse dans le silicium à la température d'oxydation et que pendant le temps d'oxydation l'arsenic dans la couche de source se diffuse dans le silicium pour former des régions de source et de drain d'une profondeur extrêmement réduite.Method for manufacturing an IGFET device making it possible to obtain IGFETs having source (24) and drain (25) regions of extremely shallow depth as well as reduced capacitances of overlap between the door and the source and the drain. In the case of a silicon MOS device, the method also makes it possible to form layers of metallic silicide (33) on polysilicon gate electrodes (18), on the interconnection paths and on the source and drain regions during the same manufacturing step. Source and drain regions are formed by oxidation of an arsenic-doped polysicilicum source layer (17) formed so as to be in contact with the areas of the silicon surface where these regions are to be formed. The thickness of the source layer and the oxidation conditions are such that the oxidation rate of the source layer exceeds the speed at which arsenic diffuses into silicon at the oxidation temperature and that during the oxidation time arsenic in the source layer diffuses into silicon to form source and drain regions of extremely reduced depth.

Description

- 1 -
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
This invention relates to a method for manufacturing a semiconductor device comprising the steps of preparing a se iconductive body of a first conductivity type and lightly doped; forming on a surface of the body a relatively thick insulating layer covering the surface except for one or more selected areas thereof; forming a relatively thin insulating layer covering a portion of each selected area and leaving exposed a first region therein; and forming a first conducting layer in each selected area overlying the relatively thin insulating layer therein.
In the manufacture of insulated-gate field-effect transistor (hereinafter referred to as IGFET) devices, such as integrated circuits, it is generally desirable to reduce the conduction channel lengths of the IGFETs for the purpose of increasing the packing density and operating speed of the device. It is also generally desirable, from the standpoint of increasing device speed, to reduce the gate to source and drain overlap capacitances of the IGFETs and to provide the device with lower resistance interconnections. Recent advances in lithographic and etching techniques have made it possible to form IGFETs having channel lengths of less than 1 μm. However, in order to avoid undesirable short channel effects, such as threshold voltage falloff, in such submicron channel length IGFETs, the source and drain regions of the IGFETs must be made extremely shallow. For example, in a silicon N-channel metal-oxide-semiconductor (MOS) transistor having an effective channel length of 0.5 yiti, a gate oxide thickness of 250 Angstroms and a net channel doping
-I f- _-D concentration of 4 x 10"**° cm , short channel effects are substantially avoided if the depths of the source and drain regions extend less than 1000 Angstroms below the surface of the channel. Furthermore, the sheet resistance of the - 2 -
source and drain regions of such a transistor must be relatively low (e.g., less than 70 ohms per square) so as not to reduce the current conduction capability of the transistor. Therefore, the fabrication of submicron channel length IGFETs requires the formation of source and drain regions which are extremely shallow and which have low sheet resistances.
In the prior art, source and drain regions of IGFETs are most frequently formed by either conventional diffusion or by ion implantations. In the case of conventional diffusion the source and drain regions are formed by diffusing an appropriate dopant impurity into selected areas of a semiconductor surface from an appropriate gas dopant source or from a predeposition source such as a doped semiconductor oxide layer or a doped polycrystalline semiconductor layer in contact with the surface. The impurity is then thermally driven to a desired depth below the surface. However, because the rate of transport of the dopant impurity into the surface by conventional diffusion is generally limited by the solid solubility of the impurity at the diffusion temperature, conventional diffusion followed later by a standard annealing step has the disadvantage of ordinarily not being able to provide an extremely shallow diffused region with a sufficiently high impurity level to provide the region with a low sheet resistance.
In the case of ion implantation, the source and drain regions are formed by bombarding selected areas of the semiconductor surface with an energetic beam of an appropriate ionized dopant impurity. Although ion implantation can provide extremely shallow impurity regions having very high impurity levels, such regions tend to have high sheet resistances owing to lattice damage in the implanted region caused by the ion implantation. Such lattice damage ordinarily results in a significant portion of the dopant impurity not being in proper substitutional lattice sites and a lowering of the carrier mobility in the - 3 -
implanted region. Consequently, ion implantation has the disadvantage in that a post-implantation annealing treatment for repairing the lattice damage is ordinarily required to lower the sheet resistance of an implanted region. Such an annealing treatment' ends to cause the region to diffuse to an excessive depth. For that reason, ion implantation cannot ordinarily be used to provide low sheet resistance source and drain regions of less than 2000 Angstroms in depth. Therefore, a need exists for a method for manufacturing IGFET devices which provides transistors having extremely shallow source and drain regions of low sheet resistance.
Presently, MOS transistors are preferably fabricated by a* self-aligned gate technology in which a patterned gate electrode serves as a diffusion or implantation mask for the formation of the source and drain regions. In such transistors, the gate to source and drain overlap capacitances arise primarily from the lateral diffusion of the source and drain regions under the gate electrode. Since the extent of lateral diffusion of the source or drain region is proportional to the depth of such a region, using shallower source and drain regions generally contributes to reducing the overlap capacitances. However, even in a self-aligned gate MOS technology, it is generally desirable to achieve further reductions in the overlap capacitances. Such reductions are preferably achieved by providing appropriate offsets between the edges of the gate electrode and the masks for the source and drain regions. A prior art technique for providing such offsets is to reduce the width of the gate electrode by oxidation after the formation of the source and drain regions. However, this technique has the disadvantage in that the thermal treatment required for oxidizing the gate electrode drives the source and drain regions to excessive depths.
Moreover, it is known that the gate electrode can be oxidized before the implant. But in that case, as well as in the case where oxidation occurs after the formation of the source and drain regions, the length of the gate will be reduced, and the channel length will be variable. Also, in either case the surfaces of the source and drain regions are unavoidably displaced below the surface of the channel.
Another prior art technique for providing the above-described offset is to over-etch the gate electrode during patterning to form an overhanging photoresist layer above the gate electrode. The overhanging photoresist layer is then used, directly or indirectly, to mask the formation of the source and drain regions. However, this technique has the disadvantage in that the extent of the over-etching of the gate electrode is difficult to control, and the gate electrode acquires undesirable nonvertical sidewalls. Therefore, a need also exists for a method for manufacturing an IGFET which provides an offset between the gate electrode and the mask for forming the source and drain regions but which does not require oxidation or over-etching of the gate electrode.
In a typical self-aligned gate MOS technology, the gate electrodes of the transistor are provided by a layer of polycrystalline silicon (polysilicon) . The polysilicon layer also provides a first level of interconnection for the transistors and other components of the device. A second level of interconnection is typically provided by a layer of an appropriate metal. Since the sheet resistance of even a heavily doped polysilicon layer is typically several orders of magnitude greater than that of the metal layer, it is desirable, for the purpose of increasing device speed, to reduce the sheet resistance of the polysilicon layer. A known technique for reducing the sheet resistance of the polysilicon layer is to form a layer of an appropriate metal silicide, such as tantalum silicide, on a surface of the polysilicon layer. In the prior art, the silicide layer is formed over the entire polysilicon layer prior to patterning. However , in some - 5 -
instances metal silicide layers are also required as contact layers for the source and drain regions. In those instances, it is desirable from the standpoint of reducing manufacturing cost to form the silicide layers for the polysilicon layer and the source and drain regions in the same processing step. Therefore, a need exists for a method for manufacturing an IGFET device which forms those silicide layers in a single processing step.
In some cases of practical importance, a need also exists for a relatively thin silicide layer for the source and drain regions (thereby establishing a prescribed low resistivity while maintaining shallow junctions) which layer is compatible with a relatively thick silicide layer (even lower resistivity) patterned to form part of the gate electrode.
In accordance with the invention, the proble of providing suitable impurity regions is solved in a method of manufacturing a semiconductor device as described above characterized in that there are included the steps of forming a source layer of an appropriate material covering at least the first region the source layer containing a suitable dopant impurity of a second conductivity type; heating the source layer at an appropriate temperature in the presence of an appropriate reactant to cause a reaction which consumes the source layer at a rate exceeding the rate at which the impurity diffuses into the body, the reaction producing a reaction product and the impurity having a source-layer-material/reaction-product segregation coefficient significantly greater than unity; and forming electrical connections to selected ones of the first regions in each selected area. In the drawing:
FIGS. 1 through 3 are respectively schematic cross-sectional views illustrating successive fabrication steps in the manufacture of an IGFET device according to alternative embodiments of the present invention. Referring now to FIGS. 1 through 3, there are shown schematic cross-sectional views representing a portion of a partially completed IGFET device 10 illustrating successive fabrication steps in the manufacture of the device according to alternative embodiments of the present invention. The same reference numerals are used throughout FIGS. 1 through 3 to denote like parts or regions of the device. As shown in FIG. 1, a 6-8 β-cm p-type (boron doped) single crystalline silicon body 11 is first prepared. The body may, for example, be a portion of a substrate wafer or a portion of an epitaxial layer grown on a substrate wafer. A silicon dioxide layer 12, approximately 3500 Angstroms thick, is thermally grown on a surface 13 of the body (step 1) . Layer 12 will also be referred to as the field oxide layer. Using known lithographic and anisotropic etching techniques, the field oxide layer is removed from at least one selected area 14 of the surface in which a transistor is to be formed (step 2) . There will typically be many such transistor areas in a device such as an integrated circuit. The field oxide is etched by reactive sputter etching (RSE) in CHF^ - H3 to produce nearly vertical sidewalls 15 at the boundaries of the transistor area. A silicon dioxide layer 16, approximately 250 Angstroms thick, is then thermally grown in each selected area (step 3) . Layer 16 will also be referred to as the gate oxide layer. Although the present embodiment of the invention uses RSE of a nonselectively grown field oxide layer followed by a subsequent thermal oxidation to provide a gate oxide layer in each transistor area and a field oxide layer outside of the transistor areas, other techniques, such as the one known as selective oxidation, may also be used to provide similar oxide patterns.
A layer of polysilicon 17, approximately 3500 Angstroms thick, is formed by conventional chemical vapor deposition (CVD) over the entire surface of the body and doped with phosphorus to achieve a sheet resistance of approximately 30 ohms per square (step 4) . (In some cases of practical importance, a metallic silicide layer is deposited on the polysilicon layer 17. This is not shown in the drawing.) The polysilicon layer and any overlying silicide is patterned by known lithographic and anisotropic etching techniques to define a gate electrode 18 in each transistor area and interconnection paths (not shown) outside of the transistor areas. The polysilicon layer is etched by RSE in Cl2 to provide gate electrodes and interconnection paths with nearly vertical sidewalls 40. Each gate electrode 18 is formed in the shape of a strip extending across the transistor area 14 and covering a central portion* thereof.
Turning now to FIG. 2, after patterning of the polysilicon layer, the gate oxide layer in each transistor area is partially removed to expose a first and a second portion 19 and 20 thereof in which the source and drain regions are to be formed. The gate oxide removal is masked by the gate electrode. Therefore, the remaining gate oxide 16 under the gate electrode also has substantially the same shape as the gate electrode. In one embodiment, the gate oxide is partially removed by RSE in CHF3 + NH3 (step 6A) . It is advantageous to perform the RSE at a relatively low power (e.g., less than 400 Watts) to minimize polymer deposition on the first and second portions. Such polymer deposition can increase the contact resistances of the source and drain regions which are subsequently formed in those portions.
In another and preferred embodiment, the uncovered gate oxide is removed by sputtering with oxygen ions at a power of approximately 500 Watts for approximately 30 minutes (step 6B) . The sputtering of the gate oxide causes regions of silicon dioxide 21 to be deposited by backsputte ing on the sidewalls of the gate electrode and the field oxide layer. The backsputtered oxide regions 21, which have a thickness in the range of 500 to 1000 Angstroms, provide offsets between the edges of - 8 -
the gate electrode and the mask for the source and drain regions. As discussed above, such offsets are useful for reducing the gate to source and drain overlap capacitances. After the sputtering, the exposed first and second portions of surface 19 and 20 are preferably cleaned in a
100:1 solution of HF for approximately one minute. Such cleaning also removes approximately 100 Angstroms of the backsputtered oxide regions 21.
In still another embodiment, prior to the removal of the gate oxide, a layer of silicon dioxide 22 approximately 700 Angstroms thick is formed to cover substantially the entire surface of the body (step 5 ) . Oxide layer 22 is advantageously formed by CVD from a tetraethyl orthosilicate (TEOS) source. The composite structure 10 is then anisotropically etched with RSE in
CHF3 -t- NH3 to expose a first and a second portion 19 and 20 of each transistor area while leaving oxide regions 42 on the vertical sidewalls of the field oxide and the gate electrode (step 6C) . Once again, the RSE should be performed at low power (e.g., less than 400 Watts) to avoid excessive polymer deposition. The oxide regions 42 which remain on the sidewalls of the gate electrode provide offsets between the edges of the gate electrode and the mask for the source and drain regions. It will be noted that in order to use anisotropic etching to provide the offset oxide regions 42, the gate electrode 18 must be formed with substantially vertical sidewalls.
After removal of the gate oxide over the first and second portions of each selected area, the exposed portions are cleaned in a 100:1 solution of HF and a source layer 23 of polysilicon, approximately 500 Angstroms thick, is formed by CVD over the entire surface of the body (step 7) . The source layer is doped by ion implantation with arsenic to a concentration of approximately 1 x 1021 cm----'. Although the disclosed embo iments use ion implantation to dope the source layer, other methods of doping the source layer, such as in situ coping during - 9 -
deposition of the source layer or conventional diffusion after deposition, may be substituted for the ion implantation. However, if ion implantation is used, the energy of the implant must be such that the ions do not penetrate through the source layer. An energy of 30 KeV was found to be satisfactory for implanting a 500 Angstrom thick polysilicon layer with arsenic. No annealing of the source layer is necessary after the implant.
The composite structure 10 is then heated at a temperature of approximately 900 degrees C in the presence of steam (water vapor) to effect oxidation of the polysilicon source layer (step 8) . The source layer is permitted to be completely consumed by oxidation in approximately 20 minutes. During that time, the arsenic in the source layer diffuses into the silicon body to form source and drain regions 24 and 25 which extend approximately 400 Angstroms below the surface of the body. The oxidation time may vary depending on the method of doping. For example, under the same conditions complete oxidation of an in situ doped source layer of the same thickness requires approximately 40 minutes.
The oxidation of the source layer produces a layer of silicon dioxide 26 which is in contact with the source and drain regions upon completion of the oxidation. Silicon dioxide has a tendency to reject arsenic, which preferentially segregates in the unoxidized portion of the polysilicon. The ratio of the equilibrium concentration of an impurity in the silicon to that in the silicon dioxide is denoted by the term silicon/silicon-dioxide segregation coefficient and is defined as
Equilibrium Concentration of Impurity in Silicon m
Equilibrium Concentration of Impurity in Si02
Since arsenic has a silicon/silicon-dioxide segregation coefficient of approximately 800, nearly all of the arsenic
- 10
in the polysilicon source layer is segregated in the unoxidized portion of the layer during oxidation. Upon completion of the oxidation nearly all of the arsenic in the region of the polysilicon layer above the first and second portions of the transistor area will have been driven into the source and drain regions 24 and 25.
Because the oxidation rate of the polysilicon layer at 900 degrees C in steam is greater than the rate at which arsenic diffuses in the polysilicon layer and the body at that temperature, there is an accumulation of arsenic at the silicon-dioxide/silicon interface which increases with oxidation time. To a lesser extent, there is also an accumulation of arsenic at the polysilicon/single-crystal-silicon interface due to grain boundary diffusion and segregation of the arsenic. After the polysilicon layer is completely oxidized, the arsenic concentrations at the surfaces of the source and drain regions are nearly twice the solid solubility of arsenic in silicon at 900 degrees C. Therefore, the oxidation of the arsenic doped polysilicon source layer provides extremely shallow source and drain regions having considerably higher surface concentrations of arsenic than that which can be provided by conventional diffusion. Steam oxidation of the polysilicon source layer may also be performed at other temperatures, advantageously in the range of 800 to 950 degrees C.
It should be noted that the source layer does not oxidize uniformly. Owing to the negligibly small diffusivity of arsenic in silicon dioxide as compared with that in silicon, the accumulation of arsenic at the silicon-dioxide/silicon interface is greater in the regions of the polysilicon layer above the field oxide layer 12 than in the regions above the exposed areas of the silicon body 19 and 20. Since the oxidation rate of silicon decreases as the arsenic concentration therein increases, it is necessary to "over-oxidize" the regions of the source layer above the exposed areas and consume approximately - 11
200 Angstroms of the body in those areas in order to obtain complete oxidation of the regions of the source layer above the field oxide layer. Over-oxidation may be avoided by forming the source layer to cover only each transistor area 5 or by doping only the region of the source layer above each transistor area.
After oxidation of the layer, the source and drain regions 24 and 25 have relatively high sheet resistances of approximately 140 ohms per square, owing to 0 a significant portion of the arsenic impurities in those regions not occupying proper substitutional lattice sites. However, the oxidation of the source layer causes relatively little lattice damage in those regions. Therefore, a relatively short annealing treatment of 5 approximately 30 minutes at approximately 950 degrees C in nitrogen is used to activate substantially all the arsenic in the source and drain regions. A separate annealing step is not required if subsequent processing steps include heat treatments sufficient for activating the arsenic. 0 Turning now to FIG. 3, the silicon dioxide layer resulting from the oxidation of the source layer is anisotropically etched with RSE in CHF3 + NH3 to expose surface portions 27 and 28 of the source and drain areas 24 and 25, respectively (step 9) . Also exposed by the 5 anisotropic etching is the top surface 29 of the gate electrode 18 in each transistor area and the top surfaces of the -lysilicon interconnection paths (not shown) . A layer o cobalt approximately 200 Angstroms thick is formed by conv-: .itional sputtering techniques over the entire 0 surface of the body (step 10) . The composite structure 10 is then heated at approximately 450 degrees C for approximately 90 minutes to initiate a sintering reaction between the cobalt layer and the silicon and polysilicon surfaces in contact therewith. The unreacted cobalt is 5 then removed by etching in a 5:3:1:1 volume mixture of
C2H4°3' ΗNO3, H3P04 and H2S04. The composite structure is heated again, this time in an oxidizing ambient, at - 12
approximately 900 degrees C for approximately 30 minutes to continue the sintering reaction to produce cobalt disilicide layers 31, 32 and 33 over the source and drain regions and the gate electrode, respectively, in each 5 transistor area.
Each cobalt silicide layer is approximately 700 Angstroms thick. The sintering reaction also produces cobalt silicide layers over the polysilicon interconnection paths (not shown) . Thus, the contact silicide layers for 0 the source and drain regions and the resistance lowering silicide layers for the polysilicon gate electrodes and interconnection paths are formed in the same processing step. It will be noted that the simultaneous formation of the silicide layers is made possible by the formation of 5 the silicon-dioxide layer 34 on the sidewalls of the gate electrodes and on the polysilicon interconnection paths (not shown) by the oxidation of the source layer and the anisotropic etching of the resulting silicon dioxide layer. The combined heating of the annealing treatment 0 and the sintering of the cobalt causes the source and drain regions 24 and 25 to diffuse to a depth of approximately 1000 Angstroms and acquire sheet resistances of less than 7 ohms per square. These regions also diffuse laterally by approximately 700 Angstroms causing the gate to overlap 5 these regions. The overlap is virtually eliminated in those embodiments where offset oxide regions of at least 700 Angstroms in thickness are formed on the sidewalls of the gate electrode by one of the above-described techniques prior to the deposition of the source layer. However, even 0 where no offset oxide layer is used, the overlap between the gate electrode and the source or drain region is less than the extent of the lateral diffusion of the source and drain regions if the source layer is doped by ion implantation. Since the energy of the implant is adjusted 5 so that the ions do not penetrate the thickness of the source layer, the vertical regions of the source layer adjacent to the sidewalls of the gate electrode are not implanted. Consequently, the diffusion of dopants from the source layer is offset from the edges of the gate electrode.
After formation of the silicide layers, successive layers of undoped and phosphorus doped silicon dioxide glass 35 and 43, respectively, are deposited by CVD at approximately 630 degrees C from a TEOS and phosphine source. The phosphorus doped glass layer is planarized by a known plasma technique, and contact windows 36 and 37 to selected source and drain contact layers 31 and 32, respectively, are opened by conventional lithography and anisotropic RSE with CHF3 (step 12) . In the same processing step contact windows to selected polysilicon interconnection paths (not shown) are also formed. A layer of aluminum 38 is then formed by a conventional deposition technique and patterned to form metal contacts to the selected source and drain regions and polysilicon interconnection paths and to form metal and interconnection paths. The aluminum layer is patterned hy conventional lithography and anisotropic etching with RSE in BCI3 + Cl2 (step 13) .
Although the preferred embodiment of the present invention uses arsenic for forming the source and drain regions by oxidation of an arsenic doped polysilicon source layer, it is contemplated that other suitable species of impurities as well as other source-layer materials may be substituted. For example, other donor impurities for silicon, such as phosphorus and antimony, have silicon/silicon-dioxide segregation coefficients which are significantly greater than unity and may therefore be substituted for arsenic for forming N-type source and drain regions in silicon. However, arsenic has the advantages of a relatively high segregation coefficient and a relatively low diffusivity. For the formation of extremely shallow source and drain regions having high surface concentrations, it is advantageous to select an impurity which has the highest segregation coefficient and the
^ EA - 14 -
lowest diffusivity.
Given a particular species of impurities and a particular source-layer material, the depth and surface concentration of the source and drain regions formed by oxidation of the source layer is a function of the thickness and impurity concentration of the source layer and the rate of oxidation. The conditions of the oxidation, i.e., temperature and ambient, should be selected to provide an oxidation rate which exceeds the rate at which the impurities diffuse in the silicon body at the oxidation temperature and which provide for complete oxidation of the source layer in a time not longer than that required for the impurity in the source layer to diffuse into the body to form source and drain regions of desired depths. If the device is to be subjected to further heating treatments after oxidation, such as annealing or silicide formation, the extent of further diffusion of the source and drain regions during such heating treatments should be taken into account. Steam is advantageously used over other oxidizing ambients for silicon, since a steam ambient provides a faster oxidation rate at a given temperature.
Although the present invention provides particular advantages for the formation of IGFETs with extremely shallow source and drain regions, it is also applicable to the formation of IGFETs with deeper source and drain regions by making appropriate changes in the thickness of the source layer and the conditions of oxidation. If ion implantation is used to dope the source layer, it may be advantageous, from the standpoint of obtaining shallower source and drain regions to implant only a surface portion of the source layer adjacent to the target surface. During oxidation of such a nonuniformly implanted source layer, the implanted impurity must first diffuse through the unimplanted portion of the source layer before entering the bulk region. Therefore, for a given - 15 -
oxidation rate the use of such a nonuniformly implanted source layer would provide shallower source and drain regions than a uniformly doped source layer.
Although in the preferred embodiment of the 5 present invention, the partially completed device is heated in an oxidizing ambient to cause oxidation of the source layer, it is also contemplated that another appropriate reactant may be substituted to cause another reaction that would consume the source layer at a rate exceeding the rate 0 at which the impurity in the source layer diffuses in the body and that would provide a reaction product in which the source-layer-material/reaction-product segregation coefficient is signif cantly greater than unity. For example, a polysilicon source layer doped with boron may be 5 heated at an appropriate temperature in the presence of platinum to cause a sintering reaction which consumes the source layer at a rate exceeding the rate at which boron diffuses in silicon. The reaction replaces the polysilicon layer with a layer of platinum silicide, and boron has a 0 platinum-silicide/silicon segregation coefficient which is significantly greater than unity. The platinum may be deposited in a layer over the polysilicon layer or may be sputter deposited simultaneously with the deposition of the polysilicon layer. 5 As stated earlier above, the need may arise in practice for relatively thin silicide layers overlying the source and drain regions and a relatively thick silicide layer overlying the polysilicon gate. In accordance with the procedures described herein, this can conveniently be achieved in at least two different ways. First, a relatively thick layer of a silicide may be formed on top of the polysilicon layer and then patterned with the polysilicon to form the gate structure. Or, after defining the polysilicon gate, a relatively thick layer of a silicide may be selectively formed on the polysilicon gate. In either case, the coped polysilicon may then be deposited and oxidized over the silicide-polysilicon structure. Further processing is then carried out as described in detail above.
It will be understood by those skilled in the art that the foregoing and other modifications and substitutions may be made to the described embodiment. For example, the source layer may be of a single crystal material, such as an epitaxially grown material, instead of a polycrystalline material, and the source layer material may be different from that of the body.

Claims

Claims
1. A method for manufacturing a semiconductor device comprising the steps of: preparing a εemiconductive body (11) of a first conductivity type and lightly doped; forming on a surface of the body a relatively thick insulating layer (12) covering the surface except for one or more selected areas (14) thereof; forming a relatively thin insulating layer (16) covering a portion of each selected area and leaving exposed a first region (19) therein; and forming a first conducting layer (18) in each selected area overlying the relatively thin insulating layer therein; CHARACTERIZED IN THAT there are included the steps of: forming a source layer (23) of an appropriate material covering at least the first region the source layer containing a suitable dopant impurity of a second conductivity type; heating the source layer at an appropriate temperature in the presence of an appropriate reactant to cause a reaction which consumes the source layer at a rate exceeding the rate at which the impurity diffuses into the body, the reaction producing a reaction product and the impurity having a source-layer-material/reaction-product segregation coefficient significantly greater than unity; and forming electrical connections (38) to selected ones of the first regions in each selected area.
2. A method as recited in claim 1
FURTHER CHARACTERIZED IN THAT the reactant is an appropriate oxidizing ambient, the reaction is oxidation, the reaction product is an oxide of the source layer material and the source-layer- material/reaction-product segregation coefficient is the source-layer-materia1/source-layer-material-oxi e segregation coefficient. - 18
3. A method as recited in claim 2 FURTHER CHARACTERIZED IN THAT the thin insulating layer (16) and first conducting layer (18) form a strip covering a central 5 portion of each selected area to leave exposed a second region (20) opposite the first region (19), the thickness of the source layer, the impurity in the source layer, the concentration thereof, the temperature and ambient of the oxidation are selected to provide source and drain regions 10 (24, 25) of the second conductivity type having desired depths and surface concentrations in the first and second regions of each selected area.
4. A method as recited in claim 3 wherein the body is single crystalline silicon,
15 FURTHER CHARACTERIZED IN THAT the source layer is polycrystalline silicon, the source-layer-material oxide is silicon dioxide and the source-1ayer-material/εource-layer-material-oxide segregation coefficient is the silicon/silicon-dioxide
20 segregation coefficient.
5. A method as recited in claim 4 wherein the strip-like insulating layer and the strip-like first conducting layer are formed by thermally growing a relatively thin silicon dioxide layer in each selected
25 area, depositing an appropriately doped polysilicon layer covering substantially the entire surface of the body and overlying the relatively thin silicon dioxide layer in each selected area, patterning the polysilicon layer into one or more strip-like layers each covering a central portion of a
30 respective selected area and one or more interconnection paths outside of the selected areas, removing portions of the relatively thin silicon dioxide layer not covered by the strip-like polysilicon layer in each selected area, and
35 FURTHER CHARACTERIZED IN THAT prior to forming the source layer, offset oxide regions (21, 42) are formed on the sidewalls of the strip-like polysilicon layer in each selected area.
6. A method as recited in claim 5 FURTHER CHARACTERIZED IN THAT the portions of the relatively thin silicon dioxide layer not covered by a strip-like polysilicon layer in each selected area are removed by sputtering with appropriate ions under conditions which cause silicon dioxide to be backsputtered onto the sidewalls of the strip-like polysilicon layer, and the offset oxide regions (21) are formed by such backsputtering.
7. A method as recited in claim 5 FURTHER CHARACTERIZED IN THAT each strip-like polysilicon layer is patterned to have substantially vertical sidewalls, a relatively thin second silicon dioxide layer (22) is formed covering at least each selected area including the strip-like polysilicon layer therein, and the second silicon dioxide layer is partially removed by anisotropic etching leaving portions (42) thereof adjacent the sidewalls of the εtrip- like polysilicon layer in each selected area.
8. A method as recited in claims 4, 6 or 7 FURTHER CHARACTERIZED IN THAT the source layer is formed to cover substantially the entire surface of the body, overlying the strip-like polysilicon layer in each selected area and the polysilicon interconnection paths, the oxidation reaction consumes substantially the entire source layer, the silicon dioxide layer produced by the oxidation reaction is anisotropically etched to expose at least portions of the first and second regions and a surface of each strip-like polysilicon layer and interconnection path, a relatively thin layer (30) of an appropriate metal is formed covering substantially the entire surface of the body, the metal layer and the body are heated to cause a sintering reaction between portions of the metal layer and the exposed portions of the surface of the body and the exposed surface of each strip-like polysilicon layer and interconnection
OM 20 -
path to form metal-silicide layers thereon, the unreacted portions of the metal layer are removed, one or more glass layers (35, 43) covering substantially the entire surface of the body are formed, contact windows in the glass layers are formed to expose portions of selected ones of the metal-silicide layers, a second conducting layer (38) is formed covering substantially the entire surface of the body, and the second conducting layer is patterned to form contacts to the exposed portions of the selected metal- silicide layers and second interconnecting paths.
9. A method as recited in claim 8 FURTHER CHARACTERIZED IN THAT the source layer is formed by chemical vapor deposition of polycrystalline silicon and at least a portion thereof being doped in situ.
10. A method as recited in claim 8 FURTHER CHARACTERIZED IN THAT the source layer is formed by chemical vapor deposition of undoped polycrystalline silicon and doped by conventional diffusion after deposition.
11. A method as recited in claim 8 FURTHER CHARACTERIZED IN THAT the source layer is formed by chemical vapor deposition of undoped polycrystalline silicon and doped by ion implantation after deposition.
12. A method as recited in claim 11 FURTHER CHARACTERIZED IN THAT only a surface portion of the source layer is doped by ion implantation.
EP19830902037 1982-06-01 1983-05-13 Method for manufacturing a semiconductor device. Withdrawn EP0110956A4 (en)

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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS618916A (en) * 1984-06-21 1986-01-16 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Method of forming doped region
US4653173A (en) * 1985-03-04 1987-03-31 Signetics Corporation Method of manufacturing an insulated gate field effect device
IT1197523B (en) * 1986-10-30 1988-11-30 Sgs Microelettronica Spa PROCESS FOR THE MANUFACTURE OF FIELD-EFFECT TRANSISTORS WITH "GATE" ISOLATED WITH JOINTS HAVING EXTREMELY REDUCED DEPTH
EP0606114A1 (en) * 1989-08-11 1994-07-13 Seiko Instruments Inc. Method of producing field effect transistor
EP0505877A2 (en) * 1991-03-27 1992-09-30 Seiko Instruments Inc. Impurity doping method with adsorbed diffusion source
US5959357A (en) * 1998-02-17 1999-09-28 General Electric Company Fet array for operation at different power levels

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2953486A (en) * 1959-06-01 1960-09-20 Bell Telephone Labor Inc Junction formation by thermal oxidation of semiconductive material
US3418180A (en) * 1965-06-14 1968-12-24 Ncr Co p-n junction formation by thermal oxydation
US3617824A (en) * 1965-07-12 1971-11-02 Nippon Electric Co Mos device with a metal-silicide gate
US3664896A (en) * 1969-07-28 1972-05-23 David M Duncan Deposited silicon diffusion sources
US3798752A (en) * 1971-03-11 1974-03-26 Nippon Electric Co Method of producing a silicon gate insulated-gate field effect transistor
US3808060A (en) * 1972-07-05 1974-04-30 Motorola Inc Method of doping semiconductor substrates
US3928095A (en) * 1972-11-08 1975-12-23 Suwa Seikosha Kk Semiconductor device and process for manufacturing same
DE2449688C3 (en) * 1974-10-18 1980-07-10 Siemens Ag, 1000 Berlin Und 8000 Muenchen Method for producing a doped zone of one conductivity type in a semiconductor body
US4182023A (en) * 1977-10-21 1980-01-08 Ncr Corporation Process for minimum overlap silicon gate devices
GB2021861B (en) * 1978-05-26 1982-09-29 Rockwell International Corp Field effect transistors
US4277881A (en) * 1978-05-26 1981-07-14 Rockwell International Corporation Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
DE2964810D1 (en) * 1978-07-29 1983-03-24 Fujitsu Ltd A method of coating side walls of semiconductor devices
US4274892A (en) * 1978-12-14 1981-06-23 Trw Inc. Dopant diffusion method of making semiconductor products
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US4319395A (en) * 1979-06-28 1982-03-16 Motorola, Inc. Method of making self-aligned device
US4355454A (en) * 1979-09-05 1982-10-26 Texas Instruments Incorporated Coating device with As2 -O3 -SiO2
US4389255A (en) * 1980-01-14 1983-06-21 Burroughs Corporation Method of forming buried collector for bipolar transistor in a semiconductor by selective implantation of poly-si followed by oxidation and etch-off
US4356040A (en) * 1980-05-02 1982-10-26 Texas Instruments Incorporated Semiconductor device having improved interlevel conductor insulation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 23, no. 9, February 1981, NEW YORK (US) *
See also references of WO8304342A1 *

Also Published As

Publication number Publication date
EP0110956A4 (en) 1984-07-03
GB8314946D0 (en) 1983-07-06
GB2121235B (en) 1986-03-19
GB2121235A (en) 1983-12-14
CA1198226A (en) 1985-12-17
WO1983004342A1 (en) 1983-12-08

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