EP0104166A1 - Systeme informatise electro-oculographique(ceog) - Google Patents

Systeme informatise electro-oculographique(ceog)

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Publication number
EP0104166A1
EP0104166A1 EP82901258A EP82901258A EP0104166A1 EP 0104166 A1 EP0104166 A1 EP 0104166A1 EP 82901258 A EP82901258 A EP 82901258A EP 82901258 A EP82901258 A EP 82901258A EP 0104166 A1 EP0104166 A1 EP 0104166A1
Authority
EP
European Patent Office
Prior art keywords
output
chair
input
operator
stimuli
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP82901258A
Other languages
German (de)
English (en)
Other versions
EP0104166A4 (fr
Inventor
Robert S. Ledley
Thomas J. Golab
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Georgetown University
Original Assignee
Georgetown University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Georgetown University filed Critical Georgetown University
Publication of EP0104166A1 publication Critical patent/EP0104166A1/fr
Publication of EP0104166A4 publication Critical patent/EP0104166A4/fr
Withdrawn legal-status Critical Current

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Classifications

    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/316—Modalities, i.e. specific diagnostic methods
    • A61B5/369—Electroencephalography [EEG]
    • A61B5/377—Electroencephalography [EEG] using evoked responses
    • A61B5/378—Visual stimuli
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/48—Other medical applications
    • A61B5/4863—Measuring or inducing nystagmus
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/25—Bioelectric electrodes therefor
    • A61B5/276—Protection against electrode failure
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/316—Modalities, i.e. specific diagnostic methods
    • A61B5/369—Electroencephalography [EEG]
    • A61B5/377—Electroencephalography [EEG] using evoked responses
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • A61B5/316—Modalities, i.e. specific diagnostic methods
    • A61B5/398—Electrooculography [EOG], e.g. detecting nystagmus; Electroretinography [ERG]
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7203—Signal processing specially adapted for physiological signals or for diagnostic purposes for noise prevention, reduction or removal
    • A61B5/7207—Signal processing specially adapted for physiological signals or for diagnostic purposes for noise prevention, reduction or removal of noise induced by motion artifacts

Definitions

  • the present invention relates to a computerized electro-oculographic system and, more particularly, an integrated system for automated administration of electro-oculographic tests and visual evoked response tests to a patient, and automated processing of results derived from such tests. Automated administration of the tests is conducted either under the direct control of the test administrator via an operator control section (console), or under the automated control of a programmed computer with indirect control by the test administrator.
  • Automated administration of the tests is conducted either under the direct control of the test administrator via an operator control section (console), or under the automated control of a programmed computer with indirect control by the test administrator.
  • electro-oculographic or electro-nystagmographic techniques have been utilized by physicians to gain useful information about a patient with certain complaints -- notably, complaints of disturbed equilibrium.
  • Such information has typically been gained by observing the patient's eye movements during certain kinds of visual and vestibular stimulation.
  • Such observations provide the only physical findings that support a patient's complaint, and they also assist the physician in defining the anatomic location of the patient's disorder.
  • the physician is often able to distinguish between a peripheral vestibular disorder and one located within the central nervous system, and is sometimes able to lateralize a peripheral disorder, or to further localize a central nervous system disorder.
  • Electro-oculography has long been widely used for research purposes in psychology and ophthalmology. It has gradually acquired its more familiar name, electro-nystagmography, because of its extensive application to the study of nystagmus (although it is used to record other types of eye movements as well).
  • electro-nystagmography ENG owes its existence to the fact that the eye is, in effect, a battery, the cornea being a positive pole, the retina being a negative pole, and the potential difference between the two poles being normally at least one millivolt.
  • This electrical potential creates, in the front of the head, an electrical field that changes its orientation as the eyeballs rotate.
  • These electrical changes can be detected by electrodes placed on the skin of a patient, and, when the changes are amplified and used to drive a writing instrument, a trace of the eye position is obtained.
  • electrodes can be arranged on the skin in a number of ways, but a standard technique for clinical purposes involves placement of two electrodes bitemporally (that is, one on the right temple and the other on the left temple) to monitor horizontal eye position, placement of a second pair of electrodes, one above and the other below one of the eyes, to monitor vertical position of the eyes, and placement of an additional electrode, usually on the forehead, to serve as a ground or reference point.
  • two electrodes bitemporally that is, one on the right temple and the other on the left temple
  • placement of a second pair of electrodes one above and the other below one of the eyes
  • an additional electrode usually on the forehead
  • other arrangements of electrodes can be utilized, as are known in the art (for example, an occipital arrangement).
  • a significant problem in the prior art, relating to the monitoring of eye movements using such electrode arrangements, results from the necessity, or at least desirability, of maintaining a constant relationship between the center position of the eye and a given value of the measured electrical parameter (for example, zero volts).
  • the measured electrical parameter for example, zero volts.
  • sustained use of such electrode arrangements and measuring devices results in the development of an offset voltage. That is, the calibration of the measuring device varies so that a center position of the eye no longer results in a reading of zero volts, but rather results in some finite number of volts (referred to as the offset voltage). This has obvious disadvantages with respect to the accuracy of the eye movement measurements.
  • electro-oculograms representing measurement of both horizontal and vertical eye movements -- and occipital measurements as well -- are recorded with the electrodes fixed to the head of the patient.
  • eye movements and visual responses from the patient can be recorded as the patient undergoes one or more tests.
  • a series of six ocular motor, vestibular and response tests are conducted, as follows:
  • Gaze tests wherein eye movements are recorded as the patient looks straight ahead, to the right, to the left, up and down, both with the eyes open and closed.
  • Optokinetic tests wherein eye movements are recorded as the patient watches vertical stripes moving at various speeds to the right, and then to the left, the test being performed both with the patient stationary while the image revolves, and with the patient revolving while the image is stationary.
  • Visual evoked response tests wherein "vision” is assessed, the integrity of the visual pathways (including the optic nerve, optic chiasm, and posterior visual pathways) being analyzed, and the visual evoked response being recorded between occipital electrodes (positioned contralateral to the eye -- i.e., electrodes on the right/left occipital, and electrodes on the right/left ear lobe), as stimulated by a burst of short, high-intensity light pulses, and a reference (ground) electrode (placed on the forehead of the patient).
  • occipital electrodes positioned contralateral to the eye -- i.e., electrodes on the right/left occipital, and electrodes on the right/left ear lobe
  • a reference (ground) electrode placed on the forehead of the patient.
  • one device might be utilized to perform the saccadic test, followed by a period of time during which a second piece of equipment is actuated in order to perform the tracking test, and so forth for the remaining tests.
  • one group of equipment (light flasher or light scanning equipment) might be utilized for administration of the saccadic and tracking tests, and then a second group of equipment (an optokinetic device in combination with a rotating chair) might be utilized to perform the optokinetic test.
  • a second group of equipment an optokinetic device in combination with a rotating chair
  • data obtained as a result of the above-mentioned tests typically include artifacts caused by electronic noise, eye blinks, random eye movements, poor electrode contact, and so forth.
  • minute voltage changes as little as several microvolts per degree of eye displacement
  • distortion of the statistics is a very real problem.
  • offset voltage phenomenon encountered in electrode measuring arrangements of the type employed with such systems is a major contributor to statistical inaccuracy.
  • SAP Software Program developed to analyze, in an off-line mode of operation, the saccadic eye movements previously recorded.
  • Such systems can be equipped with not only a processor and memory, but also various peripheral units (disk drive, magnetic tape drive, graphics display terminal, and hard copy printer). Whereas such systems display the raw data for visual inspection and allow the user to study the data for possible errors in recording and/or digitization, it is important to note that such systems are nevertheless "off-line” systems whereby data is recorded in one operation and then processed in a second operation (on different equipment) separated by a time lapse there-between.
  • Another type of prior art system is that exemplified by the disclosure of a "Method and Apparatus for Brain Waveform Examination" in U.S. Patent No.
  • That patent discloses a method and apparatus for examining the brain waveform of a subject (for example, by electro-encephalographic (EEG) techniques) by providing a stimuli (such as light), and determining a characteristic of a mathematically determinable point in the brain waveforms of the subject (for example, by means of an EEG amplifier, filter, zero-crossing detector and computer).
  • EEG electro-encephalographic
  • the stimulation of the subject can be controlled or varied via a closed-loop feedback path (between, for example, the computer and the photo-stimulator).
  • the system of the latter patent does not comprise an integrated system capable of automated administration of various test stimuli to a patient via employment of an operator control section (console), does not provide for correction of the "offset voltage" phenomenon, and does not expressly provide for automated processing of resultant test data so as to provide critical information to the attending physician or test administrator in acceptable format and in a very short period of time.
  • a computerized electro-oculographic (CEOG) system and, more particularly, an integrated CEOG system having the capabilities of automated administration of various electro-oculographc (EOG) and visual evoked response (VER) tests to a patient in response to operator selection of such tests, immediate on-line recording and display of test results (raw data), rapid and accurate analysis of such raw data in order to provide critical information to the test administrator in an acceptable form and in a very short period of time, and continuous/automatic data processing and "editing" to delete artifacts (typically, caused by electronic noise, eye blinks, random eye movements, poor electrode contact, etc.).
  • EOG electro-oculographc
  • VER visual evoked response
  • the CEOG system of the present invention basically comprises the following components: a patient system, or test unit, including a rotating chair (for use, for example, in the administration of the optokinetic tests), various visual test stimuli devices (such as, for example, an optokinetic device, flasher, and light source), and respective control units for controlling both the rotating chair and the visual test stimuli devices; various input devices (preamplifier, amplifier, and digitizer) for receiving and providing electrode test data to a computer; a computer (including -- for example -- the usual central processing unit, storage media, display/keyboard and hard-copy printer), and an interface unit between the computer and the aforementioned control units and various input devices for facilitating control of test stimuli administration and input of test data, respectively.
  • a patient system or test unit
  • a rotating chair for use, for example, in the administration of the optokinetic tests
  • various visual test stimuli devices such as, for example, an optokinetic device, flasher, and light source
  • respective control units for controlling both the rotating chair and the visual test stimuli devices
  • the integrated CEOG system of the present invention is capable of automated administration of test stimuli to a patient via the provision of an operator control section (console), by means of which the test administrator can select one of various types of stimuli (in accordance with the particular type of test being administrated), and can as well designate various parameters or characteristics of the desired stimuli.
  • the test administrator can operate the operator control section (console) to cause administration of optokinetic tests.
  • the administrator can, in an automated manner, actuate both the rotatable chair (in terms of commanding rotation of the chair and selecting a rotation speed, number of turns for which the chair is to be rotated, etc.) and the optokinetic device
  • the test administrator can operate the CEOG system of the present invention so as to administer, in an automated manner, the saccadic test or the tracking test (in terms of actuating a flasher device or a light scanner, respectively, and designating the scanning speed, scanning pattern, etc.).
  • electrode test data derived from electrodes attached to the head of the patient are, after amplification and digitization, stored in the system processor, the system having the capability of immediate display of the raw data via any one of various conventional display devices (graphic display terminal, hard-copy printer, etc.).
  • the CEOG system of the present invention is unique in that the adverse effects of the typically encountered offset voltage characterizing such electrode test data (which are initially in the form of input voltage signals) can be compensated for by not only manual techniques, but also automated techniques.
  • the CEOG system of the present invention affords the test administrator with an immediate display of the analog test data signals after preamplification, but before amplification, and further provides the test administrator with means for manually adjusting ampli bomb network reference voltages so as to eliminate the "offset voltage" effect by zero-adjusting the amplifiers to achieve zero-volt readings for non-variation of the patient's eyes from a center position.
  • the CEOG system of the present invention provides the test administrator with the selectable option of automatic zero-adjustment by means of the system processor.
  • the CEOG system of the present invention by means of the system processor -- provides immediate, on-line processing of the input test data so as to permit immediate processing and editing of the input test data to delete artificats typically caused by electronic noise, eye blinks of the patient, random eye movements of the patient, poor electrode contact, etc.
  • the inventive CEOG system is able to detect minute voltage changes (of the order, typically, of several microvolts per degree of eye displacement), to amplify them many thousands of times without distortion, and both to record the processed data in memory (for future use) and to display the processed data on a "real time" basis.
  • the inventive CEOG system is, moreover, able to accomplish the above without accepting extraneous signals from the "outside world," and without generating any extraneous signals internally.
  • the inventive CEOG system is able to provide rapid and accurate analysis of data so as to afford the physician with critical information in acceptable format and in a very short period of time.
  • Such provided data typically includes: amplitude, frequency and duration of fast and slow components of nystagmus; maximum, minimum and mean velocity and amplitude of saccades (sychronized jumps made by the eye in moving from one visual target to another in a short period of time); comparison of saccadic amplitude with light jump amplitude; and measurements of the delay between light jump and eye jump.
  • the latter data results from statistical analyses performed by the inventive CEOG system, followed by graphic display of the information resulting therefrom.
  • CEOG computerized electro-oculographic
  • FIG 1 is a diagram representing a broad overview of the CEOG system of the present invention.
  • Figure 2 is a more detailed block diagram of the CEOG system of the invention.
  • Figure 3A is a diagrammatic representation of the preamplifier network 24 of the CEOG system of Figure 2.
  • Figure 3B is a detailed schematic of the preamplifiers A1, A2,..., A6 of the preamplifier network 24 of Figure 3A.
  • Figure 4A is a diagrammatic representation of the amplifier network 26 of the CEOG system of Figure 2.
  • Figure 4B is a detailed schematic of the amplifiers A11, A12,..., A16 of the amplifier network 26 of Figure 4A.
  • Figure 5 is a diagrammatic representation of biasing circuitry 46' contained in the amplifier network 26 of the CEOG system of Figure 2.
  • Figure 6A is a diagrammatic representation of the ADC portion 56' of the converter stage 56 of the CEOG system of Figure 2.
  • Figure 6B is a detailed schematic of one-half of the converter A/D1 of Figure 6A.
  • Figure 6C is a diagrammatic representation of address decoding logic 190 in converter stage 56 of the CEOG system of Figure 2.
  • Figure 6D is a detailed schematic diagram of further ADC logic circuitry 200 and 250 of the converter stage 56 of the CEOG system of Figure 2.
  • Figure 6E is a detailed schematic diagram of the DAC portion 300 of the converter stage 56 of the CEOG system of Figure 2.
  • Figure 7A is a diagrammatic representation of the motor controller 52 of the CEOG system of Figure 2.
  • Figure 7B is a detailed schematic diagram of the fail-safe circuit 326 of Figure 7A.
  • Figure 7C is a detailed schematic of the chair interlock circuitry 328 of Figure 7A.
  • Figure 7D is a detailed schematic diagram of the dynamic braking relay 322 of Figure 7A.
  • Figure 8 is a diagrammatic representation of the relay panel 20 of the CEOG system of Figure 2.
  • Figure 9A is a diagrammatic representation of the operator control section 450 of the control panel 54 of the CEOG system of Figure 2.
  • FIGS 9B through 9E are detailed schematic diagrams of the control panel 54 of the CEOG system of Figure 2.
  • Figures 10A through 100 are detailed logic block diagrams and circuit schematics of the logic section 62 of the CEOG system of Figure 2.
  • Figures 11A through 11D and 11G are detailed logic block diagrams and circuit schematics of the interface 30 of the CEOG system of Figure 2.
  • Figures 11E, 11F and 11H are timing diagrams relating to write (data out), read (data in) and interrupt operations, respectively, as carried out in the interface 30 of the CEOG system of Figure 2.
  • FIGS 12A and 12B are general flowcharts of the test program and analysis program, repectively, implemented by the processor 34 of the CEOG system of Figure 2. Best Mode for Carrying out the Invention
  • FIG. 1 is a diagram representing a broad overview of the CEOG system of the present invention.
  • the CEOG system of the present invention is for use in performing electro-oculographic (EOG) tests and visual evoked response (VER) tests on a subject 2, the subject being positioned within a patient system or test station 4.
  • EOG electro-oculographic
  • VER visual evoked response
  • an electrode junction box 6 is placed on or near the head of the subject 2, and electrodes 6a through 6i connected to junction box 6 are attached to the skin on the head of the subject 2, so as to permit EOG testing;
  • VER testing two pairs of electrodes are connected to the right occipital/right ear lobe, respectively, of the head of the patient, while a fifth electrode 6i is connected to the patient's forehead, as a ground (or reference) electrode.
  • the test station 4 in which the subject is positioned, comprises a rotating chair 8 for rotating the subject 2 (if appropriate for the particular test being administered), the rotation of the chair being controlled by control unit 10.
  • the test station 4 also comprises: a light spot source 12 for generating a light spot; a set of x-y scanning mirrors 14 for receiving and reflecting the light spot so as to cause the light spot to appear on the generally cylindrical walls 18 of the test station 4, the x-y scanning of the mirrors 14 being controllable so as to cause the light spot to move in the x and/or y directions in accordance with a controlled pattern called for by the paticular test; and an optokinetic device or system (a vertical stripe projector) 16 for causing vertical stripe patterns to be projected onto, and to appear on, the cylindrical walls 18 (also as appropriate for the particular test being administered).
  • a light spot source 12 for generating a light spot
  • a set of x-y scanning mirrors 14 for receiving and reflecting the light spot so as to cause the light spot to appear on the generally
  • the light spot source 12, x-y scanning mirrors 14 and optokinetic device 16 are controlled by a relay panel 20, which is itself controlled by control unit 10.
  • electrodes 6a, 6b and 6e, 6f are connected to detect horizontal eye movement of the right and left eyes, respectively, of the subject 2.
  • electrodes 6c, 6d and 6g, 6h are connected to measure vertical eye movement of the right and left eyes, respectively, of the subject 2.
  • a reference electrode 6i is connected in the area of the temple of the subject 2. It is to be understood that other arrangements of the electrodes 6a through 6i can be used, as called for by the particular test being administered.
  • electrodes 6a through 6i are connected in an arrangement typically utilized in the administration of EOG tests, it is to be understood that further electrodes (not shown) can be connected to the subject 2 in an "occipital lobe" arrangement for the administration of VER tests.
  • Electrodes 6a through 6i are connected to preamplifier network 24, the output of the preamplifier network 24 being provided to filters/amplifiers 26.
  • Filters/amplifiers 26 provide analog outputs on respective channels corresponding to respective electrode measurements, and designated as RH (right horizontal), RV (Right vertical), LH (left horizontal), LV (left vertical), RO (right occipital), and LO (left occipital)!
  • the analog outputs from the filters/amplifiers 26 are provided to digitizer 28, which converts the analog signals to corresponding digital signals.
  • the digital signals from digitizer 28 are provided, via computer interface circuit 30, to a computer, generally designated by reference numeral 32.
  • computer 32 comprises a processor 34, responsive to computer programs 36, for processing the digital input test data (that is, the digital outputs of digitizer 28, provided via computer interface 30), and for providing visual display of the test data on display device 38, hard copy recording of test results on hard copy printing device 40, and permanently recorded test data via a peripheral unit such as floppy disk 42.
  • Computer 32 also comprises a keyboard 44 by which operator control of test administration, processing of test results, and output of test results can be achieved.
  • the CEOG of the present invention also comprises auto-calibration (or biasing) circuitry 46 connected to processor 34, by means of which automatic (processor-controlled) biasing of preamplifier network 24 can be achieved. This is in addition to manual biasing of preamplifier network 24. As will be discussed below in more detail, preamplifier network 24 is manually adjusted, and preferably automatically adjusted as well, for proper preamplifier biasing, so as to compensate for the offset voltages of the electrodes 6a through 6i, thereby maintaining zero adjustment of each electrode when the subject's eyes are directed toward a center position.
  • FIG. 2 is a more detailed block diagram of the CEOG system of the invention. Reference numerals previously employed in Figure 1 to designate various elements of the CEOG system have been maintained in Figure 2, where appropriate.
  • the CEOG system of the present invention generally comprises, with reference to Figure 2, a patient system or test station 4 including a revolving chair 8, upon which the subject 2 is seated -- typically during VER and EOG testing.
  • the chair 8 is rotated by a motor 50, driven by a motor controller 52 connected to a power source (such as 110 volts, 60 Hz.).
  • the motor controller 52 is, in turn, controlled by input control signals received from control panel 54 in control unit 10.
  • various output status signals (to be discussed below) from motor 50
  • Electrode test data derived from electrodes 6a-6i ( Figure 1) attached to the subject 2 ( Figure 2) are provided, via preamplifier network 24 and amplifier network 26, to analog-to-digital converters (ADC) contained in converter stage 56. Digital representations of the electrode test data are derived therein, and are provided as an input DATA to processor 34 via EOG interface 30.
  • a signal monitor scope 58 for displaying, to the operator, the electrode test data signals as generated by preamplifier network 24.
  • the operator of the CEOG system is able to perform manual bias adjustment of preamplifier network 24, by which broad-range biasing of preamplifier network 24 (to compensate for the voltage offset of the electrodes) can be accomplished easily and quickly.
  • a preferred embodiment of the CEOG system includes a selector switch 59, by which the operator can select test data signals from a particular pair of electrodes for display on the scope, thus achieving individual bias adjustment of each respective preamplifier (corresponding to a selected pair of electrodes).
  • processor 34 as a result of processing the received digital test data, DATA -- provides an output BIAS (via interface 30, converter stage 56, and amplifier network 26) to preamplifier network 24.
  • preamplifier network 24 is automatically biased so as to provide continuous/automatic compensation for the offset voltage of the electrodes.
  • Control panel 54 serves as a power distribution/junction box for distributing power throughout the system. Specifically, control panel 54 is powered by a 110 volts, 60 Hz. power input, and provides this A.C. power to power supply 60 which, in response thereto, provides necessary D.C. voltages (+5 v., +12 v., +15 v., -15 v., etc.) to the various elements of the system, as needed. Control panel 54 also receives the various D.C. power inputs from power supply 60, and distributes such D.C. power inputs throughout the system. Thus, as illustrated in Figure 2, power outputs PWR are provided by control panel 54 to preamplifier network 24, amplifier network 26, converter stage 56 and logic section 62, among others.
  • Control panel 54 also serves the function of distributing various logic control signals throughout the system.
  • motor controller 52 -- which controls rotation of the chair -- receives control signals from control panel 54, such control signals originating in logic section 62 and processor 34. More specifically, control panel 54 provides control signals which, as will be seen below, command the motor controller 52 to control the motor 50 in such a manner that the chair 8 will commence revolution on command, will revolve at a given (commanded) speed S, will stop after one turn, after a series of turns, or on command, and will automatically restart revolution in the opposite direction.
  • Control panel 54 also receives and distributes various status signals, such as a chair position indication signal and chair turn information provided by chair 8 via motor 50 motor controller 52. Such status signals are provided to logic section 62 and interface 30.
  • motor 50 and motor controller 52 transmit, to control panel 54, status signals defining tachometer information (relating to the actual speed of the rotating chair 8) , position information relating to the position of the chair 8 relative to a starting position, and turn information relating to the detection of completion of each chair rotation, as detected by a positon detector circuit (not shown in Figure 2 but to be discussed further below).
  • Control panel 54 also operates, in a manner to be described in more detail below, with relay panel 20 so as to control test stimuli, and thus the administration of tests to the subject 2, via control of light spot source 12 and x-y scanning mirrors 14, optokinetic device 16 (stripe cage 76), and flasher 70.
  • relay panel 20 controls the usage of a light spot source 12 (such as a laser) which operates in conjunction with a shutter 66 and x-y scanning mirrors 14 to provide test stimuli comprising a light spot which moves in accordance with a pre-programmed pattern corresponding to desired test stimuli for the particular test being administered (e.g., EOG tracking).
  • Light spot source (or laser) 12 is preferably a Metrologic Laser, Model No. ML-600 or ML-620 (manufactured by Metrologic Instrument, Inc.).
  • the shutter 66 -- which is a mechanism used to block the laser beam (rather than turning on and turning off the laser beam, which could be detrimental to the laser) -- is preferably implemented by a solenoid (Model No.
  • the x-y scanning mirrors 14 are preferably implemented by the following equipment (manufactured by General Scanning, Inc. of Watertown, Massachusetts): a Series XY-300 Scanning Assembly, two G-330 Galvanometers, an X-7 Mount, and an A-102 Driver Amplifier.
  • relay panel 20 controls a motor 68 which is used to raise and lower a flasher 70, thus placing flasher 70 in position with respect to the subject 2 for the purpose of administering a "flashing light” (VER) test.
  • the flasher 70 is controlled by photostimulator 72 which, in turn, is controlled by the processor 34 via logic section 62 and interface 30.
  • the flasher 70 is preferably implemented by a Photostimulator device, Model PS22 (manufactured by Grass Medical Instruments of Quincy, Massachusetts).
  • the relay panel 20 controls the optokinetic device 16, consisting of a motor 74 which is used to raise and lower a stripe cage 76, such optokinetic device 16 being utilized (for example) in the administration of EOG tests to the subject 2.
  • Figure 3A is a diagrammatic representation of the preamplifier network 24 of the CEOG system.
  • the preamplifier network 24 -- as previously mentioned -- is preferably located in the electrode junction box 6 ( Figure 1). Each of the electrodes 6a through 6i is connected to the preamplifier network 24.
  • preamplifier network 24 of Figures 1 and 2 basically comprises, with reference to Figure 3A, amplifiers A1 through A6, each corresponding to a specific pair of electrodes 6a/6b, 6c/6d, ... connected to the subject 2.
  • Preamplifier network 24 comprises individual preamplifiers A1, A2,..., A6 for receiving input test data signals from corresponding pairs of electrodes, and for providing corresponding preamplifier outputs PREMP1, PREMP2,..., PREMP6 to the amplifier network 26 ( Figure 2).
  • Preamplifiers A1, A2,..., A6 also receive zero-adjustment inputs ZRADJ1, ZRADJ2,..., ZRADJ6, resulting from manual bias adjustment by the operator or automatic bias adjustment under the control of the processor 34 ( Figure 2), as will be discussed below relative to Figure 5.
  • electrode test data signals for a particular eye measurement for example, left vertical eye measurement
  • preamplifier A1 a preamplifier output is provided (specifically, the preamplifier output of preamplifier A1 is provided as signal PREMP1 via terminal A thereof).
  • Zero adjustment signals (such as ZRADJ1 corresponding to bias adjustment of preamplifier A1) are received and provided to terminal 2 of the particular preamplifier to be adjusted (in this case, preamplifier A1).
  • ZRADJ1, ZRADJ2,... are zero adjustment signals (previously referred to, in Figure 2, as BIAS signals) received either from amplifier network 26 (in the case of manual bias adjustment) or from processor 34 via the DAC contained in converter stage 56 and the interface 30 (in the case of automatic bias adjustment). This subject will be addressed in further detail below.
  • Power signals (previously referred to as PWR in Figure 2) -- specifically, +15 volts D.C, -15 volts D.C, and a ground signal GND -- are provided to terminals F, E and H, respectively, of the various preamplifiers A1 through A6 as power inputs thereto, terminal K of each preamplifier A1 through A6 being grounded.
  • the preferred embodiment includes input/output connector terminals 102 connected by coaxial cable to respective preamplifiers A1-A6, as shown in Figure 3A for preamplifier A1 alone.
  • terminal B of each preamplifier A1-A6 is preferably connected in common to the outer shield of the coaxial cable. This common ground connection arrangement significantly aids common mode rejection, thus eliminating a substantial amount of normally encountered system noise.
  • Figure 3B is a detailed schematic of the preamplifiers A1, A2,..., A6 of the preamplifier network 24 of Figure 3A.
  • preamplifiers A1, A2,..., A6 each comprise an amplifier AMP1, which -- in the preferred embodiment -- is an AD522 amplifier (manufactured by Analog Devices of Massachusetts).
  • Amplifier AMPl receives electrode test data signals via terminals L and 10. Such electrode test data signals are applied to terminals 1 and 3, respectively, of amplifier AMPl.
  • Diodes CR1 and CR2 provide amplifier AMP1 with protection from "static discharge.”
  • Capacitors C7 and C8 are provided between terminal L and ground, and terminal 10 and ground, respectively, for the purpose of removing high frequencies occurring in the electrode test data signals.
  • Grounding resistors R13 and R14 -- provided between terminals L and 10, respectively, and ground -- are preferably five megohm resistors which drain off leakage currents from amplifier AMP1 before the electrodes are "plugged in.” If this is not done, a voltage (as much as ⁇ 15 volts) could accumulate on capacitors C7 and C8, which would cause the patient to receive a shock through the electrodes.
  • Amplifier AMP1 also has an external gain-setting resistor R8 connected between terminals 2 and 14 thereof.
  • Variable resistance P1 is an offset null potential which is adjusted to provide zero volts at terminal 7 of amplifier AMP1 when the inputs (at terminals 1 and 3 thereof) are “shorted.”
  • a further supply voltage -V EE is provided to amplifier AMP1 (at terminal 5 thereof).
  • each amplifier A1, A2,..., A6 of preamplifier network 24 may be zero-adjusted by means of respective inputs ZRADJ1, ZRADJ2, — , ZRADJ6.
  • Input ZRADJi is derived from circuitry 46' of Figure 5 (to be discussed below).
  • An input capacitor C9 is provided for the purpose of removing noise from the input signal ZRADJi.
  • Amplifier AMP2 is provided with a feedback RC network, consisting of capacitor C10 (which also removes noise) and resistor R11 connected in parallel between output terminal 6 and input terminal 2 of amplifier AMP2.
  • Supply voltages +V CC and -V EE are supplied to terminals 7 and 4, respectively, of amplifier AMP2, and biasing capacitors C11 and C12 are connected between respective terminals 7 and 4 (of amplifier AMP2) and ground.
  • Circuits 100 and 102 consist of RC networks (resistor R1 and capacitors C1 and C3 in the case of circuit 100, and resistor R2 and capacitors C2 and C4 in the case of circuit 102).
  • the latter RC circuits operate on -15 volt and +15 volt inputs, respectively, to derive the supply voltages -V EE and +V CC , respectively, while at the same time accomplishing noise decoupling.
  • FIG. 4A is a diagrammatic representation of the amplifier network 26 of the CEOG system.
  • Amplifier network 26 comprises a plurality of amplifiers A11, A12,..., A16 for receiving respective preamplifier output signals PREMP1, PREMP2,..., PREMP6, as shown.
  • Amplifiers A11,..., A16 amplify the aforementioned respective preamplifier output signals, and provide amplifier output signals AMPOUT1,
  • AMPOUT2,... , AMPOUT6 corresponding to the electrode test data signals for left vertical eye movement, right vertical eye movement, left horizontal eye movement, right horizontal eye movement, left occipital movement and right occipital movement, respectively.
  • the outputs AMPOUT1,..., AMPOUT6 are provided to converter stage 56 ( Figure 2).
  • the inputs PREMP1, PREMP2,..., PREMP6 are also provided to selector switch 59 which, as shown in Figure 4A, selects (by operator actuation of the switch) a particular preamplifier output for display on the scope 58.
  • selector switch 59 which, as shown in Figure 4A, selects (by operator actuation of the switch) a particular preamplifier output for display on the scope 58.
  • This facilitates broad-range bias adjustment of the preamplifier output signals by affording the operator a visual display of the preamplifier outputs, and thus immediate visual display of the results of the bias adjustment action taken by the operator.
  • scope 58 is preferably a B&K PRECISION Oscilloscope, Model No. 1403A (manufactured by DYNASCAN Corporation of Chicago, Illinois).
  • Figure 4B is a detailed schematic of the amplifiers A11, A12,..., A16 of the amplifier network 26 of Figure 4A.
  • network 120 comprises a series of RC circuits made up of resistor R3 in series with capacitor C5, and resistor R5 in series with capacitor C6, such RC networks being provided for the purpose of filtering the inputs PREMPj .
  • Diodes CR1 and CR2 in input network 120 correspond in function to the similarly designated diodes of the preamplifiers Ai ( Figure 3B).
  • Capacitors C7 and C8 correspond to the similarly designated capacitors in Figure 3B, and provide the function of high frequency removal during test administration.
  • Resistors R13 and R14 correspond to similarly designated grounding resistors in Figure 3B.
  • resistors R3 and R4 can be replaced by capacitors.
  • gain-setting resistor R8 connected at terminals 2 and 14 of amplifier AMP3
  • supply voltages +V CC and -V EE are provided at terminals 8 and 5, respectively, of amplifier AMP3.
  • External adjustment of amplifier AMP3 is provided via variable resistor
  • FIG. 5 is a diagrammatic representation of biasing circuitry 46' contained in the amplifier network 26 of Figure 2.
  • Figure 1 discloses auto-calibration circuitry 46, responsive to the processor 34, for adjusting offsets of individual amplifiers within the preamplifier network 24, in the preferred embodiment of the invention, such auto-calibration functions originate in biasing circuitry in amplifier network 26 ( Figure 2).
  • biasing circuitry 46' basically comprises a plurality of potentiometers POT1,..., POT6 for manual adjustment of the bias of individual amplifiers in preamplifier network 24 ( Figure 2), via generation of outputs ZRADJ1,..., ZRADJ6.
  • Such manual adjustment of individual amplifiers A1,..., A6 of preamplifier network 24 ( Figure 3A) occurs, in the preferred embodiment, when a bias select switch -- comprising ganged switches S1,..., S6 -- is in either the AUTO or MANUAL positions.
  • Automatic adjustment of individual amplifiers in preamplifier network 24 is achieved when ganged switch S1,..., S6 ( Figure 5) is in the AUTO position.
  • automatic adjustment input signals BIAS1-BIAS6 are received from converter stage 56 ( Figure 2), and such signals BIAS1-BIAS6 contribute, via respective resistors R21-R26, to the generation of zero-adjustment currents ZRADJ1-ZRADJ6.
  • the operator of the inventive CEOG system is able to manually adjust the offset voltage of the individual amplifiers in preamplifier network 24 ( Figure 2) via adjustment of particular potentiometers (POT1, POT2, etc.).
  • POT1, POT2, etc. particular potentiometers
  • This enables the operator of the CEOG system to perform broad-range biasing of particular amplifiers -- e.g., amplifiers associated with left vertical eye movement, right vertical eye movement, etc. -- and thus, to achieve, via such broad-range biasing, elimination of almost all of the D.C. offset voltage associated with the corresponding electrodes attached to the head of the subject.
  • the CEOG system of the present invention also provides automatic, narrow-range biasing of the individual amplifiers in preamplifier network 24 ( Figure 2).
  • Such automatic, narrow-range biasing of the individual amplifiers in the network 24 is achieved by generation, in processor 34 ( Figure 2) of BIAS signals, such BIAS signals being provided -- via interface 30 and converter stage 56 -- to the biasing circuitry 46' ( Figure 5).
  • Such BIAS inputs (BIAS1, BIAS2, ...) contribute to output adjustment signals ZRADJ1, ZRADJ2, etc., and elimination of the remainder of the D.C. offset voltage associated with the corresponding electrodes is thus automatically achieved.
  • Figure 6A is a diagrammatic representation of the ADC portion 56' of the converter stage 56 of Figure 2.
  • the ADC portion 56' of converter stage 56 ( Figure 2) includes a plurality of ADC's -- designated A/D1, A/D2 and A/D3 -- for receiving pairs of analog electrode test data input signals AMPOUT1/AMPOUT2, AMPOUT3/AMPOUT4 and AMPOUT5/AMPOUT6, respectively, from amplifiers A11, A12,..., A16, respectively, of amplifier network 26 ( Figure 4A), and for converting these analog inputs to respective digital outputs DAT0-DAT9.
  • converters A/D1-A/D5 are clocked by a timing clock input SAMPLE, and this causes each converter to convert its respective analog input signal (AMPOUT1, AMPOUT2, etc.) to a 10-bit digital word which is stored in an internal buffer in the particular converter A/D1-A/D5. Then, upon generation of inputs , and by the computer processor 34 ( Figure 2), converters A/D1-A/D5 gate the data from the internal buffer onto the output channel, at the appropriate time, constituting the digital output DAT0-DAT9.
  • the ADC portion 56' includes a further converter A/134 for receiving and converting, to digital form, analog signals TACH2 (relating to the speed of motor 50 ( Figure 2) which drives the chair 8, and STRIPESPD (relating to the speed of the motor 74 which drives the stripe cage 76 in optokinetic device 16 ( Figure 2)).
  • the ADC portion 56' of Figure 6A includes an additional converter A/D5 for receiving and converting, to digital form, analog signals POSX and POSY (relating to the X and Y positions of the mirrors 14 ( Figure 2)).
  • Analog signal TACH2 is provided to converter stage 56 by motor controller 52, via control panel 54 and logic section 62 ( Figure 2); analog signal STRIPESPD is provided by control panel 54 directly to converter stage 56; and analog signals POSX and POSY are provided by relay panel 20 to converter stage 56 via control panel 54 and logic section 62 ( Figure 2).
  • each converter A/D1-A/D5 receives an input SAMPLE which causes the commencement of the conversion of analog data to digital form. When all conversions are complete, output DATRDY is generated as an output. These two control signals will be discussed further below.
  • Figure 6B is a detailed schematic of one half of the converter A/D1 of Figure 6A. It is to be understood that the other half of converter A/D1 is identical in structure to the first half shown in Figure 6B. Moreover, it is to be further understood that each converter A/D2-A/D5 is identically configured to converter A/D1.
  • Converter A/D1 that is, each half thereof -- basically comprises sample and hold circuit 150, ADC device 154, and buffers 158 and 160.
  • Sample and hold circuit 150 comprises amplifiers 166 and 168, and AND gate 170, configured as shown.
  • Sample and hold circuit 150 is preferably an AD582 device (manufactured by Analog Devices).
  • ADC device 154 is a conventional analog-to-digital converting device, but is preferably an AD571 device (manufactured by Analog Devices).
  • buffers 158 and 160 include tristate amplifiers 172 through 177 and AND gate 178, configured as shown. That is to say, when the output of gate 178 is “low,” the outputs of amplifiers 172 through 177 are open circuits; when the output of gate 178 is “high,” the outputs of amplifiers 172, 173,... are the same as input signals B1, B2,... from ADC154.
  • buffers 158 and 160 are hex/tristate buffers, Model Nos. SN74LS365 or SN74365 (manufactured by Texas Instruments).
  • output AMPOUT1 is received from amplifier network 26 ( Figure 2) by sample and hold circuit 150.
  • Signal DATRDY is normally "high”
  • signal SAMPLE is normally "low.”
  • ADC device 154 performs digital conversion of the analog input AMPOUT1 in response to receipt of signal SAMPLE from ADC logic circuitry 200 going “low” ( Figure 6D), to be discussed below. During the digital conversion process, ADC holds output to the “high” condition, thus making DATRDY “low.” Once conversion is completed, however, ADC device 154 generates a "low” output . It is to be noted that, in order for output DATRDY to go "high,” each of the two ADC devices 154 in each converter A/D1,...,
  • A/D6 must generate a "low” output at terminal . This will allow the output DATRDY (subsequently provided to ADC logic circuitry 200 ( Figure 6D)) to go “high.”
  • Digital bit outputs B1 through B6 are provided to respective tristate buffers 172 through 177 in hex buffer 158, while digital bit outputs B7 through B10 are provided to corresponding buffers (not shown) in buffer 160.
  • buffers 172 through 177 of buffer 158 (and corresponding buffers (not shown) in buffer 160) are of the type that look like an open circuit at the output until receipt of a clock-type signal.
  • processor 34 ( Figure 2) provides address input signals to ADC address decoding logic 190 ( Figure 6C), which generates clock-type signals , (as will be explained in detail below).
  • ADC address decoding logic 190 Figure 6C
  • clock-type signals as will be explained in detail below.
  • buffers 158 and 160 which transmit the buffered digital bit data, via interface 30, to processor 34 ( Figure 2), as outputs DAT0 through DAT9.
  • Figure 6B is a detailed schematic of one half of converter A/D1 of Figure 6A, and further, that each of converters A/D2-A/D5 are configured identically to converter
  • A/D1-A/D5 release their digital output DAT0-DAT9 in response to respective clock-type inputs (see Figure 6A), while the second halves of converters A/D1-A/D5 release digital data DAT0-DAT9 in response to respective clock-type inputs
  • Figure 6C is a diagrammatic representation of address decoding logic 190 in converter stage 56 of Figure 2.
  • logic 190 basically comprises binary/octal decoder circuits 192, 194 and 196. Principal inputs to the logic 190 are address inputs ADDR1, ADDR2 and ADDR3 , and further inputs and
  • Binary/octal decoder 192 responds to receipt of signal inputs (acting as a decoding clock signal) and inputs ADDR1-ADDR3 to perform octal conversion, selectively actuating one of the eight outputs through in correspondence to the particular decoder input. In this manner, previously discussed clock-type outputs, STROB10-STROB17, are obtained. STROB10-STROB17 are, it will be recalled, clock-type signals provided to respective converter devices A/D1, A/D2, in the ADC portion 56' of converter stage 56 (see Figure 6A) .
  • binary/octal decoder 194 responds to receipt of signal inputs and ADDR1-ADDR3 to perform octal conversion, thus actuating a selected one of the outputs through in correspondence to the particular decoder inputs.
  • clock-type outputs STROB20-STROB27 are obtained, and these clock-type outputs (as will be discussed subsequently) are utilized in the DAC portion of the converter stage 56 ( Figure 2).
  • binary/octal decoder 196 responds to receipt of signal inputs and ADDR1-ADDR3 to perform octal conversion, thus actuating a selected one of the outputs Q0 through Q7 in correspondence to the particular decoder inputs.
  • clock-type outputs STROBMX and STROBMY are obtained, and these clock-type outputs (as will be discussed below) are utilized as clock-type inputs to the DAC circuitry 300 ( Figure 6E).
  • decoder 196 ( Figure 6C) generates clock-type outputs and which are clock-type inputs provided to A/D5 ( Figure 6A).
  • binary/octal decoders 192, 194 and 196 are preferably SN74LS42 converter circuits (manufactured by Texas Instruments).
  • Figure 6D is a detailed schematic diagram of further ADC logic circuity 200 and 250 of the converter stage 56 of Figure 2.
  • Logic circuitry 200 consists of a timer 202 (preferably, a one-second timer) which responds to
  • Logic 250 basically comprises NAND gate 252 and one-shot devices 254 and 256.
  • NAND gate 252 detects the occurrence of either input (a one-bit (specifically, bit number 14) input from interface 30 of Figure 2) or (an input from logic section 62 of Figure 2 ) , and triggers the one-shot device 254 to provide output SAMPLE, transmitted to the ADC device 154 in each converter A/D1-A/D5 ( Figures 6A and 6B).
  • the trailing edge of signal SAMPLE causes each ADC device 154 to start the conversion process.
  • processor 34 transmits -- via interface 30 -- appropriate decoder inputs (or or ), and ADDR1-ADDR3, as a result of which address decoding logic 190 ( Figure 6C) issues appropriate clock-type outputs (any one of ) so as to cause the digital data to be transmitted to the processor 34 by the appropriate converter A/D1,..., A/D5 ( Figure 6A) .
  • Figure 6E is a detailed schematic diagram of the DAC portion 300 of the converter stage 56 of Figure 2.
  • the DAC portion 300 comprises latch circuits 302 and 303, DAC device 306, and associated amplifier 308.
  • latch circuits 302 and 303 are reset by input applied to the R terminals of each. Then, in response to a clock-type input applied to the CK terminals thereof, each of latch circuits 302 and 303 receives and latches digital data DTOA6-DTOA9 and DTOA0-DTOA5, respectively, from the processor 34 ( Figure 2) applied thereto.
  • latch circuits 302 and 303 are preferably 74LS174 latch devices (manufactured by Texas Instruments).
  • DAC device 306 is preferably an AD561J converter device (manufactured by Analog Devices of Massachusetts). Accordingly, DAC 306 is provided with supply voltages V CC and V EE (+5 and -15 volts, respectively). The gain and bias of the outputs of the DAC device 306 are externally set by potentiometers P1 and P4, respectively.
  • amplifier 308 is preferably a UA741 amplifier (manufactured by Analog Devices of Massachusetts). Accordingly, amplifier 308 is supplied with +15 volt and -15 volt supply voltages. Whereas analog output ANALOUT is provided to terminal 2 of amplifier 308, the terminal 3 thereof is connected to ground via grounding resistor R1. Moreover, the output of amplifier 308 -- besides being connected in a "feedback" arrangement to the DAC device 306 (via potentiometer P1) -- is also feedback-connected to its terminal 2 input via feedback capacitor C5. Finally, amplifier 308 is provided with bypass capacitors C6 and C7.
  • the DAC circuitry 300 preferably includes an additional pair of latch circuits, an additional DAC device, and an additional amplifier, so as to provide dual-channel outputs.
  • processor 34 ( Figure 2) provides digital signals DTOA0-DTOA9 ( Figure 6F) -- via latch circuits 302 and 303 -- to DAC device 306, wherein analog conversion takes place.
  • the resulting analog output ANALOUT -- after current-to-voltage conversion in amplifier 308 -- provides an output voltage signal BIASN.
  • Figure 7A is a diagrammatic representation of the motor controller 52 of the CEOG system.
  • Motor controller 52 basically comprises a linear servo controller 320, a dynamic breaking relay 322, tach (motor speed) buffer 324, brake command input (fail safe) circuitry 326, and chair interlock circuitry 328.
  • linear servo controller 320 receives a control signal MTRSPD, provided by control panel 54 ( Figure 2), but originating in logic section 62 as a result of operator selection.
  • Linear servo controller 320 also receives a tachometer input signal TACHIN from tachometer 51 associated with the motor 50 ( Figure 2), indicating actual speed of the motor 50.
  • Linear servo controller 320 then performs, in a conventional manner, a comparison operation of actual motor speed (TACHIN) with desired motor speed (MTRSPD), and -- as a result of such comparison -- controller 320 generates appropriate motor-controlling current (LOADLO/LOADHI ) signals.
  • the motor-controlling currents are provided through dynamic braking relay 322 to motor 50 so as to control the speed of operation thereof by increasing or decreasing the speed of the motor 50, and thus the rotational speed of the chair 8 ( Figure 2).
  • Tachometer input signal TACHIN provided to linear servo controller 320 is also provided to tach buffer 324, from which analog signal TACH2 is provided to the ADC portion 56' of converter stage 56 ( Figures 2 and 6A) for subsequent digital conversion, and provision to processor 34 via interface 30. In this manner, the processor 34 is kept apprised of the actual speed of the motor-driven chair 8.
  • Tach buffer 324 can be any conventional buffer amplifier, as is well known to one of ordinary skill in the art.
  • Linear servo controller 320 also receives -- at terminals 4 and 6 thereof -- respective brake command signals BRK6 and BRK8, these brake command signals being provided by fail safe circuitry 326.
  • Linear servo controller 320 responds to the brake command input signals BRK6 and BRK8 in a conventional manner to force the motor-controlling current from controller 320 to zero during the braking operation.
  • input signals BRK6 and BRK8 are outputs of the fail safe circuit 326, which circuit 326 receives inputs BRK1 and from control panel 54 ( Figure 2).
  • Figure 7B is a detailed schematic diagram of the fail-safe circuit 326 of Figure 7A.
  • Input signal BRK1 is received from logic section 62 ( Figure 2) via control panel 54, and is always maintained at a "high” level (for example, +5 volts). Input signal is normally maintained “high,” so that solenoid 362 is non-actuated, and switch 364 is normally closed. This forces controller 320 ( Figure 7A) to put out zero amps at the LOADLO/LOADHI outputs thereof.
  • linear servo controller 320 when goes “low,” solenoid 362 is actuated, causing normally closed switch 364 to open, and the open-circuited inputs BRK6 and BRK8 to linear servo controller 320 ( Figure 7A) cause linear servo controller 320 to adjust the speed of motor 50 so as to bring actual motor speed (TACHIN) into coincidence with desired motor speed (MTRSPD).
  • FIG 7C is a detailed schematic of the chair interlock circuitry 328 of Figure 7A.
  • chair interlock circuit 328 comprises resistor 330, transient diode 332 and solenoid K1 -- arranged as shown in Figure 7C -- and connected, as shown, both to A.C. power switches 338 and 340 ( Figure 7A), and to seat belts 334 (located on the chair 8 ( Figure 2)).
  • switch S 2 the chair motor "on” switch which, as will be seen below, is located on an operator control section of control panel 54 of Figure 2 causes application of a positive D.C. voltage to solenoid K1 via resistor 330, solenoid K1 actuating A.C.
  • Motor controller 52 further includes position detection circuitry 336 which, in actual implementation, is located on the chair 8 ( Figure 7A) .
  • the chair 8 is equipped with a reflective plate 350 which reflects light received from lamp 352 (actuated by a voltage +POSLIT), causing the reflected light to impinge on photodetector 354 so as to generate chair position information POSDET, which information passes through motor controller 52 and control panel 54 ( Figure 2) to logic section 62.
  • Signal POSDET indicates that the chair 8 is at a position 90 degrees to the right of its "normal" position.
  • Motor controller 52 ( Figure 7A) also includes a start limit switch 356 (normally open) which, in actual implementation, is located on the chair 8 ( Figure 7A).
  • start limit switch 356 upon operator reset of the system, if start limit switch 356 is open, as indicated by a "high” STRLIM signal, the chair 8 will automatically, under system control, move to its "normal” position, which is attained when the limit switch 356 closes.
  • FIG 7D is a detailed schematic diagram of the dynamic braking relay 322 of Figure 7A.
  • Dynamic braking relay circuit 322 basically comprises relay switches 370 and 372, series-connected resistor 374, actuating solenoid 376, and transient diode 378.
  • relay switches 370 and 372 are normally in the downward position so as to pass the LOADLO/LOADHI control current signal of controller 320 to motor 50 (Figure 7A).
  • Input +BRAKE is maintained at a positive voltage ("high") level and relay switches 370 and 372 remain in the normal downward position.
  • solenoid 376 is actuated, and forces switches 370 and 372 into the upward position. This not only interrupts the provision of control currents signal LOADLO/LOADHI to the motor 50, but also achieves a dynamic braking effect by short-circuiting the input terminals to motor 50, via the short-circuit connection established between switches 370 and 372.
  • Figure 8 is a diagrammatic representation of the relay panel 20 of the CEOG system.
  • relay panel 20 receives various input control signals from control panel 54 and logic section 62 ( Figure 2), and in response thereto, controls the operations of the light source 12, mirrors 14, shutter 66, optokinetic device 16 (comprising motors 74 and 74' and stripe cage 76), the flasher motor 68 and flasher 70.
  • relay panel 20 receives feedback signals (XBACK and YBACK) from the mirrors 14, and provides these feedback signals, via control panel 54, to logic section 62, wherein -- as will be subsequently described -- compensation for the distortion of the light source projection on the cylindrical walls 18 ( Figure 1) of the test station 4 is achieved.
  • Relay panel 20 receives various D.C. voltage inputs (+12 v. and +15 v.), and an A.C. input (110 v.).
  • the A.C. input to relay panel 20 is merely passed therethrough, so as to provide A.C. power to the laser 12 ( Figure 2).
  • the 12 v. D.C. input is provided, via relay switches 402 and 404 and resistor 406, as inputs (LITE1 and LITE2) to the lamp 400 which illuminates the stripe cage 76 ( Figure 2).
  • relay switches 402 and 404 which are normally in the open position, are actuated to the closed position by solenoid 408 when (received from logic section 62) goes “low.” On the other hand, in response to going “high, " solenoid 408 is off, and switches 402 and 404 return to the normally open position, interrupting D.C. power supply to the lamp 400.
  • relay panel 20 includes a capacitor 412 having its positive terminal connected to power input +RELAY. Capacitor 412 acts as a noise-prevention filter for the +RELAY input (a positive voltage -- for example, 15 volts).
  • relay panel 20 includes switches 422 and 424 which remain in the normally open position so long as input (from logic section 62 of Figure 2) is "high.” However, in response to signal going "low” (thus commanding turn-on of the stripe cage motor 74), solenoid 420 causes switches 422 and 424 to close, thus defining paths for the input of +12 volts and its return, respectively.
  • the aforementioned power input paths include switches 416 and 418 which are normally (so long as from logic section 62 remain “high") in the upward position, so that +12 volts and its return are provided to input terminals A and B, respectively, of motor 74.
  • This power input to motor 74 raises, or maintains in the raised position, the stripe cage 76 of optokinetic device 16.
  • motor 74 generates status output signals LIMUPOK or LIMDNOK when the stripe cage 76 is raised to its upper limit or lowered to its lower limit, respectively.
  • Relay panel 20 also includes an arrangement of switches and solenoids for controlling the raising and lowering of the flasher 70 by motor 68. Specifically, switches 428 and 430 remain in the normal upward position so long as input signal applied to solenoid 432, stays "high” -- indicating a desire on the part of the operator to maintain the motor 68 in the "off” condition. In fact, switches 428 and 430, when in the upward position, create a short circuit across the power input terminals of motor 68.
  • Relay panel 20 of Figure 8 receives input signals -CGMTR and +CGMTR from control panel 54 ( Figure 2), and supplies same to motor 74' for the purpose of controlling the speed of rotation of the stripe cage 76 by motor 74'.
  • Relay panel 20 also receives inputs -SHUT and +SHUT from control panel 54, and provides same to shutter 66 ( Figure 2) for the purpose of opening and closing the shutter 66 in response thereto.
  • relay panel 20 provides D.C. power to the mirrors 14, and as well provides output signals XDRIVE and YDRIVE (received from logic section 62 via control panel 54) to the mirrors 14 for the purpose of driving the mirrors in the X and Y directions, respectively.
  • Relay panel 20 also receives, from mirrors 14, the X and Y position signals XBACK and YBACK which are provided to logic section 62 (via control panel 54) for the purpose of developing the POSX and POSY status inputs to processor 34 via interface 30.
  • control panel 54 of Figure 2 will now be described in more detail with reference to Figures 9A through 9E.
  • the control panel 54 ( Figure 2) basically serves two purposes. First, it is used as a junction box to distribute power throughout the system, and to act as a common distribution point for most of the control and status signals passing through the CEOG system. Secondly, it serves the usual function of a control panel -- visibly, allowing the operator to interact with the system by means of switches and display indicators. In the preferred embodiment, the former function -- that of a junction box -- is served by having one cable from each functional unit (for example, as seen in Figure 2) to the control panel, as opposed to having a plurality of cables passing throughout the system between the various functional units.
  • Figure 9A is a diagrammatic representation of the operator control section of the control panel 54 of the CEOG system.
  • control section 450 of control panel 54 comprises a plurality of display indicators (DS), switches (S), and adjustment knobs connected to potentiometers (P).
  • various display indicators, switches and adjustment knobs can be divided into various categories relating to power, chair control, stripe cage operations, flasher operations, and light source (laser) and mirror operations.
  • Operator control section 450 includes an A.C. power switch S 1 , by means of which the system is turned on and A.C. power is supplied thereto.
  • Application of A.C. power is indicated by display indicator DS1.
  • display indicator DS1 As indicated previously, with respect to Figure 2, application of A.C. power to the CEOG system, and specifically to power supply 60 thereof, results in generation of various D.C. supply voltages.
  • operator control section 450 includes various display indicators DS2, DS3, DS4 and DS5, indicating availability of the various D.C. power supply voltages -- +5 v., -15 v., +15 v., and +12 v., respectively.
  • Operator control section 450 also includes a switch S 2 for turning on the motor 50 (Figure 2) for the purpose of powering the chair 8.
  • Display indicator DS6 indicates when the motor 50 is turned on.
  • a desired speed of the motor 50, and thus a desired speed of revolution of the chair 8 is selected by the operator by means of adjustment knob P 1 which is connected to a potentiometer (not shown) for generating the signal MTRSPD applied to the motor controller 52 ( Figure 2), and specifically to the linear servo controller 320 thereof ( Figure 7A) .
  • Operator control section 450 of Figure 9A also includes switches S 3 and S 4 for causing momentary stopping and starting, respectively, of the chair 8 ( Figure 2), and a display indicator DS7 indicating when a "CHAIR READY" condition exists.
  • operator control section 450 includes a reset switch S 5 , which is preferably a momentary switch comprising a manual reset button which is utilized for a multitude of purposes, visibly: (1) to cause the rotatable chair 8 ( Figure 2) to be rotated to its normal (reset) position; and (2) to clear a number of computer bits such as SCAN (referring to mirror scanning) and RECORDING ON DISK (to be discussed below).
  • a reset switch S 5 is preferably a momentary switch comprising a manual reset button which is utilized for a multitude of purposes, visibly: (1) to cause the rotatable chair 8 ( Figure 2) to be rotated to its normal (reset) position; and (2) to clear a number of computer bits such as SCAN (referring to mirror scanning) and RECORDING ON DISK (to be discussed below).
  • Operator control section 450 also includes switches S 7 and S 8 for raising and lowering, respectively, the stripe cage 76 ( Figure 2).
  • switches S 7 and S 8 are one-shot push-button switches for raising and lowering, respectively, the stripe cage 76 in response to a single push of the respective buttons S 7 nd S 8 .
  • operator control section 450 includes an adjustment knob P 2 connected to a potentiometer (not shown) -- preferably, a 10-turn potentiometer -- for adjusting the speed of rotation of the stripe cage 76 ( Figure 2).
  • Operator control section 450 also includes an on-off switch S 11 for activating-deactivating a linear light bulb 400 ( Figure 8) inside the stripe cage 76 ( Figure 2).
  • a three-position switch S 14 having positions "left" and "right” for designating respective leftward and rightward directions of rotation of the stripe cage 76, and an "off" position for turning off the rotatable stripe cage 76.
  • Operator control section 450 also includes display indicator DS8 for indicating the "stripes ready" condition, display indicator DS9 (RECORDING ON DISK) which is an indicator that flashes when the computer is transferring data to the disk (so that the system operator will not inadvertently fill the disk to full capacity) and push-button switches S 9 and S 10 for raising and lowering, respectively, the flasher 70 ( Figure 2).
  • display indicator DS8 for indicating the "stripes ready" condition
  • display indicator DS9 RECORDING ON DISK
  • push-button switches S 9 and S 10 for raising and lowering, respectively, the flasher 70 ( Figure 2).
  • operator control section 450 includes adjustment knobs P 3 and P 4 for controlling the horizontal speed and vertical position, respectively, of the light generated by the light source (laser) 12 ( Figure 12).
  • adjustment knob P 3 is connected to a potentiometer (not shown) -- preferably, a 10-turn potentiometer -- for controlling the horizontal speed of the light spot seen by the subject 2 ( Figure 2), such light spot being controlled as a result of movement of the mirrors 14 reflecting the light from the laser 12, such movement of the mirrors 14 being in turn controlled by the potentiometer (not shown) as set by the operator via adjustment of knob P 3 .
  • Vertical position of the light spot seen by the subject 2 is controlled by adjustment of the laser 12 via the potentiometer (not shown) as set by the adjustment knob P 4 .
  • Operator control section 450 also, preferably, includes a manual function switch S 12 , by means of which the position of the light spot generated by the laser 12 and mirrors 14 ( Figure 2) can be controlled in accordance with various functions -- for example, an alternating square wave function, alternating ramp function, and alternating sine wave function.
  • Operator control section 450 includes a toggle switch S 13 for operator selection of the "set-up” or “automatic” modes of operation of the light source 12 and mirrors 14 ( Figure 2). That is to say, designation of the "set-up” mode of operation causes the subject 2 to be subjected to light source stimuli in accordance with a pattern selected by the physician administering the test by means of a previously explained control contained in the operator control section 450. Conversely, designation of the "automatic" mode of operation causes the subject 2 to be subjected to light stimuli as controlled by the computer (processor) 34 of the CEOG system.
  • Operator control section 450 includes a test warning indicator DS10, which is actuated when testing of or adjustment to the system is being performed
  • test warning condition consists of the release of the electromagnetic brake on the chair 8 ( Figure 2) so that the chair 8 can be turned manually away from its normal (reset) position.
  • Operator control section 450 also includes a display indicator DS11 for indicating the "scan" mode of operation of the CEOG system, and a switch S 6 for designating that the number of turns through which the chair 8 ( Figure 2) is to be rotated is as indicated (automatically) by the computer processor 34 of the CEOG system.
  • FIGS 9B through 9E are detailed schematic diagrams of the control panel 54 of the CEOG system.
  • Figure 9B is a detailed schematic diagram relating to the power distribution functions performed by the control panel 54 of Figure 2, as well as relating to the on-off A.C. power switch (S 1 ) and various display indicators (DS1, DS2, etc.) appearing in the operator control section 450 of the control panel 54.
  • actuation of the switch S 1 causes A.C. power in to be distributed -- via terminal board TB1 -- to various parts of the CEOG system via connector terminals J103, J110 (terminals E, F, and G thereof), etc.
  • power supply 60 ( Figure 2), in response to actuation of A.C. power in the system, generates D.C. supply voltages (for example, +5 v., +12 v., ⁇ 15 v., etc.), as needed.
  • display indicators DS7 through DS10 certain of the modes of operation or conditions of the CEOG system are indicated by display indicators DS7 through DS10. Specifically, in accordance with the arrangement shown in Figure 9B, occurrence of a "chair ready” condition causes one terminal of display indicator DS7 to go “low” (as indicated by ) , and this grounding of one side of display indicator DS7 causes application of a +15 volt D.C. voltage to display indicator DS7, resulting in visual display of the "chair ready” condition. In a similar manner, display indicators DS8 through DS10 indicate the "stripes ready,"
  • circuit 456 receives an input MTRSPD1, provided (as will be seen below) by logic portion L3 ( Figure 10F), which converts the digital signals RUNFWD, RUNBKD and RUNSLOW to analog signals.
  • Circuit 462 shows switch S 2 , by means of which the motor power supply for operation of the chair 8 ( Figure 2) is turned on.
  • Display indicator DS6 indicates "motor power on” when the chair motor is powered on, and output signals MTPWR and MTRSWON (to be discussed below) are produced in the process.
  • Circuit 464 in Figure 9C includes switch S 3 which is a momentary switch which, upon actuation, is momentarily moved from an "up” position to a “down” position, thus transferring a ground condition from terminals to terminals STOPSW.
  • switch S 3 is a momentary switch which, upon actuation, is momentarily moved from an "up” position to a “down” position, thus transferring a ground condition from terminals to terminals STOPSW.
  • terminals STOPSW and are used to set and reset, respectively, a no-bounce switch 750.
  • Circuit 466 includes switch S 4 which operates in the same manner as switch S 3 to selectively produce ground conditions at terminals STRSW and
  • circuit 468 selectively produces ground conditions at RSTSW and
  • Circuit 470 includes switch S 6 (a toggle switch) which, in its upward or closed position, designates local control of the number of turns or revolutions which the chair 8 ( Figure 2) is to take before being stopped.
  • the number of turns or revolutions is locally designated by the operator utilizing a decoded thumb-wheel switch S 21 -S 24 located in logic portion L1' of Figure 10B (to be discussed below).
  • switch S 6 turns control of the number of revolutions of the chair 8 ( Figure 2) over to the computer for automatic control thereof.
  • Circuit 472 includes potentiometer 474 associated with adjustment knob P 2 ( Figure 9A), by means of which stripe speed is designated as a result of voltage division of a +15 volt input between resistor 476 and potentiometer 474, providing an analog output
  • Circuits 478 and 480 includes switches S 7 and S 8 , respectively, which, in response to actuation thereof, generate outputs and respectively, designating upward and downward movement, respectively, of the cage 76 ( Figure 2).
  • Circuit 482 includes switch S 13 which, in its upward position, provides output calling for the mirrors 14 (Figure 2) to move in accordance with the setting of manual function switch S12 (in operator control section 450 of Figure 9A).
  • Switch S 13 -- in its lower position -- turns control of the mirrors 14 over to the computer processor 34 ( Figure 2) for automatic control thereof.
  • Circuit 484 includes display indicator DS11 which is actuated by a +15 volt input in response to terminal going "low.” Terminal goes “low” as a result of logic operations performed in portion L9 ( Figure 10L), as will be described in more detail below, when: (1) the setup switch S13 is "on,”
  • Circuits 486 and 488 include switches S 9 and S 10 , respectively, which operate in the same manner as previously described with respect to circuits 464 and 466.
  • the output conditions at terminal UPFLSW, DWNFLSW, etc. in circuits 486 and 488 are utilized to set/reset no-bounce switches contained in portion L4' ( Figure 10I).
  • Circuit 490 includes switch S 11 which, in response to actuation thereof, issues output signal STRPSW indicating "turn on” of the light 400 (Figure 8) in stripe cage 76 ( Figure 2).
  • Circuit 492 includes switch S 12 by means of which three scanning functions for scanning of the light source 12 ( Figure 2) -- under control of the mirrors 14 -- may be chosen. Specifically, output signals and are provided in correspondence to desired scanning in accordance with square wave, triangular (or ramp function) and sine wave functions, respectively.
  • Circuit 494 includes potentiometer 496 corresponding to adjustment knob P 3 ( Figure 9A), by means of which horizontal speed of the mirrors 14 ( Figure 2) can be chosen. Circuit 494 produces output signal OSREF, which designates the desired horizontal scanning speed of the mirrors 14 relative to lowermost and uppermost reference speeds determined by the voltage dividing resistors 498 and 500, respectively.
  • Circuit 502 discloses potentiometer 504 corresponding to adjustment knob P 4 ( Figure 9A) , by means of which vertical positioning of the beam from light source 12 is adjusted. As a result of such adjustment, circuit 502 performs voltage division by means of potentiometer 504 so as to provide output signal VERTPOS indicating the desired vertical positioning of the beam from light source 12. It is to be noted that, as will be seen below in connection with the discussion of portion L10 ( Figure 10M), potentiometer 504 acts in parallel with the MOVY input from the computer, and with any other signals which are summed in a summing amplifier of portion L10, to develop the. output YDRIVE, by means of which the desired vertical positioning of the beam from light source 12 is achieved.
  • circuit 506 discloses switch S 14 ( Figure 9A), by means of which leftward or rightward movement, or stopping, of the stripe cage 76 ( Figure 2) is achieved.
  • Leftward movement of the stripe cage 76 corresponds to output -CGMTR
  • rightward movement of the stripe cage 76 corresponds to output +CGMTR -- these two output signals being provided to relay panel 20 ( Figure 8), and thence to motor 74' so as to achieve leftward or rightward movement, respectively, of the stripe cage 76 ( Figure 2 ) under the control of the motor 74'.
  • switch S 14 has an "off" position whereby neither leftward nor rightward movement of the stripe cage 76 is designated.
  • circuit 506 further comprises a switch S 14 ' which is gang-connected to switch S 14 , and which generates outputs and in response to actuation of switch S 14 to the "left" and "right” position, respectively. The outputs and are provided as status signals to logic section 62 ( Figure 2).
  • circuits 530 through 533 are shown, which circuits are utilized for converting various control signals to driver signals.
  • circuit 530 converts signals TWLON (Test Warning Light On) and CHRDYON (Chair Ready On) to signals which can light display indicators DS10 and DS7, respectively ( Figure 9A) .
  • Circuit 531 supplies a regulated +12.3 volts, called +RELAY, which signal -- as will be recalled with respect to Figure 8 -- is provided to relay panel 20 for the purpose of powering certain previously described solenoid/relay switch combinations.
  • Circuit 532 converts input signals RELBRK
  • circuit 533 converts input signal STRIPESPD -- from the "center wiper" of the potentiometer 474 ( Figure 9C) associated with adjustment knob P2 ( Figure 9A) -- to output signals +CGMTR and -CGMTR provided to relay panel 20 ( Figure 8 ) , and thence to motor 74' for the purpose of turning the stripe cage 76 ( Figure 2) at a given speed.
  • circuit 533 under the influence of further input TRNCG (Turn Cage) provided (via resistor 536) to the base of transistor 535, the latter pulling -CGMTR to ground so as to turn on the stripe cage motor 74' ( Figure 8).
  • TRNCG Transmission Cage
  • the operator can take the following actions: (1) fie will power-up the CEOG system by actuating switch S 1 on operator control section 450 ( Figure 9A), thus distributing A.C. power and various D.C. supply voltages to various parts of the CEOG system, as previously described with reference to Figure 9B.
  • mirrors 14 will scan the X direction in accordance with the particular manual function previously designated by the operator utilizing switch S 12 in operator control section 450 ( Figure
  • the Y position of the mirror will be determined by a combination of the setting of adjustment knob P 4 (and potentiometer circuit 502) and a MOVY command from computer processor 34 ( Figure 2), as will be discussed in more detail below.
  • the scanning speed of mirrors 14 ( Figure 2) will be determined by the setting of adjustment knob P 3 (in conjunction with potentiometer circuit 494), and will preferably yield a scanning cycle time of from 0.8 seconds to 10 seconds duration.
  • this mode of operation will be indicated on display indicator DS11 (see circuit 484 of Figure 9C).
  • switch S 13 is a toggle switch, such that subsequent toggling of switch S 13 will result in "automatic" mode of scanning.
  • scanning will be performed under computer control.
  • the computer processor 34 can be programmed to completely and exclusively control the scanning pattern, speed, etc. to which the subject 2 is subjected.
  • the computer can be programmed so that scanning can be controlled as to the scanning pattern in accordance with whichever scanning function is manually selected at switch S 12 , and can also be controlled so as to cause the horizontal speed of scanning to be in accordance with whatever horizontal speed is set manually at adjustment knob P 3 of operator control section 450.
  • the computer processor 34 can be programmed to cause vertical scanning to be conducted in accordance with whatever speed is set on adjustment knob P 3 (even though adjustment knob P 3 is normally utilized to merely designate horizontal speed of scanning).
  • the CEOG system can be programmed (as will be seen subsequently) to continue rotation, but this time in the counter-clockwise direction (presuming that the previous direction of rotation was clockwise), in response to further actuation of switch S 4 .
  • the operator can either press a computer console button calling for a hard-copy printout of the test results, or can type a predesignated character (such as the character "R” ) on the console of the computer so as to record the test results on a more permanent storage (such as disk 42 ( Figure 2)).
  • a computer console button calling for a hard-copy printout of the test results
  • a predesignated character such as the character "R”
  • disk 42 Figure 2
  • the system can operate in an "automatic reset" mode of operation, by which reverse chair rotation will take place in a “slow mode” of operation, and the CEOG system will seek a
  • limit switch setting -- corresponding to a normal (reset) position -- at which time chair rotation will be stopped. This will be explained in more detail below.
  • switch S 6 gives the operator the alternatives of "local” control or “computer” control of the number of turns through which the chair 8 ( Figure 2) is to pass prior to being automatically stopped.
  • the number of turns through which the rotating chair is to pass can be locally designated by actuation of a decoded thumbwheel switch S 21 -S 24 in portion LI' ( Figure 10B) of logic section 62 ( Figure 2) .
  • operator console section 450 Figure 9A
  • the stripe cage 76 will be lowered into position.
  • Figures 10A through 10N are detailed logic block diagrams and circuit schematics of the logic section 62 of the CEOG system.
  • Logic section 62 ( Figure 2) receives electronic signals from three sources: the computer processor 34 via EOG interface 30 ( Figure 2), the switches on the control panel ( Figure 9A) and associated circuitry ( Figures 9B through 9E), and other units or elements of the CEOG system (as will be described below).
  • the logic section 62 processes all of these incoming signals, and produces control and indicator signals that are distributed to the remainder of the CEOG system.
  • Logic section 62 will, for the purpose of the discussion below, be divided into logic section portions L1 through L5 and L8 through L11, each of which will now be considered in detail.
  • Figures 10A and 10B are detailed logic diagrams/ schematics of the portions L1 and L1', respectively, of logic section 62 ( Figure 2). Portions of L1 and L1' of logic section 62 basically perform the following four functions:
  • one-shot device 616 protects the RST output from being immediately turned off -- as, for example, by reception of a "high” signal from NAND gate 626 if NEARRST or ZERO go “low.”
  • NAND gate 608 is caused to issue the output RST upon setting of the no-bounce switch 600 (NAND gates 602 and 604 connected as shown) upon receipt of the "high" RSTSW input, provided by operator actuation of switch S 5 in operator control section 450 ( Figure 9A) -- see also circuit 468 ( Figure 9C).
  • NAND gate 608 is caused to issue the RST output as a result of inputs ZERO and NEARRST (received by NAND gate 626) both being "high” or "on.”
  • Input ZERO is an output provided by decoder 664 in portion L1' ( Figure 10B) which, as will be seen below, indicates that the chair has been rotated in the reverse direction by a prescribed number of turns.
  • input NEARRST is an output of portion L2' ( Figure 10D) which, as will be seen below, is a control signal indicating that the chair is in the "backward rotation" mode of operation.
  • circuit 632 comprises a timer 634 which provides, at its Q output, an oscillator output BLINK applied to various selected display indicators to achieve a "blinking" effect.
  • the test warning indicator DS10 ( Figure 9A) can be caused to blink by application thereto of output BLINK of circuit 632 ( Figure 10A).
  • circuit 632 includes a NAND gate 638 which performs an OR-type operation with respect to inputs and so that the output TWLON (Test Warning Light On) is issued in the presence of either input or and input BLINK.
  • TWLON Transmission Warning Light On
  • circuit 632 includes a NAND gate 638 which performs an OR-type operation with respect to inputs and so that the output TWLON (Test Warning Light On) is issued in the presence of either input or and input BLINK.
  • TWLON Transmission Warning Light On
  • input BLINK input BLINK
  • multiplexer (MUX) 650 receives and multiplexes turn information either generated by the computer as bits 1-4 from the processor 34 ( Figure 2), or locally designated via switches S 21 -S 24 .
  • the multiplexed output of multiplexer 650 is provided to latch circuit 652 which provides its latched output to the A0-A3 inputs of comparator circuit 654.
  • Circuit 656 of portion L1' of Figure 10B responds to an input POSDET (representing chair position information), and -- via analog comparator 658 and NAND gate 660 -- generates output POSCLK whenever a reflective strip 350 (Figure 7A) on the chair is detected by photodetector 354.
  • Output POSCLK provides a clocking input at the CK terminal of counter 662 which is an up-down counter for up-counting the number of chair revolutions (for example, during clockwise rotation), and for conversely down-counting the number of chair revolutions (for example, during counter-clockwise chair rotation).
  • the outputs Q A -Q D of Counter 662 provide the B0-B3 inputs to comparator 654.
  • digital comparator 654 compares the desired number of chair revolutions to the actual number of chair revolutions, and when the two coincide, comparator 654 generates the output MATCH.
  • Counter 662 is enabled, for counting, by the logical input (provided by a GO flip-flop 752 in portion L2 of Figure 10D, to be discussed below). Counter 662 is reset upon occurrence of (indicating system reset). Up or down counting of counter 662 is determined by the logical input DOWN (provided by up/down flip-flop 772 of portion L2 of Figure 10D). The outputs Q A -Q D of counter 662 are provided to decoder 664 which issues a output upon occurrence of a complete chair cycle (clockwise rotation followed by counter-clockwise rotation). The output has already been discussed with reference to circuit 618 ( Figure 10A).
  • the output of comparator 658 is provided to a monostable device 666 which generates a output to NAND gate 660 so that output POSCLK will have a minimum time duration in response to either the output from comparator 658 and/or that from monostable device 666.
  • Circuit 668 of portion L1' comprises NAND gates 670, 672 and 674, and inverters 676 and 678, which provide a clock input to latch circuit 652 under either of the following two conditions:
  • latching of data by latch circuit 652 is controlled by the RST (Reset) signal received at AND gate 674 (enabled by an input from the switch S 6 via inverter 676), and provided to the CLK input of latch 652 via OR gate 672 and inverter 678.
  • RST reset
  • latching of data by latch circuit 652 is controlled by STROBX (a computer-generated strobe signal) provided via AND gate 670 (enabled by an enabling input from switch S 6 ), OR gate 672 and inverter 678.
  • switch S 6 is a toggle switch correspondingly designated in operator control section 450 ( Figure 9A). Closing of the switch results in a ground connection, resulting in a "low” input to AND gate 670 (disabling computer-controlled latching) and resulting in a “high” (inverted “low”) input to enable AND gate 674 for reset-controlled latching of data. Conversely, opening of switch S 6 results in application of a +5 volt ( "high”) input to enable AND gate 670 for computer-controlled latching, and to disable AND gate 674 to preclude reset-controlled latching.
  • input POSDET is an analog signal produced when light is detected from a reflective strip 350 on chair 8 ( Figure 7A). Such light is detected by comparator 658 ( Figure 10B), the negative input of which is adjusted by level-detector potentiometer P 2 .
  • comparator 658 triggers one-shot device 666 (preferably, having a one-shot duration of .25 seconds) so as to maintain an output POSCLK issuing from NAND gate 660 connected to the output of comparator 658. That is to say, NAND gate 660 performs an OR operation between the outputs of comparator 658 and one-shot 666.
  • circuit 656 insures that output POSCLK is of minimum acceptable duration, and output POSCLK is provided as a clocking input to counter 662 (for counting chair rotations), and as a further input to portion L2 ' ( Figure 10D), as will be discussed below.
  • Figures 10C, 10D(1) and 10E are detailed schematics of further portions L2, L2 ' and L2 " , respectively, of logic section 62 of Figure 2.
  • Figure 10D(2) is a timing diagram for explaining the timing of the operations of portion L2' of Figure 10D(1).
  • portions L2, L2' and L2" receive input signals STRSW (start switch), STOPSW (stop switch), RST (reset), (start limit switch), and MATCH (indicating that the number of counts of chair revolutions matches the predetermined value).
  • Portions L2, L2' and L2" provide logic circuitry for performing various logic functions so as to provide the following signals in proper sequence: CHRDYON (Chair Ready On), RUNIB (Run Motor), RELBRK (Release Brake), FWD (Go Forward), (Run Slowly), and DOWN (Count Down).
  • CHRDYON Chair Ready On
  • RUNIB Raster Drive
  • RELBRK Release Brake
  • FWD Go Forward
  • Run Slowly DOWN
  • a Run flip-flop (NAND gates 700) which provides via inverter 701 an output RUNIB when the chair motor is running, such output being provided to portion L3' ( Figure 10G).
  • the output from flip-flop 700 is OR'ed (in NAND gate 702) with input to provide output RELBRK (Release Brake) either when the motor is running (as indicated by RUNIB) or when manual rotation of the chair is indicated (by from portion L3' of Figure 10G).
  • RELBRK Release Brake
  • a Forward/Backward flip-flop (NAND gates 704) which issues an output FWD which is "high” when the chair is being driven in the forward direction, or "low” when the chair is being driven in the backward direction.
  • a Run Slow flip-flop (NAND gates 706) which issues an output which is "low” when the chair is running slow. It is to be noted that the chair runs slow only in the backward direction, as dictated by the application of output FWD from NAND gate 704 via inverter 708 to device 706 (lowermost NAND gate thereof). It is to be further noted that device 706 is set by input such that the resetting of the system by the operator causes the chair to rotate slowly in the backward direction, this being done for the purpose of centering the chair in its normal (reset) position. It will be recalled that resetting of the CEOG system results in generation (as previously discussed) of signal RST.
  • input RST is provided via inverter 710 to flip-flop 712, causing resetting of flip-flop 712.
  • the output (to NAND gate 714) is "high.” goes “low” when the chair 8 finds the start limit switch 356, and NAND gate 714 provides the output CHRDYON.
  • CHRDYON is also produced when signal -- a signal produced by a Hold flip-flop to be discussed in connection with Figure 10D(1) below -- goes “low.”
  • the signal CHRDYON (Chair Ready On) is provided to a circuit 530 ( Figure 9E), wherein it is converted to an output which in turn is responsible for activation of display indicator DS7 ( Figure 9B), which indicates the "chair ready” condition.
  • resetting of the system results in application of signal RST via inverter 710 as a clock input to Check Mechanical Ready flip-flop 716, causing a Q output therefrom to NAND gate 718.
  • NAND gate 728 performs an AND operation with respect to the inputs thereto. Specifically, when goes “high,” and when the output of inverter 732 goes “high” as a result of NAND gate 722 issuing a “low” output, and further when the Q output (MECRDY) of flip-flop 712 goes “high,” the Check Mechanical Ready flip-flop 716 is reset, resulting in removal of the Q input from NAND gates 718 and 722, respectively.
  • NAND gate 754 performs an OR operation between XYZ and the further input (STRSW . HOLD) -- provided by NAND gate 756 -- to produce output GOB, the latter being provided as a clock input to "turn on” Go flip-flop 758. Generation of output GOB also turns on the Run flip-flop 700 ( Figure 10C).
  • POSCLK is the primary clock pulse, based on which the number of rotations of the chair is counted. It is to be noted that, in the preferred embodiment, the chair rotates through a one-quarter turn before reception of the first POSCLK pulse. In Figure 10D(2), it is presumed that the number of rotations is preset for three. Upon the completion of two and one-quarter turns -- that is, the beginning of the third full turn -- the comparator output MATCH occurs, and flip-flop 766 is set with the reception of the next POSCLK pulse.
  • the Q output of flip-flop 766 enables one-shot device 768 so as to produce a output on the trailing edge of POSCLK for a prescribed period of time (preferably, 0.1 seconds), this output being defined as signal
  • the latter is a negative pulse applied to Forward/Backward flip-flop 704 ( Figure 10C) to reset the flip-flop 704, resulting in FWD going "low,” further resulting in rotation in the backward direction of the chair 8 ( Figure 2).
  • flip-flop 766 has its reset input connected to a series connection of NAND gate 778 and inverter 780, NAND gate 778 performing an OR operation between input and input
  • flip-flop 766 is reset under either of two conditions: (1) generation of the negative pulse ; or (2) occurrence of the reset input Up/Down flip-flop 782 is set by the output of flip-flop 766 when flip-flop 766 first goes “on,” issuing the output DOWN, indicating the down-count mode of operation of the counter 662 ( Figure 10B).
  • NAND gate 626 ( Figure 10A) performs an AND operation with respect to inputs ZERO and NEARRST, and as a result of the OR operation of NAND GATE 608, the output RST is issued by the arrangement of Figure 10A. See the timing diagram of Figure 10D(2). As previously explained, with reference to Figure 10A, this output RST lasts for 0.1 seconds as a result of the operation of one-shot 616, which deactivates NAND gate 608 after that time period.
  • the output HOLD is AND'ed with BLINK in NAND gate 792, resulting in the latter being provided -- as previously discussed -- to NAND gate 714 in Figure 10C, for the purpose of generating the CHRDYON (Chair Ready On) indicator.
  • the HOLD output is provided to NAND gate 756, the other input of which receives the "set" output of flip-flop 750, the latter being set by actuation of the start switch (reception of signal STRSW).
  • actuation of the start switch results in reverse rotation of the chair 8 ( Figure 2).
  • the chair 8 can, of course, be stopped manually, by actuation of the Stop switch, generating signal STOPSW.
  • the latter signal is a "set” input to flip-flop 794, resulting in generation of output
  • the latter output turns off the Run flip-flop 700, resulting in stopping of rotation of the chair.
  • portion L2" receives input MTRSWON from circuit 462 as a result of the actuation of switch S 2 in the operator control section 450 ( Figure 9A), and receives input RELBRK from circuit 532 ( Figure 9E).
  • both MTRSWON and RELBRK be "high” -- this will cause the output of inverter 802 to be “high,” which will turn on transistor Q1, and accordingly turn off transistor Q2.
  • the dynamic braking relay 322 Figure 7A
  • Logic portion L2" ( Figure 10E) also has a manual brake on/off switch 804 which, in the downward position, manually allows the portion L2" to function as described above. Conversely, when switch 804 is in the upward position, brake application is removed from the chair 8 for manual positioning. In this case, test warning indicator DS10 in operator control section 450 ( Figure 9A) comes on, as a result of being "low” (connected to ground).
  • FIGS 10F and 10G are detailed schematics of portions L3 and L3', respectively, of the logic section 62 of Figure 2.
  • portion L3' receives inputs RUNIB (output of Run flip-flop 700 of Figure 10D(1)) and FWD (output of Forward/Backward flip-flop 704 of Figure 10D(1)).
  • Switch SC of portion L3' is a push-button switch actuated by the operator in order to manually rotate the chair 8 ( Figure 2).
  • N ND gates 870 and 878 perform an AND operation with respect to the inputs thereto, and NAND gate 872 OR's the outputs of gates 870 and 878.
  • NAND gate 872 issues an output under either of two conditions: (1) actuation of switch SC in the manual mode (MANMODE) of operation, or (2) receipt of Run flip-flop output RUNIB in the non-manual mode of operation.
  • NAND gates 880, 882 and 884 operate in a similar manner, so that NAND gate 882 issues an output under either of two conditions: (1) receipt of Forward/Backward flip-flop output FWD in the non-manual mode of operation, or (2) actuation of switch SD (to designate backward rotation) in the manual mode of operation.
  • NAND gate 876 issues output (provided to portion L3 of Figure 10F) provided that the following two conditions both exist: (1) running of the chair has been ordered either manually or automatically, and (2) either backward rotation of the chair has been manually designated, or forward rotation of the chair has been non-manually designated.
  • NAND gate 886 and inverter 884 combine to issue RUNBKD (provided to portion L3 of Figure 10F) under the following conditions: (1) running has been designated either manually or automatically, and (2) neither manual backward rotation nor automatic forward rotation have been designated.
  • the input will cause a current to flow into the negative input of op amp 822, but this current will not be applied instantaneously because of the RC time constant associated with resistor 830 and capacitor 832.
  • the current into op amp 822 will cause a voltage output from op amp 822. This voltage output is, preferably, +5 volts, as adjusted by potentiometer Pf associated with op amp 822.
  • the input (which is mutually exclusive from as dictated by the logic of Figure 10G) will cause a different output of op amp 822.
  • this voltage output of op amp 822 is preferably -5 volts.
  • the input will cause the output to be decreased in magnitude (preferably, from -5 volts to -2.5 volts). will be "on” only during system reset (as dictated by previously described signal RST).
  • portion L3 contains switches SA and SB which provide the capability of selecting manual operation of the chair motor 50 ( Figure 2), for example, for the purpose of testing the system.
  • Inputs and are provided to optical coupler devices 810 and 824, respectively.
  • input goes “low”
  • current is caused to flow through resistor 812, turning off NPN transistor 814, resulting in application of a negative current via resistors 816 and 820 to op amp 822.
  • op amp 822 provides a negative output.
  • optical coupler device 824 causes current to flow through resistor 826, turning off transistor 828, and resulting in a negative current input to the op amp 822.
  • op amp 822 provides a positive (+15 volts) input.
  • RSLOW RSLOW by inverter 836.
  • Optical coupler device 826 in response to detection of a "low” input, turns off PNP transistor 832, and a negative voltage is provided to the negative input of op amp 822.
  • resistors 834 and 838 are twice the impedance value of corresponding resistors (discussed above) 816, 830 and 820, 834 (respectively). Accordingly, the input to op amp 822 is not as large a negative current, but half that. As a result, op amp 822 issues an output one-half the magnitude of the previously discussed outputs.
  • Portion L3 includes switches SA and SB which are actuable to a "manual" position. In such position, output MTRSPDl is connected via potentiometer 852 to the output of op amp 822, with the result that manual adjustment of motor speed MTRSPDl can be accomplished. Moreover, when switch SB is moved to the "manual" position, output goes “low” indicating the
  • portion L3 is provided with a potentiometer 844 which is a zero-bias potentiometer, utilized to insure that the output of op amp 822 is zero volts when both and are "high” (that is, both RUNFWD and RUNBKWD are “off”).
  • a potentiometer 844 which is a zero-bias potentiometer, utilized to insure that the output of op amp 822 is zero volts when both and are "high” (that is, both RUNFWD and RUNBKWD are “off”).
  • FIGS 10H and 10I are detailed schematics of portions L4 and L4', respectively, of logic section 62 of Figure 2.
  • the logic circuitry in portions L4 and L4' receive signals from the various switches on the operator control section 450 ( Figure 9A), and as well from limit switches on the motors 68 and 74 ( Figure 2) which raise and lower the flasher 70 and stripe cage
  • logic portions L4 and L4' generally produce signals that operate relays in relay panel 20 ( Figures 2 and 8) previously discussed so as to raise and lower the flasher 70 and stripe cage 76, and to also rotate the stripe cage 76.
  • logic portions L4 and L4' provide status output signals which indicate, to the processor 34 ( Figure 2), the status of the two devices -- flasher 70 and stripe cage 76. Referring to portion L4 of Figure 10H, when goes “high,” flip-flop 900 is turned on. As a result, the Q output thereof is "low.”
  • Limit switches 902 and 904 are "limit up” and “limit down” switches, respectively, associated with the optokinetic device 16.
  • motor 74 -- which raises and lowers the stripe cage 76 -- includes, in the preferred embodiment, the switches 902 and 904 ( Figure 10H) .
  • Switches 902 and 904 are normally closed, but are selectively opened when the stripe cage 76 is raised by the motor 74 to its upper limit and lower limit, respectively.
  • the stripe cage 76 Upon system initialization, the stripe cage 76 will normally be in its uppermost position, such that switch 902 will be open and switch 904 will be closed. Moreover, resetting of the system in combination with upper limit switch 902 being open (LIMUPOF) and operator actuation of switch S 8 (to lower the stripe cage -- ) , results in operation of Up flip-flop 906 and Down flip-flop 908 via NAND gate 910 to turn the motor on ( goes “low”) and to designate lowering of the stripe cage 76 (via going "low”). Turn-on of the motor 74 and lowering of the stripe cage 76 is effected by signals and respectively, in the manner previously described with reference to Figure 8.
  • switch 904 opens, and the "stripes ready" condition is indicated via NAND gate 912, inverter 914 and NPN transistor 916, provided that switch S 11 (in operator control section 450 of Figure 9A) has been actuated to energize the stripe cage light 400 and stripe gate rotation motor 74' ( Figure 8).
  • NAND gate 912 issues output LITEON via inverter 918 and TRNCG via inverter 920, provided to circuits 532 and 533 ( Figure 9E), respectively, so as to provide further outputs and +CCMTR/-CGMTR to relay panel 20 and motor 74' ( Figure 8)
  • NAND gate 912 issues output LITEON via inverter 918 and TRNCG via inverter 920, provided to circuits 532 and 533 ( Figure 9E), respectively, so as to provide further outputs and +CCMTR/-CGMTR to relay panel 20 and motor 74' ( Figure 8)
  • going “low” results in application of power to stripe cage light 400
  • inputs -CGMTR and +CGMTR to motor 74' result in forward and reverse rotation, respectively, of the stripe cage 76 under the influence of motor 74'.
  • the direction of rotation of the stripe motor 76 ( Figure 8) is designated by switch S 14 in operator control section 450 ( Figure 9A) .
  • portion L4' includes a flip-flop 950 which is set by turn-on of the system power, at which time the Q output of flip-flop 950 is provided via NAND gates 952 and 954 to one-shot 956, which generates a short (preferably, 0.15 seconds) pulse Q.
  • NAND gate 952 performs an OR operation with respect to the inputs thereto, while NAND gate 954 permits the output of NAND gate 952 to be blocked by and LIMDNOF (the latter two signals being received from portion L4 of Figure 10H).
  • the Q output of one-shot 956 results in generation,' by NAND gate 958, of the output FLMTRON (Flasher Motor On), the latter comprising a "high" input to circuit 532 ( Figure 9E), generating a low output which causes application of power to the flasher motor 68 ( Figure 8).
  • the Q output of one-shot 956 resets the flip-flop 950.
  • Portion L4' also receives an input UPFLSW (as a result of operator actuation of switch S 9 in operator control section 450 of Figure 9A for the purpose of raising the flasher).
  • Input UPFLSW sets flip-flop 960, and the "set" output thereof is provided via NAND gates
  • flasher down switch S 8 in operator control section 450 results in setting of flip-flop 962 via DWNFLSW, and the set output thereof is provided -- via NAND gates 964 and 958 -- to produce FLMTRON (again, presuming that NAND gate 964 is not inhibited by and LIMDNOF).
  • FIG 10J is a detailed schematic of portion L5 of logic section 62 of Figure 2.
  • Portion L5 generates SYNCIN and 5MSSAMP which -- via photostimulator 72 ( Figure 2) -- operate the flasher 70, such operation being conducted under the control of computer processor 34 via EOG interface 30 and portion L5.
  • portion L5 actuates photostimulator 72 to send a trigger pulse to the flasher 70 to produce a single flash on command.
  • the CEOG system can, again via photostimulator 72, arrange for stimulation of the subject 2 -- and thus, transmission of electrode test data to the computer processor 34 -- once during any given time interval (for example, 2.5 milliseconds, 5 milliseconds, etc.).
  • portion L5 includes flip-flops 970 and 972 which are reset by a power-on initialization input or a computer initilization input ( , provided to flip-flops 970 and 972 via NAND gate 974 and inverter 976.
  • the Q output of flip-flop 970 actuates one-shot device 978 and series-connected one-shot device 980 to generate short (preferably, 10 microseconds) pulses separated by a longer (preferably, 5 milliseconds) time duration, such output being designated 5MSSAMP.
  • the latter comprises an "initiate sample” pulse provided to circuit 250 of Figure 6D, wherein it is utilized to provide the output SAMPLE (used for ADC in Figure 6A).
  • Flip-flop 972 -- via its output -- actuates solenoid/ switch combination 982 to cause closing of the switch so as to provide a variable (by virtue of potentiometers 984 and 986) time control to the one-shot device 980.
  • one-shot 980 can be adjusted to provide "initiate sample” pulses of less than 5 milliseconds (preferably, 2.5 milliseconds) duration.
  • one-shot 978 is triggered by the falling edge of the pulse output from the output of flip-flop 970. This falling edge is generated by flip-flop 970 in response to the D input, DOUT13 -- comprising a "Go bit” input from the computer processor 34 ( Figure 2). DOUT13 designates a desired stream of pulses which will occur typically at 5 millisecond intervals. Similarly, processor 34 provides input DOUT11 to the D input of flip-flop 972, and this results (as previously explained) in adjustment of one-shot 980 so as to provide a 2.5 millisecond "initiate sample” pulse separation.
  • flip-flops 970 and 972 are clocked (at the C inputs) by computer-generated strobe input provided via inverter 988. is, as will be seen below, decoded in interface 30 of Figure 2 (see discussion of Figure 11D below).
  • processor 34 Figure 2 generates a flash bit DOUT12, provided to the D input of flip-flop 990, the latter being clocked by computer-generated strobe
  • the Q output of flip-flop 990 triggers one-shot 992 which generates -- via inverter 994 -- a square wave pulse of short duration (preferably, 15 microseconds).
  • SYNCIN is a pulse, preferably having a 25-volt "swing,” and is provided to photostimulator 72 so as to synchronize the flashing light produced thereby.
  • Flip-flop 990 is reset either by operator-initiated reset or by the output of one-shot 992, provided via NAND gate 998 and inverter 999.
  • Figure 10K is a detailed schematic diagram of the portion L8 of logic section 62 of Figure 2.
  • Portion L8 uses feedback from the X mirror signal (XBACK) to generate a signal (YFIX) that is sent to the Y mirror 14 ( Figure 2) -- specifically, to the Y-deflection circuitry of mirrors 14 -- to correct for the curvature of the light spot (laser spot) on the cylindrical walls 18 ( Figure 1) of the test station 4.
  • XBACK X mirror signal
  • YFIX a signal
  • YFIX Y-deflection circuitry of mirrors 14
  • This curvature results from the fact that the laser 12 is located above the head of the subject 2, and is accordingly aimed downwardly on the cylindrical walls 18.
  • portion L8 receives input XBACK, an analog signal provided by mirrors 14.
  • Isolation op amp (voltage follower) 1000 in response to the positive input XBACK and the negative bias/gain-adjusted input (bias and gain are adjusted via potentiometers 1002 and 1004, respectively) -- provides its output to both positive inputs of a multiplier 1006.
  • Multiplier 1006 squares the output of amplifier 1000, and provides the result -- via isolation op amp (voltage follower) 1008 -- as output YFIX. The latter output YFIX is provided to portion L10 ( Figure 10M) to be discussed below.
  • portion L8 correction or compensation for the vertical angle existing between the line-of-sight from the light source (laser) 12 and the cylindrical wall 18 ( Figure 1) and the line-of-sight between the eyes of the subject 2 and the cylindrical walls 18 is achieved.
  • FIG. 10L is a detailed schematic diagram of the portion L9 of logic section 62 of Figure 2.
  • portion L9 receives and stores four bits from a Move X register (to be subsequently explained), the four bits being designated:
  • DOUT10 (GO X bit) -- a bit which causes scanning of the mirror in the X direction in accordance with circuitry contained in portion L10 ( Figure 10M) to be discussed below.
  • CMPSINE DOUT11 -- a bit which causes scanning of the mirror in the X direction using bits 0 through 9 of the MOVX register (to be discussed below), the deflection ranging from -30° to +30° in 1024 increments thereof.
  • DOUT12 CMPSHTR -- a bit which causes opening of the shutter 66 ( Figure 2).
  • DOUT13 YSCAN -- a bit which causes scanning of the mirror in the Y direction in accordance with a signal from the portion L10 ( Figure 10M) to be discussed below.
  • the output of flip-flop 1020 forms the output XSINE via NAND gate 1026.
  • NAND gate 1026 has its other input connected to switch S 13 (in operator control section 450 of Figure 9A), such that actuation of the auto/setup switch S 13 to the "setup" position (or DOUT10) will generate XSINE.
  • the output of inverter 1028 is OR'ed with the Q output of flip-flop 1022 in NAND gate 1032 to provide -- via transistor 1036 -- output is utilized to open/close the shutter 66 associated with the mirrors 14 ( Figure 2).
  • XSINE from inverter 1028 is AND'ed with the Q output of flip-flop 1021 in NAND gate 1030 and inverter 1034 to provide output CMPSINE.
  • inverter 1028 and NAND gate 1030 are OR'ed in NAND gate 1038, the latter providing a base-controlling input to transistor 1040.
  • Transistor 1040 provides a collector output the latter indicating operation of the laser 12 associated with the mirrors 14 and shutter 66 ( Figure 2).
  • the Q output of flip-flop 1023 is provided via inverter 1042 in a wire-OR'ed connection to the base of transistor 1040.
  • D0UT13 (YSCAN) -- input to flip-flop 1023 -- also actuates the scan light.
  • Portion L9 also includes flip-flop 1050 which is reset by initialization inpu (which occurs for one second after the power to the system is turned on) .
  • Flip-flop 1050 is set by inputs WRTONLY (indicating that the computer wants to write data to one of its register addresses) and (a strobe for loading data into the MOVY register, to be discussed below). These inputs are provided via inverter 1052 and NAND gate 1054.
  • the Q output of flip-flop 1050 is output (to be discussed further below with respect to Figure 10M).
  • Figures 10M and 10N are detailed schematic diagrams of portions L10 and L10', respectively, of logic section 62 of Figure 2. Portions L10 and L10' are responsible for performing various analog switching functions which enable the driving of the mirrors 14 ( Figure 2) in the X direction to be accomplished either under computer control or under local control. Furthermore, portions L10 and L10' are responsible for the performance of various summing and analog switching functions to accomplish the following:
  • portion L100' contains two buffer amplifiers provided for the purpose of feeding back the signal from the mirrors 14 ( Figure 2) so that the computer processor 34 can read and display the positions of the X mirror and Y mirror relative to the corresponding Position X and Position Y registers (discussed in more detail below).
  • portion LIO receives SIGOUT -- an analog signal produced by portion L11 ( Figure 100 -- to be discussed below); this analog signal defines a desired pattern of scanning to be performed by the laser 12/mirrors 14 ( Figure 2).
  • portion L10 receives output XSINE -- generated by portion L9 of Figure 10L, previously discussed -- the latter forming an enabling input permitting gate 1100 (preferably, a field-effect transistor analog switch) to pass SIGOUT through to the negative input of summing amplifier 1102, the positive input of which is connected to ground.
  • gate 1100 preferably, a field-effect transistor analog switch
  • summing amplifier 1102 produces mirror-driving output signal XDRIVE.
  • Portion L10 receives input MOVX (bits 0-9 of the MOVX register to be discussed below), and -- in a similar manner -- input MOVX is gated to the negative input of summing amplifier 1102 via gate 1104 enabled by input CMPSINE (generated by portion L9 of Figure 10L previously discussed). Proper biasing of the negative input of summing amplifier 1102 is provided by biasing circuitry 1106.
  • XSINE or CMPSINE is received by portion L10
  • SIGOUT the pattern generated by portion L11 of Figure 100
  • MOVX the computer-generated pattern
  • Output XDRIVE is an analog input to the X-driver card (not shown), which is a conventional hardware element supplied with the mirrors 14 ( Figure 2).
  • portion L10 initialization of the system results in generation of the latter being provided via amplifier 1112 as an enabling input to the switch 1114.
  • biasing voltage provided by biasing circuitry 1116 is gated through switch 1114 to the negative input of further summing amplifier 1118.
  • switch 1108 In response to input YSCAN (designating desired Y-direction scanning in accordance with the pattern SIGOUT), switch 1108 gates SIGOUT through to the negative input of amplifier 1118.
  • amplifier 1118 generates YDRIVE (the Y-direction driving signal for the mirrors 14 of Figure 2 ) in accordance with either SIGOUT (the pattern generated by portion L11 of Figure 100) or MOVY (the computer-generated pattern) .
  • the inverse of YSCAN is provided by inverter 1120 as an enabling input to switch 1122, thus disabling a further input to the negative input of amplifier 1118 (and thus, the parabolic correction when using YSCAN) .
  • Portion L10 includes circuitry 1130 and 1132 which supply voltages -V ss and +V dd , respectively, and are as well used to supply voltages to potentiometer 504.
  • Potentiometer 504 is associated with adjustment knob P 4 in operator control section 450 ( Figure 9A) which, as previously explained, is utilized to adjust the vertical position of the laser beam from light source 12.
  • the center tap thereof provides another summed input to the negative input of amplifier 1118, thus achieving necessary adjustment of the Y-direction mirror-driving output YDRIVE so as to achieve the desired vertical positioning of the light beam.
  • the portion L10' basically comprises an op amp (voltage-following) 1150 which receives feedback signal XBACK from the mirror driving circuitry in mirrors 14 ( Figure 2), and appropriately amplifies same to obtain the analog output POSX.
  • the analog output POSX is, as previously described, provided via converter stage 56 ( Figure 2) -- that is, the ADC portion thereof -- so as to provide the computer processor 34 with a digital input representative of the mirror position.
  • portion L10' is identical to a circuit which performs the same function with respect to the feedback signal YBACK (Y-direction feedback signal from the mirrors 14) so as to generate the analog output POSY.
  • Figure 100 is a detailed schematic diagram of the portion L11 of logic section 62 of Figure 2.
  • portion L11 includes a sine wave oscillator utilized in conjunction with establishment of a scanning pattern for the light beam generated by light source 12 in the case where manual function switch S 12 (on operator control section 450 of Figure 9A) is set to call for scanning of the light source 12 in accordance with a sine wave pattern.
  • manual function switch S 12 on operator control section 450 of Figure 9A
  • the frequency of the sine wave generated by the sine wave oscillator in portion L11 is controlled by various input signals corresponding to the scanning speed setting, as set by adjustment knob P 3 on operator control section 450.
  • portion L11 of Figure 100 contains the necessary circuitry for choosing between the various scanning waveform patterns, as selected by manual function switch S 12 .
  • device 1200 is a conventional device (preferably, an ICL8038 made by Intersil of Cupertino, California). It generates, at output terminal 2 thereof, a sine wave having characteristics as determined by an adjustable sine wave timing circuit 1202 provided at the L in terminal of the device 1200. In addition, device 1200 provides (at terminal 9 thereof) a square wave output and (at terminal 3 thereof) a sawtooth output. As previously discussed with reference to Figure 9C, switch S 12 is employed by the operator to designate the desired type of output. Switch S 12 generates signals and (selectively), and these inputs are provided to corresponding relays K1l, K12 and K13, respectively ( Figure 10L).
  • ICL8038 made by Intersil of Cupertino, California
  • the square wave, sawtooth or sine wave output of device 1200 is provided to the negative input of isolation amplifier 1204, the positive input of which is grounded.
  • amplifier 1204 issues output SIGOUT.
  • Proper biasing of the negative input of isolation amplifier 1204 is provided by biasing circuit 1206.
  • Device 1200 is provided, at terminal 8 thereof, with a frequency-controlling input OSREF originating in a potentiometer 496 connected in a voltage-divider arrangement with voltage-dividing resistors 498 and 500 (see Figure 9C).
  • signal OSREF is a frequency-controlling input resulting from operator actuation of adjustment knob P 3 in operator control section 450 ( Figure 9A), by which the operator adjusts the horizontal speed of scanning of mirrors 14. This effect is achieved by application of the input OSREF as a frequency-controlling input to the device 1200.
  • reference voltage inputs +VREF and -VREF are provided to supply voltage input terminals V CC and V EE , respectively, of the device 1200, the latter terminals also being connected to respective supply voltage circuits 1200 and 1212.
  • Portion L11 is provided with ganged switches SN connected to the terminal 10 input of device 1200.
  • Figures 11A through 11D and 11G are detailed logic block diagrams and circuit schematics of the interface 30 of the CEOG system of Figure 2.
  • Figures 11E, 11F and 11H are timing diagrams of the write (data out) sequence, read (data in) sequence and interrupt sequence, respectively, relating to the operation of the interface 30 of the CEOG system of Figure 2.
  • tristate buffers 1230, 1232 and 1234 are provided, each of which is responsive to input signal Specifically, when goes “low,” each of tristate buffers 1230, 1232 and 1234 is actuated so that a prewired address (for example, in the preferred embodiment, address 000,154) in the processor 34 ( Figure 2) passes through the tristate buffers 1230, 1232 and 1234 to outputs DAT0-DAT15.
  • a prewired address for example, in the preferred embodiment, address 000,154
  • tristate buffers 1230, 1232 and 1234 appear as an open circuit to output terminals DAT0-DAT15, and as a result data from DAT0-DAT9 (from processor 34 of Figure 2) is provided to the arrangement of Figure 11B.
  • DAT0-DAT9 from processor 34 of Figure 2
  • outputs DAT10-DAT15 are not active.
  • Tristate buffers 1230, 1232 and 1234 are, in the preferred embodiment, SN74LS365 devices (manufactured by Texas Instruments).
  • bus transceiver devices 1240-1243 receive and respond to input
  • data DAT0-DAT15 passes through internal inverter 1246 (shown, for illustrative purposes, in device 1240 only) to terminals (the latter terminals representing a common data bus to the computer processor 34 ( Figure 2)), and data passes through inverter 1247 to output terminals DAL0-DAL15.
  • Output terminals DAL0-DAL11 are connected as inputs to tristate buffers 1244 and 1245, which are responsive to input More specifically, when goes “low,” inputs DAL0-DAL11 are passed through to outputs DTOA0-DTOA11, the latter (as will be recalled from above) providing inputs to the DAC circuitry in converter stage 56 ( Figure 2). Conversely, when goes “high,” tristate buffers 1244 and 1245 are open-circuited, thus precluding any output DTOA0-DTOA11.
  • data is provided by the computer processor 34 ( Figure 2) via the computer bus , bus transceivers 1240-1243, tristate buffers 1244 and 1245, and output terminals DTOA0-DTOA11, to the DAC circuitry in converter stage 56 ( Figure 2).
  • control data (specifically, and are transmitted over the computer bus to further bus transceiver devices (not shown) -- identical to bus transceivers 1240-1243 -- so as to produce at the output thereof corresponding control data DOUT, DIN, SYNC, WTBT, IAKI , BS7 and INIT.
  • control data are utilized in a manner to be described below.
  • bus transceivers 1240-1243 are, in the preferred embodiment, bus transceivers. Model No. DM8838 (manufactured by National Semiconductors).
  • tristate buffers 1244 and 1245 are, in the preferred embodiment, buffer devices SN74LS365 (manufactured by Texas Instruments).
  • interface 30 ( Figure 2) further comprises tristate buffer devices 1250-1253 and latch circuit 1254.
  • device 1250 responds to going “low,” to pass data DAL8-DAL13 (the outputs of bus transceiver devices 1240 and 1241, respectively, of Figure 11B, just discussed above) to output terminals DOUT8-DOUT13.
  • DAL8-DAL13 the outputs of bus transceiver devices 1240 and 1241, respectively, of Figure 11B, just discussed above
  • the latter outputs are derived indirectly from the corresponding inputs (provided via the computer bus -- Figure 11B) to bus transceiver devices 1240 and 1241, and in particular are control bits 8-13 in a control word register (to be discussed below).
  • control bits 8-13 in a control word register
  • Tristate buffer 1251 responds to (a "Group 1" strobe) going “low,” to connect outputs DAT10-DAT15 to ground, thus creating “low” (zero) output conditions at DAT10-DAT15. It is to be noted that goes “low” whenever analog-to-digital converted data (from converter stage 56 to Figure 2 ) is to be entered in the processor 34. Referring back to Figure 6A, since converters A/D1-A/D5 provide 10 bits of data
  • tristate buffer 1251 performs the necessary function of inserting leading zeros into the most significant six bit positions (DAT10-DAT15). Referring back to Figure 11B, it will be recalled that goes “low, " when data input to the computer is to be achieved. Accordingly, DAT0-DAT15 from tristate buffers 1250-1252 are passed through devices 1240-1243 to the computer bus
  • tristate buffer 1252 responds to (a "status in” strobe) going “low,” to pass data DATIN9-DATIN14, provided by logic section 62 (of Figures 2 and 10A-100), to outputs DAT9-DAT14.
  • the latter is provided to the computer bus via devices 1240 and 1241 ( Figure 11B), as previously
  • tristate buffer 1252 blocks transfer of data.
  • Latch circuit 1254 responds to STROB0 (a "control register” strobe) to strobe data DAL0-DAL4 (received from processor 34 of Figure 2 via the computer bus and devices 1242 and 1243 of Figure 11B) in latch circuit 1254.
  • Tristate buffer 1253 responds to (a "status register” strobe) going “low,” to send data DAL0-DAL4 latched by device 1254 to outputs DAT0-DAT4, the latter being provided to the computer bus via devices 1242 and 1243 of Figure 11B.
  • tristate buffer 1253 receives input DOSAMP (a "write busy” signal set in the logic whenever a write operation is to be performed), and provides DOSAMP to output DAT15 in response to going “low.” When goes “high,” tristate buffer 1253 blocks transfer of data therethrough.
  • DOSAMP a "write busy” signal set in the logic whenever a write operation is to be performed
  • Figure 11D illustrates the read/write decoding and control circuitry in interface 30 of Figure 2, and will now be explained in conjunction with timing diagrams Figures HE and 11F, respectively.
  • inverters 1270-1273 receive inputs DAL12, DAL10, DAL9, DAL8 and DAL7, respectively, from the circuitry of Figure 11B.
  • NAND gate 1274 receives inputs BS7, DAL15, DAL14, DAL13 and the outputs of inverters 1270-1273, and decodes these inputs so as to derive a logic one output whenever inputs (address line inputs) DAL7-10, DAL12-15 indicate a predetermined block of addresses in processor 34 ( Figure 2).
  • inputs DAL7-DAL10 and DAL12-DAL15 indicate address blocks 164, Oxx or 164, lxx.
  • DAL0-DAL17 are address inputs from the processor 34 of Figure 2, and -- when the various DAL bits have the values shown in Table 1 (below) -- corresponding address blocks are indicated.
  • NAND gate 1284 the other input of which receives the decoder output of NAND gate 1274.
  • the arrangement of Figure HD also includes latch circuit 1292 which receives computer-generated addresses DAL1-DAL6 from the arrangement of Figure 11B.
  • Latch 1292 is strobed by NAND gate 1294 whenever either of flip-flops 1276 and 1286 are set.
  • WTBT ( Figure 11E) goes
  • NAND gate 1294 goes “high,” preferably within a maximum of 14 nanoseconds after AND gate 1280 has gone “high.” As indicated earlier, the "high" output of NAND gate 1294 strobes address data (from the processor 34 of Figure 2) into latch 1292.
  • NAND gate 1298 performs an AND operation with respect to inputs DOUT and RDYWRIT, and the output of NAND gate 1298 is provided -- via NAND gate 1300 (which performs an OR operation) -- to trigger one-shot device 1302.
  • One-shot device 1302 issues a short (preferably, one microsecond) negative pulse, the trailing edge of which triggers flip-flop 1304.
  • the Q output of flip-flop 1304 is provided to NAND gate 1306, the other input of which receives the inverted (via inverter 1308) output of NAND gate 1298.
  • NAND gate 1306 performs an AND operation with respect to the inputs thereto so as to issue a negative pulse, the leading edge of which triggers further one-shot device 1310.
  • the output of NAND gate 1306 is designated and this output is provided as one input to NAND gate 1312 which performs an OR operation with respect thereto.
  • the output of NAND gate 1312 is provided, via inverter 1314, as a strobe input to decoder 1316 which, at its A-C inputs, receives address inputs ADDR4-ADDR6 from latch 1292.
  • the further address outputs ADDR1-ADDR3 of latch 1292 are provided directly to a further decoder 1318 which is strobed (at its D input) by the Q 0 output of decoder 1316.
  • decoder 1316 as a result of the
  • ADDR4-ADDR6 inputs thereto and -- creates groups of strobe signals and Outputs are provided to corresponding decoders 192, 194 and 196 ( Figure 6C), wherein a decoding operation takes place so as to generate further appropriate strobe inputs STROBN for use in the DAC circuitry ( Figure 6E) of converter stage 56 ( Figure 2).
  • Output from decoder 1316 is provided to further decoder 1318, which also receives address inputs ADDR1-ADDR3 from latch 1292.
  • decoder 1318 As a result of its operation, decoder 1318 generates output (via amplifier 1320), output STROBO (a "control word” strobe generated via inverters 1322 and 1324 and NAND gate 1326), and output (a "status word” strobe).
  • the circuitry of Figure 11D decodes the address line inputs DAL1-DAL6, and generates the various groups of strobe signals (GRPOSTB, GRP1STB, GRP2STB and GRP3STB) which are variously sent to the logic section 62 ( Figures 2 and 6A-6E).
  • These groups of strobe signals insure that the computer processor 34 ( Figure 2) retrieves the proper data from, or stores the proper data in, proper address locations in memory, while properly timing the various transfer and analog-to-digital (or digital-to-analog) conversion functions. It will be recalled that the leading edge of the output of NAND gate 1306 triggered one-shot 1310.
  • flip-flop 1338 The Q output of flip-flop 1338 is accordingly a negative pulse which -- via NAND gate 1340 and inverter 1342 -- causes output to go "low,” the latter being provided to the computer processor 34 ( Figure 2) via the computer bus.
  • NAND gate 1340 also receives -- generated by the circuitry of Figure 11G during device (i.e., CEOG system) interrupt of the computer -- and performs an OR operation so that goes “low” either upon the occurrence of the Q negative pulse output of flip-flop 1338 or upon going “low.”
  • input DOUT (received via the computer bus, as explained above in discussion of Figure 11B) goes “low” (see the timing diagram of Figure 11E), so that the output of NAND gate 1300 goes “low.”
  • This "low” signal passes through NAND gate 1356 (acting as an OR gate) and inverter 1358 to reset flip-flops 1304 and 1338, resulting in output going "high” (or RPLY going “low”) -- see the timing diagram of Figure 11E.
  • signal SYNC also goes “low,” and the write (data out) sequence is completed.
  • Time lapse T 1A is preferably 75 nanoseconds at the minimum; T 1B is preferablly 66 nanoseconds maximum (including a 20 nanosecond set-up time); T 2A is preferably 25 nanoseconds minimum; T 3A is preferably 14 nanoseconds maximum; T 4A is preferably 25 nanoseconds minimum; T 5A is preferably 190 nanoseconds minimum; T 5B is preferably 220 nanoseconds minimum; and T 6 is preferably 120 nanoseconds maximum (typically, 60 nanoseconds).
  • the above preferred time durations are based on the particular hardware utilized in the preferred embodiment of the CEOG system, as discussed above with respect to Figures 11A-11D.
  • a read (data input to the computer) operation takes place as follows.
  • the computer generates address inputs DAL(N), which inputs are provided to latch 1292 of Figure 11D.
  • the computer processor 34 Figure 2) further generates SYNC which is provided as a strobe input to flip-flop 1286 (the Ready Read flip-flop). This strope (SYNC) sets flip-flop 1286 if its D input is a logic one on the leading edge of SYNC.
  • AND gate 1290 provides a logic one at the D input of flip-flop 1286 in response to detection of the desired address block (so long as BS7 is logic 1
  • NAND gate 1344 performs an AND operation with respect to inputs RDYREAD (from flip-flop 1286) and DIN (indicating that the computer is ready to receive input data) so as to generate DIN is provided to NAND gate 1344 via an RC (delay) network -- resistor 1346 and capacitor 1348 -- so as to insure a necessary time delay (preferably 60 nanoseconds) between the occurrence of SYNC and the leading edge of DIN. going "low” strobes decoder 1316 (via NAND gate 1312 and inverter 1314) so as to decode the inputs ADDR6-ADDR4 provided by latch 1292.
  • Decoders 1316 and 1318 function as previously described above to generate the groups of strobe signals and STROBO,
  • the signals generated by STROBEREAD each gate a particular set of data (e.g., STROB10 will gate data from channel 1 in the A/D section of Figure 6A) onto the data lines DAT0-DAT9.
  • lines DAT10-DAT15 will be zeroed by as shown in Figure 11C.
  • flip-flop 1304 is AND'ed with STROBEREAD in NAND gate 1350 to produce the signal that sets flip-flop 1338 via its S input. goes “low” in response to setting of flip-flop 1338, the latter acting via its Q output, NAND gate 1340 and inverter 1342.
  • Inverter 1354 is an open-collector device, which is to say that its output may be connected to other open-collector outputs which also generate (as seen later). It will be recalled that was used (in Figure 11B) to put data DAT0-DAT15 on the bus lines Once DIN goes “low,” STROBEREAD goes “low” (via the operation of NAND gate 1344 and inverter 1352). The reset (R) terminal of flip-flop 1338 will be accordingly enabled by NAND gates 1300 and 1356 (the latter of which performs an OR operation with respect to input ) and inverter 1358.
  • flip-flop 1338 will be reset, causing to go “high” via the operation of NAND gate 1340 and inverter 1342. Subsequently, the computer will cause SYNC to go “low, " and the read (data in) sequence will be completed.
  • Time durations disclosed therein are, in the preferred embodiment, as follows.
  • Time duration T 1F is preferably 54 nanoseconds maximum (in order to preclude a previous code (and thus, an erroneous code) from remaining in decoder 1316 of Figure 11B for too long a time duration);
  • T 2F is preferably 60 nanoseconds;
  • T 3F is preferably 83 nanoseconds; and
  • T 4F is preferably one microsecond.
  • the above-stated time durations are preferable based on the previously described circuitry of Figures 11A-11D.
  • Input is received by and sets flip-flop 1400 (the Data Ready flip-flop), while input DAL15 (the most significant bit from a control register to be described below) is received by and sets flip-flop 1402 (the Interrupt Enable flip-flop).
  • the Q outputs of flip-flops 1400 and 1402 are provided to NAND gate 1404 (which performs an AND operation), and the output thereof is provided -- via inverter 1406 -- as a clock input to set flip-flop 1408.
  • flip-flop 1408 The Q output of flip-flop 1408 is provided via inverter 1410 as output (see IRQ of the timing diagram of Figure 11H) . It is to be noted that flip-flop 1402 is clocked by STROBO generated by the circuitry of Figure 11D. is transmitted to the processor 34 as an "interrupt computer" command.
  • the circuitry of Figure 11G receives input IAKIN which (as mentioned above) is generated by a bus transceiver device similar to devices 1240-1243 of
  • Figure 11B in response to computer-generated input received over the computer bus.
  • IAKIN and the output of inverter 1406 are “high, " the output of NAND gate 1412 goes “low.”
  • Output is provided, via inverter 1414 and RC delay network 1416, to inverter 1418, the output of which is Accordingly, goes “low” in response to GATVEC going “low.”
  • going “low” causes (the output of inverter 1420, the input of which is connected to inverter 1414) to also go “low.”
  • flip-flop 1408 is reset in response to either going “low” or going “low,” such being accomplished via NAND gate 1409 and inverter 1411.
  • Resetting of the circuitry of Figure 11G is accomplished in response to either of three conditions: operation of a manual switch SWA (preferably, physically located in the interface 30) so as to reset the no-bounce switch 1424, resulting in generation of output via NAND gate 1426 (which performs an OR operation) and inverter 1428; INIT going "high,” as provided via inverter 1430 to NAND gate 1426; or turn-on of the system, activating a one second timer 1432 which provides an output via inverter 1434 to the NAND gate 1426 and inverter 1428.
  • a manual switch SWA preferably, physically located in the interface 30
  • input is connected, via an amplifier 1427 and a wired-OR connection, to one input of NAND gate 1426 so as to cause to go “low” in response to going "low,” thus achieving reset of the. circuitry of Figure 11G in response to resetting of the ADC circuitry in converter stage 56 ( Figure 2).
  • inverter 1430 which receives the input INIT
  • the output of inverter 1430 is connected to the input of amplifier 1436, the output of which produces (previously discussed above).
  • the circuitry of Figure 11G further comprises a flip-flop 1437 which is clocked by input STROBO, and set by input DAL14 -- the fourteenth bit of a control word register (to be discussed below) in computer processor 34 of Figure 2. As a result of being set, flip-flop 1437 generates a "low" output which is bit 15 in a status word register (also to be discussed below) .
  • the preferred embodiment of this invention includes a PDP 11/03 central processing unit as processor 34, a UT-52 terminal as display 38/keyboard 44, an RXV-11 disk unit as floppy disk 42, and the RT-11 software package as computer programs 36 (the latter being readily available from Digital Equipment Corporation).
  • the circuitry of Figures 11A-11G constitutes an addition to the memory locations of the computer. A summary of the additions is shown in Table 2 (below).
  • control word register (mentioned in Table 2 ) is a 16-bit, write-only register, organized from bit 15 through bit 0, as follows:
  • Bit 15 Interrupt Enable bit -- this bit will be reset whenever the logic section 62 ( Figures 10A-10O) or the computer processor 34 ( Figure 2) initializes the system. Otherwise, it is set/reset by the computer programs (software) 36. This bit is actually generated -- in the preferred embodiment -- by flip-flop 1402 in Figure 11G.
  • Bit 14 A "single step" bit provided to the ADC in converter 56 ( Figure 2). This bit is generated -- in the preferred embodiment -- by flip-flop 1437 and results in generation of signal CMPSAMP (via data bit DAL14 of Figure 11G), which is one of the signals which generates SAMPLE (see Figure 6D), the latter being utilized (it will be recalled) in the analog-to-digital conversion process
  • DOUT13 to the arrangement of Figure 10 J so as to cause generation of signal 5MSSAMP, calls for the generation of data at the rate of one sample point (six channels) every 5 milliseconds. It will be recalled that DOUT13 turns on flip-flop 970, triggering one-shot 978, so as to generate 5MSSAMP.
  • Bit 12 A Flash bit is provided, as input DOUT12 (CMPSHTR), to flip-flop 1022 of Figure 10L, so as to generate output SHUT, resulting in pulsing of the flasher 70.
  • Bit 11 A 2.5 Millisecond Sample bit is provided as input DOUTH to flip-flop 972 of Figure 10J. Flip-flop 972 accordingly -- via its Q output -- enables relay (solenoid/switch) 982, so as to adjust the timing of one-shot 980. As a result, the sampling time is decreased from 5 milliseconds to 2.5 milliseconds.
  • Bit 10 A bit DOUT10 is provided to flip-flop 1020 of Figure 10L, to set that flip-flop. As a result, flip-flop 1020 -- via its Q output -- generates output RECORDING. When RECORDING goes “low,” display indicator DS9 of Figures 9A and 9B is illuminated thus indicating that the system is in the "recording" mode of operation. Bit 9: A Copy bit, which causes the hard-copy printer 40 ( Figure 2) to make a printout of test results. Bits 8-0: Bits 5-8 are "spare" bits available for use in accomplishing other functions or display indications, as would be judged by one of ordinary skill in the art to be necessary with respect to the CEOG system.
  • bits 0-4 -- it will be noted -- are stored in latch circuit 1254 of Figure 11C as written thereinto by STROBO. Thus, these bits may be read back by the computer processor 34 through tristate buffer 1253, as enabled by STROBl.
  • the status word register is a 16-bit, read-only register, organized from bit 15 through bit 0, as follows:
  • Bit 15 A Write Busy bit, which must be checked before the computer writes a word into any of the registers (except for the control register). If bit 15 is "on,” this indicates that the CEOG system is involved in storing a word transmitted by the computer processor 34 ( Figure 2) during the last "write” command. In the preferred embodiment, bit 15 is provided by flip-flop 1437 of Figure 11G. It is to be noted that output of flip-flop 1437 becomes computer input DAT15 via tristate buffer 1253 of Figure 11C. Bit 14: A Stripe-On bit indicating that the stripe cage 76 in optokinetic device 16 is turning.
  • switch Sll Figures 9A and 9C -- when turned on by the operator -- and is provided to the computer processor 34 -- via NAND gate 912, inverter 918, NAND gate 924 and inverter 928 of portion L4 of Figure 10H -- as input DATIN14.
  • Bit 12 A Copy Busy bit, indicating that the hard-copy printer 40 ( Figure 1) is busy printing from the last command.
  • Bits 11-0 These bits are indicated as spare bits, but can be utilized for providing various other control functions/display indicators as would be obvious to one of ordinary skill in the art.
  • the Data-in registers are made up of the above-specified (Table 2) I/O addresses, which correspond to respective channels 1-8 of information.
  • digital channel 1 corresponding to analog input AMPOUTl
  • channel 2 contains right vertical eye movement test data
  • channel 3 contains left horizontal eye movement test data
  • channel 4 contains right horizontal eye movement test data
  • channels 5 and 6 contain VER test data
  • channel 7 correspond to analog input TACH2
  • channel 8 contains cage speed test data.
  • Data Out channels 1-8 (referred to in Table 2 above) include digital data 'from the computer processor 34 of Figure 2 for conversion in converter stage 56.
  • Discussion of channels 5-8 is eliminated as not being critical to the full disclosure of this invention; however, it will be obvious to one of ordinary skill in the art that channels 5-8 could be utilized for the development of various other analog functions.
  • the Move X register (referred to in Table 2) is a 16-bit, write-only register, organized (in the preferred embodiment) as follows: Bit 10: Go X mirror -- instructs the mirrors 14 (and associated driving circuitry) to begin scanning in the X direction with its own sine wave. See input DOUT10 to flip-flop 1020 in Figure 10L, resulting in generation of XSINE. Bit 11: The CMPSINE bit which instructs the mirrors 14 that the computer processor 34 is to control the X deflection of the mirrors 14 so that the 10 least significant bits of the MOVX register are in control of operation of the X-deflection mirrors.
  • Bit 12 The CMPSHTR bit which opens the shutter 66 ( Figure 2) to allow the light from laser 12 to pass therethrough, usually used in conjunction with bits 10 or 11 above. See input DOUT12 (CMPSHTR) applied to flip-flop 1022 in Figure 10L, with resultant generation of SHUT by NPN transistor 1036.
  • Bit 13 YSCAN bit which causes the Y-deflection mirrors to scan -- similar to Bit 10 except that it controls scanning in the Y direction. See input YSCAN to amplifier 1110 in Figure 10M, with subsequent generation of mirror driving output YDRIVE.
  • Bits 0-9 These 10 bits are provided by the processor 34 -- via interface 30 -- to converter stage 56 ( Figure 2). Specifically, in the preferred embodiment, bits 0-9 are provided as inputs DTOA0-DTOA9 to circuitry of the type illustrated as DAC circuitry 300 of Figure 6E, the data being strobed into latch circuits 302 and 303 by a strobe input STROBMX (similar to STROBN) .
  • the digital data is digital- to-analog converted to develop analog output MOVX (similar to BIASN of Figure 6E), thus providing an analog voltage (preferably, having a value of from -5 volts (000...000) to +5 volts
  • Position X register (referred to in Table 2) is a read-only register which feeds back (to the computer processor 34 of Figure 2) information relative to the position of the X-scaiming mirrors 14. The 10 least significant bits of this register give the relative X position of the mirrors. However, in the preferrred embodiment, either the Go bit or the single-step bit (both of which were referred to above) must be turned on, and an interrupt received, before the 10 least significant bits of the Position X register contain up-to-date data. (This is true of all the outputs of A/D converters 56' of Figure 6A).
  • the Move Y register is a write-only register used for controlling scanning of the mirrors 14 in the Y direction.
  • the 10 least significant bits (0-9) of this register are D/A converted -- in the same manner as described above for bits 0-10 controlling X direction scanning -- to form MOVY, an analog voltage which operates in conjunction with the Y position potentiometer (under the control of the operator) -- see Figures 9A-9E -- to move the Y-deflection mirrors. See potentiometer 504 in circuit 502 of Figure 9C.
  • Position Y register is a read-only register, the 10 least significant bits of which give the relative Y position of the mirrors 14. As was the case with the Postion X register, either the Go bit or the single-step bit must be on, and an interrupt received, before the 10 least significant bits of the Position Y register have up-to-date data contained therein.
  • the CEOG system address decoding scheme is set forth in Table 3 (below). It is to be noted that, in the preferred embodiment, memory locations 164,000 through 164,176 are not true memory locations in processor 34 ( Figure 2).
  • locations 164,000-164,016 include the control word register, status word register, and chair control register, and addressing of these locations is accomplished by the decoding NAND gate 1274, decoders 1316, 1318, etc. of Figure 11D (previously described) which produce STROB0, STROB1, etc. to send data to the proper address.
  • locations 164,020-164,036 are channels 1-8 of data input from the CEOG system to the processor 34, such data input being, of course, analog-to-digital converted prior to input.
  • Locations 164,040-164,056 are channels 1-8 of data output from the processor 34 to the CEOG system, such data output being, of course, digital-to-analog converted after output.
  • locations 164,060-164,076 are the Move X register, Position X register, Move Y register, and Position Y register (previously discussed above).
  • address. data bits D6-D0 represent the seven least significant bits of a data address for addressing any one of the locations 164,000-164,076. It is to be noted that since, in the preferred embodiment, only alternate locations
  • bits D6-D1 correspond to address line inputs DAL6-DAL1 provided as data address line inputs provided by the computer bus to bus transceiver devices 1240-1243 of Figure 11B (discussed above), and further correspond to inputs ADDR6-ADDR1 provided to decoders 1316 and 1381 of Figure HB (also discussed above).
  • strobe signals GRPOSTB, GRPISTB, GRP2STB and GRP3STB are developed -- specifically, STROBO-STROB7, STROB10-STROB17, STROB20-STROB27 and STROB30-STROB37.
  • the CEOG system of Figure 2 includes a processor 34 which is preferably software-controlled by computer programs 36.
  • computer programs 36 preferably use the RT-11 software package (provided by Digital Equipment Corporation for use with the preferred processor unit PDP11/03).
  • Figures 12A and 12B are general flowcharts of the test program and analysis program, respectively, implemented by the processor 34 of the CEOG system of Figure 2, as a preferred implementation of computer programs 36. That is, computer programs 36 of Figure 2 are divided into a Run program ( Figure 12A) by means of which various selected tests are performed on the patient, and an Analysis program ( Figure 12B) by means of which the test results are analyzed/processed and a display or hard copy of the test results in a convenient format is provided to the test administrator.
  • Figures 12A and 12B Prior to discussion of Figures 12A and 12B, a few additional introductory comments are appropriate.
  • RUN TEST calls up the test process for presenting the stimulus to the patient and recording the patient's reaction
  • RUN ANALYSIS calls up the analysis process, by which the patient's reaction is analyzed and recorded on the patient's record
  • RUN REVIEW calls up the review process, by which the patient's record is reviewed, a directory of patients processed can be displayed, and a hard copy replication of the patient's records can be made.
  • the processor 34 is preferably programmed to provide the operator (test administrator) with the capacility of choosing which of the three processes (test, analysis or review) to enter by means of entry of an appropriate alphabetical character (e.g., T, A or R) on the keyboard 44 ( Figure 2).
  • an appropriate alphabetical character e.g., T, A or R
  • test process will be commenced by loading the system and data disks, and "booting" the system -- block 1500 of Figure 12A.
  • the present data (such as the present date) is then entered into the computer's file record -- block 1501.
  • the test process is formally commenced by starting the system (e.g., by typing RUN SYS on the keyboard 44 of Figure 2) -- block 1502.
  • a display of a patient data form on display device 38 ( Figure 2) will then occur -- block 1503.
  • the test administrator then enters various patient information (such as name, ID, etc.) onto the data form from the keyboard 44 -- block 1504.
  • test menu -- block 1505 Upon completion of patient data input, the system displays a test menu -- block 1505 -- such as the following:
  • T time scale -- follow with 5, 7.5, 10. 12:5, 15, 17.5 or 20 seconds -- otherwise time scale is 2.5 seconds.
  • T time scale: follow with 5, 7.5, 10, 12.5, 15, 17.5 or 20 seconds; otherwise, time scale is 2.5 seconds.
  • T time scale: follow with 5, 7.5, 10, 12.5, 15, 17.5 or 20 seconds; otherwise, time scale is 2.5 seconds.
  • T time scale: follow with 5, 7.5, 10, 12.5, 15, 17.5 or 20 seconds; otherwise, time scale is 2.5 seconds.
  • Lower rotating drum by operator control section 450 of Figure 9A).
  • turn potentiometer adjustment knob P2 in Figure 9A
  • TP perform three revolutions of the drum for the pattern test.
  • T time scale: follow with 5, 7.5, 10, 12.5, 15, 17.5 or 20 seconds; otherwise, time scale is 2.5 seconds.
  • L rotate chair left: take horizontal data at end.
  • RHV rotate chair right: take horizontal and vertical data at end.
  • LHV rotate chair left: take horizontal and vertical data at end. It is to be noted, that, in the chair rotation test, data may be taken during rotation and also after the chair has stopped.
  • the chair Presuming that oscillation -- block 1516 -- has been chosen, the chair will be automatically oscillated for four cycles, and data will be taken during chair motion.
  • the procedure is preferably as follows:
  • T time scale: follow with 5, 7.5, 10, 12.5, 15, 17.5 or 20 seconds; otherwise, time scale is 2.5 seconds.
  • Blinking letter (on display 38 of Figure 2) indicates next test to be done in the normal VER sequence.
  • B8 both eyes open, 128 flashes, one per second.
  • B4 both eyes open, 64 flashes, one per second.
  • R4 right eye occluded, 64 flashes, one per second.
  • L4 left eye occluded, 64 flashes, one per second.
  • T(f,r) test VER using number of flashes f (f is 16, 32, 64 or 128) and flashes per second r (r is 1/2, 1 or 2).
  • M(m) on display, choose magnification factor m.
  • test administrator is required by the test program to provide parameters (such as chair rotation speed via potentiometer adjustment knob PI of Figure 9A, etc.)
  • parameters such as chair rotation speed via potentiometer adjustment knob PI of Figure 9A, etc.
  • the administration of pursuit tests, chair motion tests and visual evoked response (VER) tests which previously were relatively inefficient in their administration -- can be very quickly and efficiently performed.
  • VER visual evoked response
  • the integrated CEOG system of the present invention is highly flexible in that, as previously discussed and described in great detail above, the test administrator always has the option of manually administering one or more of the particular tests by manipulation of the various controls in operator control section 450 of Figure 9A.
  • immediate display of the test results in either mode of operation -- automated or manual test administration -- immediate display of the test results, in a graphical format readily usable by the attending test administrator or physician, is provided (as illustrated on display device 38 of Figure 1).
  • the administrator or physician is able to: (1) determine immediately if the test has been properly administered, (2) determine whether or not the patient has validly received/reacted to the test stimuli presented, and (3) thus, determine whether further testing (or repeated testing) is necessary.
  • Header information is read from the disk 42 ( Figure 1) -- block 1550.
  • Header information is displayed -- block 1551.
  • N is compared to zero (block 1557); then, if N is equal to or greater than zero, the Nth record is obtained from the disk (block 1559), while if N is less than zero, a further decision (block 1558) is made. Specifically, if -1 is equal to or less than N, the system returns to START (block 1550), while if -1 is greater than N, the system stops. Once the Nth record from disk is obtained
  • VER -- block 1561 the system displays two channels with labels and scaling -- block 1563 -- and enters a "print" routine (to be subsequently discussed).
  • test is a pursuit test
  • mirror position H or V
  • chair rotation is called for
  • chair motor speed is displayed -- block 1566 --
  • print routine the following procedure applies:
  • the "group size” is printed -- block 1567.
  • the print routine would be entered if the test question was a VER test (see discussion above).
  • the system prints the message "position point and its disposition" -- block 1569.
  • the system displays a cursor -- block 1570.
  • the operator enters one of three alphabetic characters: S, E or F -- block 1571.
  • group size is made -- block 1573. If group size equals 1, the system prints the message "enter label” (block 1574), the operator enters a character (block 1575), the system displays the label so entered (block 1576 ) , and the system returns to "display cursor" (block 1570).
  • the channel information is saved, and initiate next channel is executed -- block 1580 -- followed by a decision (block 1581) as to whether the channel is less than, equal to or greater than 4. If the channel is equal to or less than 4, a return to "display cursor" (block 1570) is executed.
  • the system computes and displays times and velocities (block 1582), and prints the message "save?" (block 1583).
  • Test program of Figure 12A and Analysis program of Figure 12B are implemented by various computer programs 36 ( Figure 1) -- preferably, a master control program, individual test programs for the respective EOG and VER tests, and individual main analysis programs for the respective EOG and VER tests. More specifically, the computer programs 36 of
  • Figure 1 are implemented, in the preferred embodiment, by the following: a master control and stored format (for printout) program; a program for calling forms for display; an EOG test program; a VER test program; a main analysis program (for EOG test analysis); a main analysis program (for VER test analysis); and a display program.

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Abstract

Un système informatisé électro-oculographique se compose d'une chaise rotative (2) pour le patient, entourée d'un écran cylindrique (18) sur lequel des projecteurs (12, 16) projettent les stimulus optiques désirés. Les signaux produits par les mouvements des yeux sont captés par des électrodes (6a-1), amplifiés (24, 26), étalonnés (46), filtrés (26) et numérisés (28) pour l'interface (30) avec un ordinateur (32). Les tests à effectuer sont sélectionnés au moyen d'un clavier (44) qui commande l'ordinateur en fonction de ses programmes (36). Les signaux produits par l'ordinateur sont ensuite affichés (38) et/ou enregistrés (40, 42).
EP19820901258 1982-03-22 1982-03-22 Systeme informatise electro-oculographique(ceog). Withdrawn EP0104166A4 (fr)

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PCT/US1982/000343 WO1983003341A1 (fr) 1982-03-22 1982-03-22 Systeme informatise electro-oculographique (ceog)

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EP0104166A1 true EP0104166A1 (fr) 1984-04-04
EP0104166A4 EP0104166A4 (fr) 1986-03-04

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IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, vol. BME-28, no. 5, May 1981, pages 390-395, IEEE, New York, US; J.R. TOLE et al.: "A microprocessor-controlled vestibular examination chair" *
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See also references of WO8303341A1 *

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EP0104166A4 (fr) 1986-03-04

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