EP0072644A2 - Halbleiterchipträger - Google Patents

Halbleiterchipträger Download PDF

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Publication number
EP0072644A2
EP0072644A2 EP82304063A EP82304063A EP0072644A2 EP 0072644 A2 EP0072644 A2 EP 0072644A2 EP 82304063 A EP82304063 A EP 82304063A EP 82304063 A EP82304063 A EP 82304063A EP 0072644 A2 EP0072644 A2 EP 0072644A2
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EP
European Patent Office
Prior art keywords
substrate
bus
lead
semiconductor chip
reference voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP82304063A
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English (en)
French (fr)
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EP0072644B1 (de
EP0072644A3 (en
Inventor
Dimitry G. Grabbe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TE Connectivity Corp
Original Assignee
AMP Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/293,052 external-priority patent/US4417266A/en
Priority claimed from US06/314,921 external-priority patent/US4419818A/en
Application filed by AMP Inc filed Critical AMP Inc
Publication of EP0072644A2 publication Critical patent/EP0072644A2/de
Publication of EP0072644A3 publication Critical patent/EP0072644A3/en
Application granted granted Critical
Publication of EP0072644B1 publication Critical patent/EP0072644B1/de
Expired legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L23/64—Impedance arrangements
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/48233—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a potential ring of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Definitions

  • This invention relates to substrates for semiconductor chips, and specifically to a power and ground bus structure where individual resistors between signal leads and the ground bus are selectively connected and resistance values varied.
  • Chip carriers for integrated circuit semiconductor chips are well known in the art and are widely used.
  • a common type of semi-conductor chip carrier comprises a substrate and an array of conductive leads thereon which extend from plural locations at the edges of said substrate toward the center thereof. See, for example, U.S. Patent No. 4,195,193. The leads are connected to bonding pads on semiconductor chips bonded to the center of the chip carrier.
  • leads on the substrate are thin and easily overloaded, it has been necessary to use a plurality of leads on the chip carrier to provide power and ground voltages to appropriate pads on the chip. Many leads in parallel have been used to minimize lead resistance, thus limiting the number of leads which may be utilized as signal leads.
  • Signal leads on prior art substrates are made up of two parts.
  • the first part is a conductor strip which is deposited on the substrate and extends from the outer edge of the substrate to the inner edge where the chip is attached.
  • the second part is a fine wire or lead, referred to as an elevated lead, which is extended in air from the inner edge of the laminated strip to the chip.
  • a resistor to ground referred to as a terminating lead resistor, is generally connected to the signal lead beyond the outer edge of the substrate on the printed circuit board. This arrangement results in an unterminated transmission line with a discontinuity in the impedance at the point where the resistor lead is attached. The remaining connection from this point on is referred to as an unterminated stub.
  • a chip carrier as defined above further comprises a first reference voltage bus toward the center of the substrate, the first reference voltage bus being connected to a lead.
  • the first reference voltage bus is preferably a ground bus and substantially surrounds a second reference voltage bus which is preferably a power bus which surrounds the center of the substrate.
  • the chip carrier defined above is further characterized in that the conductive leads are mostly signal leads, the substrate having resistive material bonded thereon between the signal leads and the first reference voltage bus, whereby the resistive material may be selectively removed to form discrete paths of desired resistance between at least one signal lead and the reference voltage bus.
  • This aspect of the present invention involves a technique which enables signal leads to be terminated through a unique resistor to ground at the point where the deposited signal lead changes to the elevated lead going to the chip.
  • the technique consists of two steps. The first step is to terminate all the signal leads to one side of a resistor zone which is terminated to ground bus on its other side. The next step is to use a laser or some such method beam to dissect the resistor zone into individual resistors, one resistor for each signal lead. The value of each lead resistor will then be adjusted or trimmed to the required value. This will enable each lead to be terminated to ground through a unique resistor.
  • the material left between the laser cut and the ground bus will be at ground potential and thereby acts as a reference ground plane. This minimizes the distance over which the elevated lead is not referenced to ground, thus reducing the discontinuity and reflectance of high frequency signal.
  • Figure 1 shows the substrate 10 of the present invention prior to placement and connection of a semiconductor chip thereon.
  • the substrate is formed of appropriate dielectric material such as beryllium oxide, aluminum oxide, or other suitable dielectric.
  • the circuitry is formed thereon by a standard process such as photoetching, printing, or a copper lead frame is bonded to the substrate by the procedure described in U.S. Patent Nos. 3,744,120; 3,766,634; 3,911,553; 3,994,430; and 4,129,243.
  • the lead frame is oxidized on one side initially and is positioned on the ceramic substrate 10.
  • the lead frame and substrate are then heated to about 1068°C, at which temperature the copper oxide melts and fuses with the substrate.
  • the chip support pad 12 occupies the center of the substrate 10 and is surrounded completely by the power bus 22 which is connected to one corner of the substrate by the power lead 23.
  • the power bus 22 is surrounded almost completely by the ground bus 18 which is connected to the opposite corner by the ground lead 19.
  • the ground bus 18 is broken where the power lead 23 passes through, at which point the mounting pad 20 on the ground bus 18 lies adjacent the pad 24 on the power bus.
  • the pads 20, 24 serve as mounting means for the attachment of a decoupling capacitor between the power and ground structures.
  • a plurality of signal leads 14 extend between each outer edge 17 of the substrate 10 and the ground bus 18, being separated therefrom by four elongate resistor zones 26 formed on the substrate. Thus, the signal leads 14 are connected to the ground bus 18 through the resistor zones 26.
  • the deposited resistor zones 26 are formed from material of the thick or thin film type which is frequently a composition of carbon with two metal oxides and a binder.
  • the resistor zones can be screen printed and fixed onto the substrate by conventional thick film techniques as is well known in the hybrid circuit art.
  • FIG. 2 shows the function of the resistor zones 26 with several examples.
  • laser cuts 27 are formed in a resistor zone 26 to isolate discrete portions of the resistor zone between each signal lead 14 and the ground bus 18.
  • a laser cut 27a may completely cut off the signal lead 14a from the ground bus 18, leaving a ground plane 29, as shown in section in Figure 3.
  • a defined resistor 28 may be extended between the signal lead 14b and the ground bus 18, by using a zig-zag laser cut 27b.
  • a trimming laser cut 27c may be used to slightly alter the value of the resistance from signal lead 14c to ground 18.
  • Various leads 32, 33, 34 are shown connected to the semiconductor chip 13.
  • Lead 32 connects a signal lead 14 to the chip 13, while lead 33 is a power lead which provides power directly to the chip 13 and lead 34 is a ground lead which provides a direct ground connection from the chip 13. All leads 32, 33, 34 are elevated in the manner of lead 32 as will be explained below.
  • FIG. 3 shows an elevated lead 32 which connects each of the signal leads 14 to the semiconductor chip 13 mounted on the chip support pad 12.
  • the elevated wire lead 33 is bonded at both ends and passes over the ground bus 18 and power bus 22.
  • the elevated wire leads 32 are disposed roughly parallel to the defined resistors 27.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
EP82304063A 1981-08-14 1982-08-02 Halbleiterchipträger Expired EP0072644B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US293052 1981-08-14
US06/293,052 US4417266A (en) 1981-08-14 1981-08-14 Power and ground plane structure for chip carrier
US06/314,921 US4419818A (en) 1981-10-26 1981-10-26 Method for manufacturing substrate with selectively trimmable resistors between signal leads and ground structure
US314921 1981-10-26

Publications (3)

Publication Number Publication Date
EP0072644A2 true EP0072644A2 (de) 1983-02-23
EP0072644A3 EP0072644A3 (en) 1983-03-16
EP0072644B1 EP0072644B1 (de) 1986-03-26

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EP82304063A Expired EP0072644B1 (de) 1981-08-14 1982-08-02 Halbleiterchipträger

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EP (1) EP0072644B1 (de)
DE (1) DE3270106D1 (de)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0135089A2 (de) * 1983-09-22 1985-03-27 International Business Machines Corporation Apparat zum Herstellen einer Mehrzahl von Spannungsebenen auf ein dielektrisches Mehrschicht-Substrat
WO1985004522A1 (en) * 1984-03-22 1985-10-10 Mostek Corporation Impedance-matched leads
EP0317038A1 (de) * 1987-11-20 1989-05-24 Laboratoires D'electronique Philips Stiftloses Gehäuse für ultra-schnelle integrierte Schaltung
WO1990016080A1 (en) * 1989-06-15 1990-12-27 Cray Research, Inc. Chip carrier with terminating resistive elements
GB2244404A (en) * 1990-04-30 1991-11-27 Motorola Inc Precision terminator circuit
USRE34395E (en) * 1989-06-15 1993-10-05 Cray Research, Inc. Method of making a chip carrier with terminating resistive elements

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4129243A (en) * 1975-07-30 1978-12-12 General Electric Company Double side cooled, pressure mounted semiconductor package and process for the manufacture thereof
EP0018174A1 (de) * 1979-04-12 1980-10-29 Fujitsu Limited Hochfrequenz-Halbleiteranordnung auf einem isolierenden Substrat
WO1981000949A1 (en) * 1979-09-20 1981-04-02 Western Electric Co Double cavity semiconductor chip carrier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4129243A (en) * 1975-07-30 1978-12-12 General Electric Company Double side cooled, pressure mounted semiconductor package and process for the manufacture thereof
EP0018174A1 (de) * 1979-04-12 1980-10-29 Fujitsu Limited Hochfrequenz-Halbleiteranordnung auf einem isolierenden Substrat
WO1981000949A1 (en) * 1979-09-20 1981-04-02 Western Electric Co Double cavity semiconductor chip carrier

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 5, October 1978, pages 1895-1897, New York, USA; S. MAGDO: "Low inductance module". *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 1A, June 1981, pages 46-48, New York, USA; J.R. CAVALIERE et al.: "High-performance single-chip module". *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0135089A2 (de) * 1983-09-22 1985-03-27 International Business Machines Corporation Apparat zum Herstellen einer Mehrzahl von Spannungsebenen auf ein dielektrisches Mehrschicht-Substrat
EP0135089A3 (de) * 1983-09-22 1986-08-27 International Business Machines Corporation Apparat zum Herstellen einer Mehrzahl von Spannungsebenen auf ein dielektrisches Mehrschicht-Substrat
US4649417A (en) * 1983-09-22 1987-03-10 International Business Machines Corporation Multiple voltage integrated circuit packaging substrate
WO1985004522A1 (en) * 1984-03-22 1985-10-10 Mostek Corporation Impedance-matched leads
EP0317038A1 (de) * 1987-11-20 1989-05-24 Laboratoires D'electronique Philips Stiftloses Gehäuse für ultra-schnelle integrierte Schaltung
FR2623662A1 (fr) * 1987-11-20 1989-05-26 Labo Electronique Physique Dispositif de connexion pour circuits integres numeriques ultra-rapides
WO1990016080A1 (en) * 1989-06-15 1990-12-27 Cray Research, Inc. Chip carrier with terminating resistive elements
USRE34395E (en) * 1989-06-15 1993-10-05 Cray Research, Inc. Method of making a chip carrier with terminating resistive elements
GB2244404A (en) * 1990-04-30 1991-11-27 Motorola Inc Precision terminator circuit
GB2244404B (en) * 1990-04-30 1993-07-21 Motorola Inc Precision terminator circuit

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EP0072644B1 (de) 1986-03-26
DE3270106D1 (en) 1986-04-30
EP0072644A3 (en) 1983-03-16

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