Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/77—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
  • H04N9/78—Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/02—Digital function generators
  • G06F1/03—Digital function generators working, at least partly, by table look-up
  • G06F1/0307—Logarithmic or exponential functions
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/02—Digital function generators
  • G06F1/03—Digital function generators working, at least partly, by table look-up
  • G06F1/035—Reduction of table size
  • G06F1/0353—Reduction of table size by using symmetrical properties of the function, e.g. using most significant bits for quadrant control
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/02—Digital function generators
  • G06F1/03—Digital function generators working, at least partly, by table look-up
  • G06F1/035—Reduction of table size
  • G06F1/0356—Reduction of table size by using two or more smaller tables, e.g. addressed by parts of the argument
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T3/00—Geometric image transformations in the plane of the image
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/39—Control of the bit-mapped memory
  • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N9/00—Details of colour television systems
  • H04N9/64—Circuits for processing colour signals
  • H04N9/646—Circuits for processing colour signals for image enhancement, e.g. vertical detail restoration, cross-colour elimination, contour correction, chrominance trapping filters
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2101/00—Indexing scheme relating to the type of digital function generated
  • G06F2101/04—Trigonometric functions
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2101/00—Indexing scheme relating to the type of digital function generated
  • G06F2101/08—Powers or roots
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F2101/00—Indexing scheme relating to the type of digital function generated
  • G06F2101/10—Logarithmic or exponential functions

Definitions

• the present invention relates to digital calculation using a digital memory, such as a read-only memory (ROM) for table look-up of non-linear functions of variables and, more particularly, to the reduction of the size of the memory required for given number of places of resolution in the looked-up function.
• a digital memory such as a read-only memory (ROM) for table look-up of non-linear functions of variables and, more particularly, to the reduction of the size of the memory required for given number of places of resolution in the looked-up function.
• An example of such digital calculation occurs in the calculation of the angular coordinate in a scan conversion from Cartesian to polar coordinates, as may be done for addressing television graphic display memory organized to be addressed in polar coordinates.
• Cartesian coordinates x and y are directed from left to right and from top to bottom of screen, respectively, in the left-hand coordinate system customarily employed by- television engineers; and it is convenient to choose the origin at the center of screen supposing the display memory is to cover the entire television screen.
• the • origins of the Cartesian-coordinate and polar-coord ' inate systems should preferably coincide at a point in image space. Radial polar coordinate r is measured outward from this point, and angular polar coordinate 9 is measured turning about this point counterclockwise from positive half of x axis, in keeping with the use of left-hand coordinates.
• the angular coordinate ⁇ could be looked up from ROM responsive to x and y. Supposing the display to comprise 512 lines with 512 picture elements (or "pixels", for short) per line, then a quadrant of 9 could be looked up from ROM using eight bits of x and eight bits of y as input. About fourteen bits of output are required to define 9 with the resolution found b experiment to be required for extracting graphic images from display memory addressed in polar coordinates.
• the nine most significant bits of this angular coordinate are xise ⁇ together with eight bits of radial coordinate as input to a ROM storing u a graphic image that fills the display screen, and five next most significant bits of this angular coordinate are used in two-dimensional interpolation betv/een video samples from spatially adjacent locations in the ROM to avoid visible discontinuities in edges of the graphic image as it appears on the display screen.
• About sixty-four ROM's of the conventional size with eleven-bit inputs and eight- bit outputs would be required for such direct lcok-up of 9.
• the angular coordinate 9 could be calculated by first dividing y and x and then using a ROM to look up tan ⁇ ⁇ -(y/x). Several division .
• ROM substantially less ROM is required if one looks up 9 in ROM responsive to log2 (y/x) input as the tan ⁇ - * - ⁇ nti-log [log2 (y/x) ]) . This is because 9 is more linear respective to log29 (y/x) -. Q than to y/x, so that adequate resolution in 9 can be obtained through the full range of log y/x with fewer bits than through the full range of y/x.
• a general aspect of the invention concerns the looking up of a non-linear function of a first variable from ROM not being done directly using the first variable as input to the ROM. Rather, responsive to said first variable, a second variable is generated (either from ROM or by calculation) to be applied to the ROM. This second variable is dependent from said first variable in such a way that responsive to change in the first variable the rate of change of said second variable approximates the rate of change in said non-linear function of said first variable. Fewer bits of resolution in the ROM input are required, using the second variable rather than the first variable as input, in order to describe the non-linear function with no more than a given level of quantization error.
• a digital memory which contains digital data words representative of the desired transfer characteristic of the signal processor.
• Digital signals which are to be processed are applied to the address inputs of the memory, producing cutpur signals in conformance with the desired transfer characteristic.
• Advantage is taken of the symmetrical nature of the transfer characteristic to reduce the size of the emorv.
• Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory, and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit.
• FIGURE 1 is a block diagram of a television display system for displaying an image taken from memory and rotated through a programmable angle in which apparatus the invention finds use;
• FIGURE 2 is a sketch useful in understanding the forms taken by the Cartesian coordinates ⁇ describing the rotatable image prior to its rotation;
• FIGURE 3 is a block diagram of scan generator and scan converter circuitry used for addressing a memory storing information organized according to polar coordinates, which scan converter embodies the invention
• FIGURE 4 is a schematic diagram of a digital signal processor constructed in accordance with the principles of the present invention
• FIGURES 5 and 6 are -data tables used to explain the embodiments of FIGURES 3 and 4;
• FIGURE 7 is a block diagram of a modification that can be made to the FIGURE 3 scan converter.
• FIGURE 8 is a block diagram of a memory system useful in connection with the FIGURE 1 apparatus.
• display memory 10 stores information read out at video rates to the inp ⁇ t of digital-to-analog converter (DAC) 11 to be converted to video for application to a video amplifier 12, the output of which drives the electron gun of a cathode ray tube (CRT) 13.
• CRT .13 has a screen 14 raster-scanned by the electron beam emanating from its electron gun.
• the raster-scanning is -ypically accomplished using horizontal and vertical deflection coils 15 and 16 supplying sawtooth currents from horizontal and vertical sweep generators 17 and 18, respectively. It is customary to use resonant circuits including the deflection coils in these generators and to synchronize the sweeps with horizontal and vertical synchronizing pulses supplied by timing control circuitry 19.
• Circuitry 19 generally includes frequency-dividing circuitry for generating these synchronizing pulses at rates subharmonic to master clock signals provided from a master clock 20, which customarily comprises a crystal oscillator which operates at the pixel scan rate or a multiple thereof.
• Memory 10 is addressed during its readout by the integral portions of radial and angular coordinates R and ⁇ , respectively, supplied as output from a scan converter 21 responsive to x and y coordinates supplied to it as input from a scan generator 22.
• Scan generator 22 generates a sub-raster — i.e., a raster scanning of x and y addresses which may or may not be co-extensive- with the raster scanning of the display screen by electron beam.
• These x and y coordinates are generated by scan generator 22 at pixel scan rate during each line scan of CRT 13 screen 14 in the trace direction, as timed from timing control circuitry 19.
• Scan converter 21 is programmable as to the degree of rotation (expressed as angle ⁇ ) of the image to be read out of display memory 10.
• This angle ⁇ is added to the angular ⁇ coordinates descriptive of unrotated image to obtain the angular 9 coordinates descriptive of rotated graphic image. That is, in the system being described tan-l(y/x) defines ⁇ , rather than , with 9 being defined as equalling ⁇ plus the angle ⁇ by which the image is rotated betv/een memory 10 and its display on screen 14 of CRT 13.
• the angle ⁇ may, for example, be calculated by a microprocessor 23, responsive to data received or interchanged with display control circuitry 24.
• the display control circuitry 24 might, for example, comprise the gyroscopic compass, synchros and synchro-to-digital converters in a horizontal situation indicator svstem for aircraft cock it use.
• MicroDrocesscr 23 may also use radial coordinate r output from scan converter 21 in its calculations where concentric images are to be rotated in differing degrees.
• FIGURE 2 is useful in understanding how to define the x and y coordinates of electron beam trace position to implement scan conversion.
• Point 30 is the arbitrarily chosen center of rotation for the image to be retrieved from memory 10. This center of rotation 30 is the center of a dashed-line circle 31 of arbitrary radius within the perimeter of which the image will always repose, whether rotated or not. It is convenient to choose this radius to be 2 n' pixels, where n is an integer.
• Circle 31 is inscribed in a square 32 with sides 32a, 32b, 32c, and 32d which defines that portion of the raster-scan to be transformed from x, y coordinates to the r, 9 coordinates used for addressing memory 10.
• the scan conversion calculations are considerably simplified by choosing the center of rotation 30 as the origin for the x, y coordinate system.
• the point at which it is best. to begin to carry forward the scan conversion process is the first point to be scanned in square 32—i.e. the upper left-hand corner 33, presuming the use of conventional CRT raster-scan with the relatively slow line-by-line scan from top to bottom in the trace direction and with the relatively fast pixel-by- pixel scan from left to right in the trace direction.
• This facilitates the changing of the rotation of the graphic image taken from memory 10 as it is presented on display screen 14 of CRT 13 without introducing disruption in the image as displayed.
• y origin poses a problem of how to establish the initial conditions for accumulation.
• this problem arises in as much as the origin is the only point that is scan- converted without being affected by the angle ⁇ through which the image is rotated.
• Another aspect of the problem is that the origin in both coordinate systems is remote from point 33, so at least one of its coordinates tends to have nearly maximum value.
• accumulation processes are carried forward from zero, however, so that the large numbers are gradually accumulated, this tending towards simplifying the arithmetic to a single addition or so.
• FIGURE * 3 shows a particular sub-raster scan generator 40 for generating x and y scan coordinates.
• the rest of the apparatus in the figure is a scan converter for converting these Cartesian coordinates to polar form for addressing memory 10 addressed in polar coordinates.
• memory 10 is addressed by column using the integral portions (int 9) of the angular coordinate (9) and by row using the integral portions (int r) of the radial coordinate (r) . It is convenient to have the scan generator generate x and y coordinates in two's complement form.
• the y coordinate of scan is generated using an n-bit counter 41 and a set-reset flip-flop 42; their combined outputs provide the y coordinate in two's complement form, its most significant bit being provided by the Q output of flip-flop 42 and its less significant bits by counter 41 output.
• the output of counter 41 is reset to "ZERO” and the Q output of flip-flop 42 is set to "ONE” by a SLOW-PRR INITIALIZATION pulse generated in timing control circuitry 10 at the time when the raster- scanning of the display screen brings the electron beam trace to position 33 (described in connection with FIGURE 2).
• the count in counter 41 is incremented by a LINE-SCAN-RATE CLOCK pulse furnished to it by timing control circuitry 19 following each time the electron beam trace crosses side 32d of square 32 in FIGURE 2, and occurring before the trace crosses side 32b on the ensuing line of display screen raster-scan.
• the n-bit counter 41 will have counted 2 n scan lines and have reached full count of 2 n -l .
• the next LINE-SCAN-RATE CLOCK pulse input will cause the counter 41 output to change from n parallel bits each .i_.ei.ng a ONE to n parallel bits each being a ZERO and to reset flip-flop 42.
• flip-flop 42 toggles -from a ONE to a ZERO at ' its Q output; and its Q output remains a "ZERO" for the remainder of the scanning of square 32.
• the x coordinate of scan is generated using a n-bit counter 43 and a set-reset flip-flop 44; their combined outputs provide the x coordinate in two's complement form, its most significant•bit being provided by the Q output of flip-flop 44 and its less significant bits, by counter 43 output.
• the output of counter 43 is reset to a ZERO and the Q output of flip-flop 44 is set to a ONE by a FAST-PRR INITIALIZATION pulse generated by timing control circuitry 19 at the time when the raster- scanning of the display screen brings the electron beam to any point on side 32b of square _32 (described in connection with FIGURE 2) .
• the count in counter 43 is incremented at video rate by a PIX ⁇ L-SCAN-RAT ⁇ CLOCK pulse furnished from timing control circuitry 19. Khen • the electron beam has reached a distance from side 32b one pixel shorter than that center of rotation 30 is from side 32b, the n bit counter 43 will have counted 2 n pixels and have reached full count of 2 n -l. The next PIX ⁇ L-SCAN- RATE CLOCK pulse input will cause the counter 43 output to change from n parallel bits each being a ONE to n parallel bits each being a ZERO and to set flip flop 44 with its overflow bit. The Q output from flip flop 44 toggles from a ONE to a ZERO and remains a ZERO for the remainder of the scan to side 32d of square 32.
• timing control circuitry 19 for generating the LINE-SCAN- RAT ⁇ CLOCK, SLOW-PRR INITIALIZATION, PIX ⁇ L-SCAN-RATE CLOCK and FAST-PRR INITIALIZATION pulses are familiar to the video system designer.
• the PIXEL-SCAN-RATE CLOCK and LINE-SCAN- ATE CLOCK pulses are normally generated by frequency-dividing counters v/hich count MASTER CLOCK pulses—although it is possible (particularly in systems with monochromatic display) that the master clock 20 supplies output pulses at pixel scan rate, which may be applied without frequency division to counter 43 as input for counting.
• the SLOW-PRR INITIALIZATION pulse may be generated using a counter to count e.lectron-beam-trace scan lines since field retrace and then using a digital comparator to compare the output of that counter to a programmed line count for obtaining indications of when the edge 32a of square 32 has-been reached by the electron beam trace; and the FAST PRR INITIALIZATION pulse may be generated using a counter to count pixels since line retrace and then using a digital comparator to compare the output of that counter to a programmed pixel count for obtaining indications of when the edge 32b of square 32 has been reached by the electron beam trace.
• the SLOW-PRR and FAST-PRR INITIALIZATION pulses may be provided by the vertical and horizontal synchronization pulses, respectively, with the PIX ⁇ L-SC ⁇ N- RATE and LINE-SCAN RATE CLOCK pulses being supplied as gated clocks, with clock pulses furnished only during trace and not during 5 retrace.
• the counters used in the scan generator may also be employed in the counting used in frequency division of the master clock pulse repetition rate to control the timing of horizontal and vertical synchronization pulses for sweep generators 17 and 18.
• gated clocks may be used where clock pulses are provided only so long as the electron beam trace is within square 32. Allowing square ⁇ 32 to be only partially on screen will require measures to
• the LINE-SCAN- RATE CLOCK to counter 41 can comprise 'pulse doublets, each doublet occurring once per line scan interval to cause counter 41 to increment by two each time it counts 0 rather than by one. Provision is then also made to apply an additional LINE-SCAN-RATE CLOCK pulse to counter 41 every other interval between field scans, to compensate for the one less line in alternate fields.
• Circuitry 50 converts the x and y coordinates to 5 the radial coordinate r of the polar coordinates used for addressing memory 10 supposing it to be of a type addressed in polar coordinates.
• the following formula is a conventional basic conversion formula used in circuitry 50.
• ROM 52 stores a square-root look-up table and responds to r" to provide the radial coordinate r.
• x 2 and y2 are based on the following specific expression of the binomial theorem, where z is the general expression for either variable, x or y.
• the two's complement output of ' register 51 is clocked out and added to the two's complemeni output of a multiplexer 53 responsive to each REGISTER CLOCK pulse provided from the output of an OR.
• ate 55 responsive to either a LINE-SCAN-RATE or PIXEL-SCAN-RATE CLOCK received at one of the inputs of gate 55; and the two's complement result is used to update the contents of register 51.
• Multiplexer 53 is arranged to select as its output, during times the register 51 is to be clocked with a REGISTER CLOCK pulse derived from a PIXEL-SCAN-RAT ⁇ CLOCK pulse, its input corresponding to a (2x+l) term.
• This term comprises n more significant bits each * corresponding to the Q output bit of flip-flop 44, n less significant bits corresponding to the n-bit output of counter 43, and a least significant bit which is invariably a ONE.
• Multiplexex 53 is arranged to select as its output, during times the register 51 is to be clocked with a REGISTER CLOCK pulse derived from a LINE-SCAN-RATE CLOCK pulse, its input corresponding to a (2y+l) term.
• This term comprises n more significant bits each corresponding to the Q output bit of flip flop 42, n less significant bits corresponding to the n-bit output of counter 41, and a least significant bit which is invariably a ONE.
• n more significant bits of these two's complement terms being all ZERO'S is indicative of their being positive.
• the n less significant bits correspond to the 2x portion of (2x+l) and to the 2y portion of (2y+l) ; and the least ' significant bits being ONE's add unity to 2x and 2y.
• the n more significant bits in these two' s complement terms being all ONE's is indicative of their being negative.
• the remaining bits correspond to the complement of (2x+l) and to the complement of (2y+l) —i.e. those terms subtracted from 2 n .
• the multiplexer 53 is controlled by pulses generated during horizontal retrace. Absent the pulses, counter 43 output is selected by multiplexer 53 as its output, otherwise counter 41 output is selected as its output. In other cases the multiplexer 53 can be controlled by the output of a flip-flop, set by alternate overflow bits from counter 43 to direct multiplexer 53 to select counter 41 output as its output, and reset by delayed LINE-SCAN-RATE CLOCK pulse to direct multiplexer 53 to select counter 43 output as its output.
• Circuitry 60 converts the x and y coordinates to an unrotated image angular coordinate ⁇ to which a programmable angle ⁇ of image rotation is added to generate the rotated-image angular coordinate 9 of the polar coordinates used for addressing memory 10, continuing to suppose it to be of a type addressed in polar coordinates.
• the most significant bit of ⁇ indicative of the half-plane the sample point of the unrotated image lies in is available directly from polarity-bit flip-flop 42 of scan generator 40.
• the second most significant bit of ⁇ which together with the most significant bit of ⁇ indicates the quadrant in which ⁇ lies, is generated at the output of an exclusive OR gate 68 to which the outputs of flip flops 42 and 44 of scan generator 40 are applied.
• y output o counter 41 is applied as first inputs to a first battery 61 of exclusive OR gates each receiving the Q output of flip flop 42 (MSB) as their second inputs.
• the outputs of the battery 61 of exclusive OR gates is the approximation to
• the output from second battery 62 of exclusive OR gates provides a good approximation " for larger values of jx
• a ROM 63 responds to the n-parallel-bit output of battery 61 of exclusive OR gates to supply its logarithm to the base two, and a ROM 64 responds to the n-parallel-bit output of battery 62 of exclusive OR gates to supply the logarithm to the base two of its reciprocal.
• These logarithms are summed in adder 65 to develop the logarithm of [y
• a battery 69 of exclusive-OR gates responds to the quadrant indication from exclusive-OR gate 68 applied to their first inputs and to ROM 66 output applied to their second inputs to provide the polar • coordinate ⁇ of the unrotated image, ⁇ is summed in adder 67 with the angle ⁇ through which the image is to be rotated. This addition generates 9, the polar coordinate the integral portion of which is to be used in addressing memory 10, supposing its storage locations to contain the display image information in polar-coordinate organization.
• a digital memory 80 corresponding to cascaded ROMS 63, 64 and 66 , is addressed by exclusive OR gates 81 through 87 to produce output signals which are decoded by exclusive OR gates 91 through 97.
• the exclusive OR gates 91 through 97 correspond to the battery of exclusive OR gates 69 of FIGURE 3.
• the seven lower order bits 2 through 2 and (LS3) the least significant bit of an ei ⁇ ht-bit input sicnal are applied to the ! respective inputs of the seven exclusive-OR gates 87 through 81.
• the MSB of the input signal is applied to second inputs of each of the seven exclusive-OR gates 87 through 81.
• the outputs of exclusive-OR gates 87 through 81 are coupled to the seven address inputs a fi -a n of a digital memory 80.
• the seven outputs b ( .-b r) of the memory 80 are coupled to respective inputs of exclusive-OR gates 97 through 91.
• the MSB of the input signal is applied to second inputs of exclusive-OR gates 97 through 91.
• the seven lower order output bits 2 6 through 21 and LSB of a processed output signal are produced at the outputs of exclusive-OR gates 97 through 91.
• FIGURE 4 The operation of the embodiment of FIGURE 4 is exemplified by the tables of FIGURES 5 and 6. These tables illustrate the principles of the processor of the present invention in terms of four-bit signals, which are equally applicable to the arrangements of FIGURES 3 and 4.
• the table with the heading "Binary Data In” shows the binary words and their decimal equivalen for the dynamic range of a four-bit input signal.
• the dynamic range extends from a minimum value of 0000, decimal 0, to a maximum value of 1111, or decimal 15.
• the range is seen to exclude sixteen levels.
• the dashe box shown in the center table of FIGURE 5, labelled "Memory Address”, contains the data stored in the memory for a linear, unity transfer characteristic.
• the memory contains eight addressable memory locations, indicated as L0 through L7. Three bits are stored at each address location.
• L0 through L7 the digital data stored -in each memory location is the same as the digital address for that location; for example, when memory location L5 is addressed by the digital address word 101, the digital word produced by the memory is 101.
• the processed output signal values are the same as the input signal values. For instance, assume that the input signal to the processor has a value of 0101, or decimal 5.
• the MSB, 0, is exclusive-ORed with the lesser significant bits 1, 0, and 1, to produce the address for the memory.
• the input signal to the processor has a value in the upper half of the dynamic range, including decimal values 8-15.
• the MSB of 1 is exclusive-ORed with the lesser order bits 101. This exclusive-ORing produces an address of 010 for the memory, which addresses memory location L2.
• the data word stored in location L2, 010 is produced at the output of the memory.
• the 010 bits are exclusive-ORed with the MSB of 1 to produce the three_lower order bits of the output signal, in this case 101.
• the MSB is passed directly to the output, forming the complete output word of 1101.
• FIGURE 5 illustrates that the arrangements of FIGURES 3 and 4 will process an input signal over its full dynamic range for a symmetrical transfer characteristic with a memory having a capacity of 2N-1 (N-l) .
• 2 N (N-l) is equal to 896, which is an improvement of required data storage as compared with the 2048 bits of memory required for eight-bit words without encoding and decoding.
• FIGURE 6 shows data tables similar to those of FIGURE 5, in that four-bit input signals are transformed into four-bit output signals with unity gain.
• the tables 5 of FIGURE 6 differ from those of FIGURE 5 because the input signals and the RAM data are in two's complement notation, as are x and y of FIGURE 3.
• the "Data In" table of FIGURE 6 comprises ascending positive and descending negative values from a median zero value.
• ROM's 63 and 64 of FIGURE 3 have * been constructed using two component ROM's of the conventional size with eleven-bit inputs and eight-bit outputs, responding to the nine bits of x and y respectively to provide sixteen- bit logarithms.
• ROM 66 has been constructed using four component ROM's of this size to respond to the twelve most significant bits of adder 65 output to provide 9 with sixteen bits resolution. So eight component ROM's of this size in addition to simple adder 65, suffice for calculation ⁇ with sixteen-bi-t resolution, rather than sixty four ROM's of this size being needed as would be the case with table look-up of 9 directly from x and y.
• FIGURE 7 shows how ROM 66 of FIGURE 3 can be replaced by a ROM 71 which stores 0_ ⁇ _ ⁇ ( ⁇ /4) rather than 0_ ⁇ _ ⁇ (. ⁇ r-/2) taking advantage of the following relationship for 0 p_ ( ⁇ . /2 ) .
• Digital comparator 72 compares the n-parallel-bit output from battery 61 of exclusive OR gates to the n- parallel-bit output from battery 62 of exclusive OR gates to develop an output that is a ZERO for the former smaller than the later and is otherwise a ONE.
• This output and the output of exclusive OR gate 68 are applied as inputs to a further exclusive OR gate 78.
• the output of gate 78 is used as the third most significant bit of ⁇ and so reduces by one the number of bits stored at each location in ROM 71 to preserve the accuracy provided by ROM 66.
• the output of comparator 72 also is applied as 5 control signal to multiplexors 73 and 74 and as first input to each of a battery 75 of exclusive OR gates .
• These exclusive OR gates receive as second inputs respective bits of the output from ROM 71, reproducing those bits as their outputs when their first inputs are Q ZERO and complementing those bits as their outputs when their first inputs are ONE.
• the output of comparator 72 being a ZERO directs multiplexors 73 and 74 to apply the outputs of batteries 61 and 62 of exclusive OR gates to ROM's 63' and 64', respectively; and battery 75 of 5 exclusive OR gates passes the ROM 71 output without complementing to furnish the less significant bits of ⁇ .
• comparator 72 being a ONE directs multiplexors 73 and 74 to apply the outputs of batteries 61 and 62 of exclusive OR gates to ROM's 64' and 63', respectively; 0 and battery 75 of exclusive OR gates complements the ROM 71 output in its output to furnish the less significant bits of ⁇ .
• ROM 64 or 64' is replaced by a ROM supplying the logarithm of y rather than the logarithm of its reciprocal, and wherein adder 65 is replaced by a subtractor circuit for linearly combining the output of ROM 63 or 63' with that of the ROM responsive to y.
• the two-dimensional linear interpolation can be done by successively polling each of the four adjacent 1 locations in memory for each pixel scanned in the display raster.
• the memory may be quadruplicated with the image shifted one coordinate step in one direction or the other or both in the three supplementary memories, with the four memories being read in parallel and their outputs 0 summed for each pixel scanned in the display raster.
• the first of these alternatives involves high video rates of operation.
• the second of these alternatives requires a four times increase in memory size. It was observed that this increase in memory size is just to store replicated 5 data with shifted addresses, which led to a search for a way to retrieve the four pieces of information for the two-dimensional linear interpolation in parallel from a memory not increased in size.
• FIGURE 8 shows the result of ' that search.
• 0 Memory 1-0 is subdivided into four portions 10a, 10b, 10c, and lOd. These portions are read out in parallel via a multiplexer 100 to simultaneously supply four bits of information in parallel to the two-dimensional linear interpolation circuitry 90.
• interpolator circuitry 90 As each pixel is raster-scanned the four adjacent locations in memory addressed at that time supply upper left, upper right, lower left, and lower right information for two-dimensional linear interpolation in interpolator circuitry 90. This interpolation can be

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• 1982
  • 1982-01-25 ES ES509037A patent/ES8303863A1/es not_active Expired
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