EP0063012A2 - Auslösevorrichtung - Google Patents

Auslösevorrichtung Download PDF

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Publication number
EP0063012A2
EP0063012A2 EP82301735A EP82301735A EP0063012A2 EP 0063012 A2 EP0063012 A2 EP 0063012A2 EP 82301735 A EP82301735 A EP 82301735A EP 82301735 A EP82301735 A EP 82301735A EP 0063012 A2 EP0063012 A2 EP 0063012A2
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EP
European Patent Office
Prior art keywords
output
input
trip
monitored
potential difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP82301735A
Other languages
English (en)
French (fr)
Other versions
EP0063012A3 (de
Inventor
Edward Houghton Carr
Harry Wilson Knight
Richard Chales Turnock
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imperial Chemical Industries Ltd
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Imperial Chemical Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imperial Chemical Industries Ltd filed Critical Imperial Chemical Industries Ltd
Publication of EP0063012A2 publication Critical patent/EP0063012A2/de
Publication of EP0063012A3 publication Critical patent/EP0063012A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B23/00—Alarms responsive to unspecified undesired or abnormal conditions

Definitions

  • This invention relates to a trip apparatus.
  • a parameter e.g. temperature, pressure, degree of travel
  • a device e.g. a valve, motor, or brake
  • the device we will hereinafter refer to the device as a solenoid although it will be appreciated that a wide range of other devices could be employed.
  • a trip system of high reliability is required to enable shut-down or modification of the operation in the event of said monitored parameter reaching e.g. as a result of failure or malfunction of equipment, a predetermined limit for safe operation.
  • the trip system of the present invention is of the type wherein an input field circuit is connected to the input terminals of a trip apparatus which forms the rest of the input circuit.
  • the trip apparatus in turn has output terminals, for connection to complete an output field circuit.
  • the input and output terminals of the trip apparatus provide the power source for supplying electrical current to the input and output field circuits.
  • the potential difference across the input terminals and/or between the input terminals and earth and/or across the output terminals and/or between the output terminals and earth are continuously monitored, so that if the monitored potential difference varies from preset limits, an alarm signal is generated.
  • the present invention provides a trip apparatus for operating a device when a monitored parameter reaches a predetermined trip value comprising
  • the trip system is preferably of the fail-safe type wherein, in the non-tripped condition, the input and output signals are not zero and change, e.g. decrease, when the system is tripped.
  • the means monitoring the parameter preferably includes a pair of contacts connected in series with the input field circuit with the contacts closed in the non-tripped condition. In this case monitoring the potential difference across the input means enables high contact resistance, i.e. a malfunction, to be detected.
  • the apparatus may also be arranged for use with an input field circuit producing an analogue signal, i.e. a signal that increases, or decreases, gradually as the monitored parameter approaches its trip value.
  • an analogue signal i.e. a signal that increases, or decreases, gradually as the monitored parameter approaches its trip value.
  • the trip apparatus may be arranged for use with more than one input circuit and/or more than one output circuit. In this case the health of the field circuit of at least one input and/or output may be monitored.
  • the means for monitoring the potential differences are preferably substantially isolated, e.g. by high impedances, from the main trip circuit so that alarm signals indicating malfunction of the input and/or output field circuits do not interfere with the operation of the main trip circuit, and cause unnecessary operation of the solenoid.
  • the potential difference across the terminals need not be monitored directly: thus the potential difference between one terminal and earth may be monitored and compared with the potential difference between the other terminal and earth. Likewise since the potential difference across a pair of terminals is dependent on the current flowing in the circuit including those terminals, the potential difference across the terminals may be monitored by manitoring the potential difference across another component in the circuit.
  • input signals may be obtained from several parameter monitoring means.
  • several parameters may each be monitored and the system tripped should any one or more of sala parameters reach its predetermined value. In other cases it may be desired to trip the system only if two or more parameters reach their predetermined levels.
  • a plurality of means monitoring the same parameter may be employed and the system arranged to trip when
  • each controlling the operation of one or more process modifying devices e.g. solenoids.
  • process modifying devices e.g. solenoids.
  • circuitry enabling such arrangements to be achieved, together with various safety devices, is described with reference to the accompanying circuit diagrams Figures 1 to 14.
  • the trip system is built up on a modular solid state system comprising a plurality of printed circuit cards, bearing the appropriate solid-state circuits, which can be inserted into slots in racks provided with points for connection to the appropriate input and output field circuits.
  • inter-trip cards There are three basic types of cards, primary cards, matrix cards, and secondary cards. However, as will be described hereinafter, further cards termed inter-trip cards may be employed in some cases.
  • the primary cards contain part of the trip circuit and the input field circuit monitoring circuit.
  • the secondary cards contain the remainder of the trip circuit and the output field circuit monitoring circuit.
  • the matrix cards act as a means for connecting in a desired combination the outputs from the primary cards to the inputs of the secondary cards.
  • the illustrated embodiment is designed to operate from a nominal 50 volts supply obtained from either a battery or from a 3 phase full-wave rectified AC supply; the supply negative is earthed.
  • the nominal value of 50 volts was chosen as it represents a good compromise between higher voltages which introduce personnel safety problems and lower voltages which introduce problems such as voltage drops in cables and the long term deterioration of initiating contacts.
  • the system has been designed to accommodate DC supply varying between 42 and 57 volts, thus avoiding the complications of constant voltage supply systems.
  • Operation on rectified AC may be used in systems where plant shutdown due to loss of mains supply would not be serious or where independent supplies of acceptable reliability are available. No smoothing is required so avoiding the need to use large electrolytic capacitors and their inherent unreliability.
  • transient loss of supply has been catered for; the system will withstand interruptions in supply of up to 250 milliseconds (ms).
  • the basic primary card trip circuit is shown in Figure 1 and employs an optical-electrical coupling comprising a light- emitting-diode (LED) Ll coupled to a photosensitive transistor Tl.
  • LED light- emitting-diode
  • the input circuit field circuit i.e. that within dotted box I contains a pair of contacts IC, termed initiating contacts, which open when the parameter being monitored reaches its predetermined value.
  • initiating contacts During normal, i.e. non-tripped, operation the initiating contacts IC are closed, diverting current from the LED Ll of the opto-coupler Ll, Tl. This causes transistors Tl and T2 to remain off, i.e. non-conducting; R5 holds down the base of transistor T3 which is thus also switched off. Since no current flows through T3, the potential difference (p.d) across R6 is zero so the output is at the line voltage of e.g. 50v.
  • R2 charges Cl until Ll conducts and opto-couples a signal to switch on Tl.
  • Rl and R3 allow the voltage at the contacts IC to reach about 40 volts to keep the contacts clean.
  • the switching on of Tl causes T2 to switch on driving current into the base of T3 thereby switching on T3.
  • the p.d across T6 increases and so the output voltage drops to approximately I volt. This is the trip condition.
  • Zener diode Zl is provided to protect Tl from excessive voltages.
  • a normally closed defeat switch DS is provided so that the output can be maintained when DS is opened even though the initiating contacts are open. This is of use when it is required to test or replace the means monitoring the parameter: it may also be required to be operated when the process covered by the whole trip system is being started up or changed from one mode of operation to another.
  • the defeat switch DS is in series with the output and operates by not allowing T3 to pass current when its contacts are open. This causes the output to remain high, i.e. the 'normal' condition, An LED L2 local to the defeat switch indicates when the primary card is defeated and extinguishes when the defeat switch is closed.
  • FIG 2 a modification of the circuit of Figure 1 is shown to provide for the use of more than one input field circuit to the card.
  • three inputs are used and arranged so that the system trips only when two or more of the inputs become open circuit, e.g. as a result of the initiating contacts of two of the inputs opening.
  • Tl, T2 and R4 thereof are shown in Figure 20
  • the emitters of the three transistors T2a, T2b, and T2c all drive into a common resistor R7.
  • T2a When one initiatiug contact opens, say that of circuit a, T2a will conduct and drive a current "i" mA througta R7 producing "x" volts across it.
  • T2a and T2b When two initiating contacts open, say those of circuits a and b, T2a and T2b will each conduct and each drive i mA through R7 producing 2x volts across it.
  • all three contacts open 3x volts is produced across R7.
  • the voltage across R7 is compared with say 1.5x volts, produced by potential divider R8, R9, by a voltage comparator VC 1.
  • the output of VC 1 is low when 0 or I contacts are open and high when 2 or 3 contacts are open.
  • comparator VC 1 is looking at the corners of a bridge so that the circuit will operate for any value of supply voltage.
  • the output of the comparator VC 1 is fed via a zener diode Z2 and current limiting resistor R10 to drive the base T3.
  • the zener diode Z2 is required to ensure that T2 is switched off when the comparator's output is 'low'.
  • FIG 3 another modification of the circuit of Figure 1 is shown to provide for a time delay where it is desired that a trip will only occur if the initiating contacts have remained open for a continuous pre-set time 't'. If the contacts close before 't' has elapsed the system will reset so that if the contacts then reopen, the previous portion of time 't' that the contacts were open is not counted towards the period 't' This is achieved by interposing a timer chip TC between T2 and T3. It will be appreciated that this time delay may also be used in the modification of Figure 2. In this case the timer TC is interposed between the comparator VC1 and T3. Input to the timer is via potential divider Rll, R12. This provides the correct input voltages for the timer from all options.
  • the duration of 't' can be preset e.g. by selection of a suitable value for the timing capacitor C2.
  • Careful design of the primary card layout permits the same printed circuit to be used for the various options. Dif- erent options are achieved by including extra components and using different values of resistors.
  • the matrix card is illustrated by Figure 4 and consists of a double sided printed circuit board having vertical input tracks on one side and horizontal output tracks on the other connected to input and output pins respectively.
  • Each input pin of the matrix card is wired to an individual input slot in the rack.
  • Each output of the. matrix card is connected to two pins; one pin is wired to an output slot in the module; the other pin may be wired to the appropriate channel on an inter-trip card as described hereinafter.
  • each primary card is connected to an input pin of the matrix card and the input to each secondary card is taken from an output pin of the matrix card. Holes are drilled in the board to allow connections, via diodes, to be made between input tracks and output tracks. Where it is desired that a particular input should, when tripped, provide a trip signal to any particular secondary card, a diode is connected between the respective input and output tracks of the matrix card where they intersect. Thus in the example shown in Figure 4, three inputs A - C and three outputs D - F are shown. It is desired that a signal from input A provides a signal to output E, that a sigmd from input B also provides a signal.
  • the circuit is shown in Figure 5.
  • the latching action is provided by means of a thyristor T5.
  • the trip signal received by the input of the secondary card via the matrix card from the output of a primary card is a reduction in the voltage, normally to a value of less than 2 volts, from the normal, i.e. non-tripped, line voltage.
  • the input to the secondary card includes an input filter R13, C3, R14, C4 which requires the input signal to persist for nominally 5 ms before the card latches 'offo The input filter immunity against spurious electrical signals.
  • T4 drives current into the Rl6, C5 filter at the gate of thyristor T5 which switches on.
  • This filter at the gate is to prevent firing of the thyristor by spurious electrical signals.
  • T5 conducting clamps the base of transistor T6 to 0 volts and T6 switches off. This removes the base drive to transistor T7 which also switches off. This removes the base drive from the output transistor T8 which, in turn, switches off and de-energises the output to the output field circuit containing solenoid SV. T7 switching off also 'starves' thyristor T5 of holding current thereby switching it off.
  • two 1 ohm resistances R17, R18 are connected in parallel to provide a resistance Rp of about 0.5 ohm in line with the output of transistor T8.
  • Rp resistance of the output field circuit
  • the p.d across Rp increases which causes the voltage at the base of T8 to drop.
  • C6 limits the rate of rise of current through T8 by diverting its base current as the voltage at the base of T8 falls. This continues until T8 current reaches 5 amps; Dl, Z4 and T4 then conduct enough to switch on T5 on the output is latched 'off in the usual way.
  • the time delay in this mode is about 250 - 300 micro seconds; this is long enough, to prevent spurious operation of the overcurrent trip, but will not drive T8 into the secondary breakdown area of its operating characteristic.
  • C7 provides base current to hold T6 switched on if the supply is interrupted.
  • C7 is sized to allow for an interruption of 250 ms; if the supply interruption lasts longer than this, C7 will become discharged and T7, T6 will switch “off", causing latching "off".
  • T6 would remain switched on and would reset T7 and T8 as described hereinafter.
  • T6 When the reset switch RS contacts (normally closed) are opened, C8 is charged via field effect transistor T9 and provides a signal to the base of T6 which starts to conduct. T6 conducting provides base drive to T7 which switching on provides base drive to T8 and feedback to T6. Thus T7, T6 form a positive feedback loop and rapidly latch themselves on. T8 then has a continuous base drive and the output is latched 'on'.
  • T5 conducts and prevents this reset action.
  • Inter-trip cards may be provided to enable a trip signal from an output of a matrix card to be used as a trip signal for the input of another primary card connected, for example, via another matrix card, to further secondary cards.
  • Primary card 1 drives secondary card 2 via the matrix card 3; the drive to secondary card 2 is also connected via the inter-trip card 4 to primary card 5.
  • Transistor T3 on primary card I switching on pulls the input to the inter-trip card 4 low via the appropriate matrix diode D2, and so the voltage at the intersection of R21 and R22 drops to about 2.5 volts, which is lower than the voltage at the junctuon of T10 and R3 of primary card 5.
  • Transistor T10 is thus switched off.
  • T10 thus acts as open contacts for primary card 5 and allows its opto-coupler LED L1 to conduct. This maintains the voltage at the junction of T10 and R3 of primary card 5 at about 7 volts and thus ensures that T10 is held switched off.
  • Diode D3 protects the base-emitter of T10 from excessive reverse voltage.
  • diode D4 is provided to isolate the cards when the drive to secondary card 2 is high, i.e. when there is no trip signal fed from primary card 1.
  • Inter-trip cards may also be employed to enable a trip signal from the output of a secondary card to be used as a trip signal, often via a time delay, for another primary card: in this way two solenoid valves can be de-energised, the second a set time interval after the first.
  • the output drive to the first solenoid valve SV is taken from secondary card 6, via the inter-trip card 7, to a primary card 8 which carries the timer option previously described with reference to Figure 3.
  • De-energising the solenoid valve SV, i.e. tripping of secondary card 6, removes the base drive to T10 and the circuit functions as described above.
  • the monitoring circuits on both primary and secondary cards involve the use of bridge circuits with a voltage comparator 'looking' at the corners of the bridge.
  • the use of a bridge is desirable to minimise the effect of fluctuations in the supply voltage.
  • the comparator is well buffered i.e. substantially isolated from the main trip circuits, by using large value input resistors: this is to prevent any fault in the monitoring circuits from affecting the correct operation of the trip circuit.
  • Each primary card is provided with a number of monitoring circuits, each.generally of the type shown in Figure 8, taking a monitoring voltage from a desired position in the circuit of Figure 1, via a high resistance R24, to a voltage comparator VC2 wherein it is compared, via a resistance R25, with reference voltage obtained from a potential divider R26m, R26n.
  • the output from the comparator VC2 is low, below the threshold voltage of zener diode Z5 and so transistor Tll has no base drive.
  • a change in input conditions causing the comparator VC2 to switch over causes transistor T11 to switch on. This allows current to flow through the LED L3 which lights and through isolating diode D5 from any extra outputs, e.g. alarm bells.
  • the field wiring has a resistance and opening or closing of the initiating contacts, or faults in the field circuit, in effect vary the field circuit resistance.
  • the initiating contacts have been replaced, for ease of explanation, by a resistance Rf denoting the field circuit resistance.
  • the potential differeace across the inputs, i.e. between points A and B is monitored by comparing the voltage at point A with reference voltages obtained from potential dividers (R26a, E26b + R26c) and (R26a + R26b, R26c) connected between the positive rail and point B.
  • R26a is made N times R2 (B1 - see Figure 1 - is much greater than R2) and R26b and R26b + R26c are selected to be N times the field circuit resistance limits that are indicative of normal, i.e. non-tripped, resistance and high, but not open- circuit, resistance respectively.
  • R2 and R26a are selected so that R26a is much greater than R26b + R26c.
  • a normal, non-tripped, field resistance would be less than 30 ohms which is a nominal value corresponding to approximately 50 m of 0.75 sq mm or 1000 m of 1.5 sq mm cable.
  • Rf increasing, e.g.
  • Any shunt resistance to ground, i.e. earth leakage, will cause a lower p.d. between the initiating contacts and earth, and consequently between point B and earth.
  • a monitoring circuit is thus provided to compare the voltage at point B with that at point E created by the potential divider R26d + R26e and R26f.
  • the comparator VC2d of this monitoring circuit is arranged to chauge state to a high output, causing L3d to light when an earth leakage equivalent to a shunt resistance of, for example 15 kohms appears between point B and earth. This gives adequate warning as a trip will not be prevented, if suitable values are chosen for R2 and R3, until a much lower shunt resistance, e.g. 250 ohms, has developed.
  • the input circuit is not completely immune to high common mode voltage (CMV) and warning of the onset of this is provided.
  • point B is held at a suitable voltage, e.g. about 8 volts, above ground potential by R3.
  • a "High Voltage” monitoring circuit therefore compares the voltage at point B with the voltage at point F created by the potential divider R26d and R26e + R26f.
  • the comparator VC2c of this circuit gives a "high” output, causing L3c to light, at a positive CMV of greater than about 4 volts with respect to point B.
  • the 'Earth Leakage' comparator can also detect a negative CMV of greater than about 0.5 volts with respect to point B.
  • the monitoring circuits for "trip input” and “high” and “low” current in the output field circuit are shown in Figures 10 and 11 and are analogous to those of the primary card but compare the monitored voltage with a reference voltage given by a potential divider (R27, R28 Figure 10) or (R27, R28 + R29 or R27 + R28, R29 Figure 11) by a voltage comparator VC3.
  • a potential divider R27, R28 Figure 10
  • a voltage comparator VC3 a voltage comparator VC3
  • a low output from the comparator VC3 causes a transistor T12 to conduct which thus supplies. base drive to a second transistor Tl3 to cause the latter to conduct, thus illuminating LED L4.
  • the output signal from the matrix card is monitored at point J ( Figure 5) by a monitoring circuit of the type shown in Figure 10.
  • the LED L4 remains lit for as long as there is such an input signal to the secondary card, e.g. for as long as the initiating contacts causing the trip signal on the associated primary card remain open.
  • the monitoring circuit of Figure 11 is used to detect "high” and "low” current through the output field circuit, i.e. through solenoid valve SV. This current passes through the resistance Rp.
  • the p.d. across Rp, i.e. at the point K ( Figure 5) is monitored by the circuit shown in Figure 11 using reference voltages, obtained via potential divider R27, R28, R29 which are preset to suit the normal load current of the solenoid valve SV.
  • Comparator VC3a lights its LED L4a when the current through Rp is low while LED L4b is let when the current through Rp is high. When the current through Rp is normal, i.e. between the "high” and “low” limits, neither L4a nor L4b is lit.
  • the "low current” LED L4a When “tripped”, the "low current” LED L4a would also light. If desired this can be disabled via a diode D7 connected to the collector of the transistor Tll of the circuit monitoring "trip output" at point L. Where disablement of LED L4a- is not required, zener diode Z6 can be omitted.
  • a closed reset switch RS holds the base of Tl4 (see Figure 5) near ground. Tl4 conducts and lights LED L5 when the reset switch or its associated wiring is open circuit.
  • the trip system is of the fail-safe type where a current flows through the input field and output field circuits in the non-tripped condition, and, on tripping, these currents decrease, generally to zero.
  • the secondary card circuitry can be modified, for example as shown in Figure 13, to provide for energising the output field circuit solenoid SV only in the event of a trip signal.
  • the output field circuit is connected in parallel with output transistor T8. and an additional resistance R31.
  • T8 conducts and diverts current through R31 so that the residual current through the solenoid SV is insufficient to energise it.
  • T8 switches off so removing the shunt and causing the solenoid SV to energise.
  • the circuit shown in Figure 14 could be used: here the secondary card circuit has to be modified (by means not shown) to provide that T8 is non-conducting in the non-tripped condition and switches on upon receipt of a trip signal.
  • T8 is switched on, R32 is shunted thus allowing the current in the output field circuit to increase to energise the solenoid SV.
  • the trip system may also be coupled to a computer in which a model of the whole trip system is carried: the computer may be arranged to check on the operation of the trip system by feeding a signal from the input monitoring circuits into the model and comparing the actual monitored output signals with those predicted by the computer from the model contained therein.

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  • Business, Economics & Management (AREA)
  • Emergency Management (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Testing And Monitoring For Control Systems (AREA)
  • Emergency Protection Circuit Devices (AREA)
EP82301735A 1981-04-09 1982-04-01 Auslösevorrichtung Withdrawn EP0063012A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8111142 1981-04-09
GB8111142 1981-04-09

Publications (2)

Publication Number Publication Date
EP0063012A2 true EP0063012A2 (de) 1982-10-20
EP0063012A3 EP0063012A3 (de) 1983-07-06

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EP82301735A Withdrawn EP0063012A3 (de) 1981-04-09 1982-04-01 Auslösevorrichtung

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EP (1) EP0063012A3 (de)
JP (1) JPS57178507A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116169652A (zh) * 2023-03-07 2023-05-26 国网江苏省电力有限公司镇江供电分公司 一种220kV主变开关跳闸监控判别方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1209402A (en) * 1968-03-12 1970-10-21 Honeywell Inc Improvements in or relating to electrical indicating and monitoring apparatus
DE2546997A1 (de) * 1975-10-21 1977-05-05 Bureaux De Const De Relais Ele Einrichtung zur isolationsueberwachung nicht geerdeter gleichstromnetze
DE2614748A1 (de) * 1976-04-06 1977-10-27 Baum Elektrophysik Gmbh Schaltung zur funktionsueberwachung eines mittelbar wirkenden schalters
DE2723019A1 (de) * 1977-05-21 1978-11-30 Hartmann & Braun Ag Schaltungsanordnung zur ueberwachung des isolationszustandes von gleichspannungsnetzen
US4159501A (en) * 1975-03-27 1979-06-26 Kerr-Mcgee Nuclear Corporation Method and apparatus for indicating the leakage resistance in an electrical system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1209402A (en) * 1968-03-12 1970-10-21 Honeywell Inc Improvements in or relating to electrical indicating and monitoring apparatus
US4159501A (en) * 1975-03-27 1979-06-26 Kerr-Mcgee Nuclear Corporation Method and apparatus for indicating the leakage resistance in an electrical system
DE2546997A1 (de) * 1975-10-21 1977-05-05 Bureaux De Const De Relais Ele Einrichtung zur isolationsueberwachung nicht geerdeter gleichstromnetze
DE2614748A1 (de) * 1976-04-06 1977-10-27 Baum Elektrophysik Gmbh Schaltung zur funktionsueberwachung eines mittelbar wirkenden schalters
DE2723019A1 (de) * 1977-05-21 1978-11-30 Hartmann & Braun Ag Schaltungsanordnung zur ueberwachung des isolationszustandes von gleichspannungsnetzen

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116169652A (zh) * 2023-03-07 2023-05-26 国网江苏省电力有限公司镇江供电分公司 一种220kV主变开关跳闸监控判别方法
CN116169652B (zh) * 2023-03-07 2024-05-28 国网江苏省电力有限公司镇江供电分公司 一种220kV主变开关跳闸监控判别方法

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Publication number Publication date
EP0063012A3 (de) 1983-07-06
JPS57178507A (en) 1982-11-02

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Effective date: 19840614

RIN1 Information on inventor provided before grant (corrected)

Inventor name: CARR, EDWARD HOUGHTON

Inventor name: TURNOCK, RICHARD CHALES

Inventor name: KNIGHT, HARRY WILSON