EP0055322B1 - Miniature electrical connectors and methods of fabricating them - Google Patents

Miniature electrical connectors and methods of fabricating them Download PDF

Info

Publication number
EP0055322B1
EP0055322B1 EP19810105734 EP81105734A EP0055322B1 EP 0055322 B1 EP0055322 B1 EP 0055322B1 EP 19810105734 EP19810105734 EP 19810105734 EP 81105734 A EP81105734 A EP 81105734A EP 0055322 B1 EP0055322 B1 EP 0055322B1
Authority
EP
European Patent Office
Prior art keywords
wafer
miniature electrical
silicon
electrical connector
fabricating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19810105734
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0055322A2 (en
EP0055322A3 (en
Inventor
Michael Jon Palmer
Kwang Kuo Shih
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0055322A2 publication Critical patent/EP0055322A2/en
Publication of EP0055322A3 publication Critical patent/EP0055322A3/en
Application granted granted Critical
Publication of EP0055322B1 publication Critical patent/EP0055322B1/en
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R3/00—Electrically-conductive connections not otherwise provided for
    • H01R3/08—Electrically-conductive connections not otherwise provided for for making connection to a liquid
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/36—Mechanical coupling means
    • G02B6/3628—Mechanical coupling means for mounting fibres to supporting carriers
    • G02B6/3632—Mechanical coupling means for mounting fibres to supporting carriers characterised by the cross-sectional shape of the mechanical coupling means
    • G02B6/3644—Mechanical coupling means for mounting fibres to supporting carriers characterised by the cross-sectional shape of the mechanical coupling means the coupling means being through-holes or wall apertures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/36—Mechanical coupling means
    • G02B6/3628—Mechanical coupling means for mounting fibres to supporting carriers
    • G02B6/3684—Mechanical coupling means for mounting fibres to supporting carriers characterised by the manufacturing process of surface profiling of the supporting carrier
    • G02B6/3692—Mechanical coupling means for mounting fibres to supporting carriers characterised by the manufacturing process of surface profiling of the supporting carrier with surface micromachining involving etching, e.g. wet or dry etching steps
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/36—Mechanical coupling means
    • G02B6/38—Mechanical coupling means having fibre to fibre mating means
    • G02B6/3807—Dismountable connectors, i.e. comprising plugs
    • G02B6/3873—Connectors using guide surfaces for aligning ferrule ends, e.g. tubes, sleeves, V-grooves, rods, pins, balls
    • G02B6/3885—Multicore or multichannel optical connectors, i.e. one single ferrule containing more than one fibre, e.g. ribbon type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
    • H01R4/58—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation characterised by the form or material of the contacting members
    • H01R4/68—Connections to or between superconductive connectors

Definitions

  • This invention relates to miniature electrical connectors and their fabrication.
  • a multisocket electrical connector is described in the IBM Technical Disclosure Bulletin, Vol. 19, No. 1, June 1976, pages 372 to 374.
  • the connector consists of two silicon wafers bonded together having cavities filled with a metal which is liquid at or above a desired temperature.
  • the connector supports a high density of electrical conducting pins which are individually insulated.
  • Fabrication of the connector comprises the anisotropic etching of tetrahedral openings in two silicon wafers.
  • the two mirror-imaged wafers are laminated so that the base of the tetrahedrals are aligned to form an octahedral cavity.
  • the disclosed connectors are useful, they suffer some drawbacks. More particularly, because of the need to bond to substrates increased inductance occurs across the cavity, thus lowering the speed of operations. Similarly, because of the need to match to substrates packing densities are reduced.
  • octahedral cavities can be anisotropically etched in a single silicon substrate. Such cavities can be thinner and therefore have less inductance which can result in higher speeds of operation. Greater densities are also obtainable.
  • An object of the invention is to provide a structure having a closely spaced array of octahedral cavities in a single wafer of silicon.
  • Another object of the invention is to provide a method of fabricating miniature electrical connectors.
  • a miniature electrical connector comprises, according to one aspect of the invention, a single wafer of silicon having a plurality of octahedral cavities formed therethrough.
  • a method of fabricating a miniature electrical connector comprising a plate-like structure of silicon having a plurality of octahedral cavities therein, is characterised by the successive steps of growing Si0 2 films (2, 2') on opposite sides of a single monocrystalline wafer of silicon having the (100) planes parallel to its surface, forming aligned holes in the Si0 2 films, and simultaneously etching both sides of the wafer in an anisotropic etching solution.
  • Octahedral cavity arrays offer the capability of fabricating high density demountable connectors with zero insertion force. They are also suitable for partitioning the interconnections of circuit boards. Their fabrication is completely compatible with silicon large scale integration technology.
  • FIG. 1 An octahedral cavity formed by a method according to the present invention is illustrated in Figure 1.
  • the cavity is formed in a single silicon wafer by etching both sides of the wafer in an anisotropic etchant.
  • Etchants found suitable for use in the present invention includes solutions of pyrocatechol, ethylene diamine and water, KOH solutions, NaOH solutions and hydrazine water solutions.
  • the thickness of the wafer needed to get these cavities is dependent upon the initial hole size through which etching is to proceed.
  • the thickness needed in the process is equal to or less than 2w/1.42 where w is the width of the entrance and exit holes.
  • wafer thickness should be less than about 7 mils (0.18 mm). If the wafer thickness is greater than about 7 mils (0.18 mm) etching will end prior to meeting at a central point within the wafer. Consequently pyramidal cavities will develop. Whereas, if the wafer thickness is equal to or less than about 7 mils (0.18 mm), etching will proceed through the wafer. After which etching will then proceed at the intersection of the (111) planes of the cavity until the desired octahedral cavity is formed.
  • Figure 2 illustrates an array of octahedral cavities formed in a single Si wafer 1 by a method according to the present invention.
  • Figure 3 illustrates a similar array of octahedral cavities 10 prepared by a known method.
  • two wafers 12 and 14 are etched in an anisotropic etchant to form pyramidal openings 16 and 18 in the individual wafers.
  • the etched wafers 12 and 14 are then mirror image matched and bonded together with a bonding agent 20.
  • the array of the present invention is thinner, i.e., about half as thick as the prior art, thus when used as electrical conductors exhibit less inductance. Consequently, connectors according to the present invention will exhibit higher speed operations than the prior art connectors.
  • Another advantage of the present invention is that higher packing densities are obtainable than with the prior art connectors.
  • the method comprises providing a mono- crystalline silicon wafer 1 ( Figure 4.1) having a (100) crystallographic orientation, i.e. the (100) planes are parallel to the surface of the crystal. As indicated above the thickness of the wafer is dependent upon the initial opening sizes. Si0 2 films (2, 2') about 5 x 10- 7 m (5000 A) thick are then formed on both sides of the wafer 1. The Si0 2 films (2, 2') are coated with a resist material (not shown), the resist is patterned and developed through mirror-imaged masks to provide aligned openings 3, 3' ( Figure 4.3) in both the Si0 2 films (2, 2'). State of the art etching and developing agents are used.
  • the wafer 1 is then immersed in an anisotropic etchant, so that both surfaces of the wafer 1 are etched simultaneously. As indicated above the openings 3, 3' are preferentially etched in the (100) plane.
  • the etchant can be effected using a water amine pyrocatechol etchant or other basic etchants. Etching further proceeds along the (111) plane until octahedral cavities ( Figure 4.4) are obtained.
  • the precision etching of monocrystalline materials is an established technique and is discussed extensively in the art, for example, in U.S. Patent No. 3,765,959.
  • the remaining Si0 2 films 2, 2' are then removed to provide the octahedral cavity array structure.
  • the oxide can be removed by known methods, for example with buffered HF at room temperature, followed by rinsing in distilled water.
  • the structure represented in Figure 4.5 can be used as a multi-socket electrical connector for use at cryogenic temperatures.
  • the cavities are filled with a suitable metal which is liquid at the temperature of operation, and a suitable male electrical connector inserted therein.
  • the connector can be cycled repeatedly between liquid helium and room temperatures without suffering structural failures.
  • arrays made in accordance with this invention have been cycled between 4.2°K and room temperature at least 50 times.
  • octahedral cavity array uses include optical fibre wire connections and evaporation masks.

Landscapes

  • Manufacturing Of Electrical Connectors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • ing And Chemical Polishing (AREA)
  • Connecting Device With Holders (AREA)
  • Weting (AREA)
EP19810105734 1980-12-31 1981-07-21 Miniature electrical connectors and methods of fabricating them Expired EP0055322B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22187080A 1980-12-31 1980-12-31
US221870 1980-12-31

Publications (3)

Publication Number Publication Date
EP0055322A2 EP0055322A2 (en) 1982-07-07
EP0055322A3 EP0055322A3 (en) 1983-05-11
EP0055322B1 true EP0055322B1 (en) 1985-05-22

Family

ID=22829753

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19810105734 Expired EP0055322B1 (en) 1980-12-31 1981-07-21 Miniature electrical connectors and methods of fabricating them

Country Status (3)

Country Link
EP (1) EP0055322B1 (enrdf_load_stackoverflow)
JP (1) JPS57114224A (enrdf_load_stackoverflow)
DE (1) DE3170598D1 (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214533A (ja) * 1984-04-09 1985-10-26 Mitsubishi Electric Corp 半導体基板へのバイアホ−ルの形成方法
CN100407366C (zh) * 2005-10-13 2008-07-30 探微科技股份有限公司 制作腔体的方法与缩减微机电元件的尺寸的方法
JP5767076B2 (ja) * 2011-10-17 2015-08-19 地方独立行政法人東京都立産業技術研究センター 熱型加速度センサー

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2168936B1 (enrdf_load_stackoverflow) * 1972-01-27 1977-04-01 Labo Electronique Physique

Also Published As

Publication number Publication date
JPS641048B2 (enrdf_load_stackoverflow) 1989-01-10
JPS57114224A (en) 1982-07-16
EP0055322A2 (en) 1982-07-07
DE3170598D1 (en) 1985-06-27
EP0055322A3 (en) 1983-05-11

Similar Documents

Publication Publication Date Title
US3765969A (en) Precision etching of semiconductors
US5436471A (en) Josephson junction apparatus formed on flexible polymeric film
US6417075B1 (en) Method for producing thin substrate layers
EP0430593B1 (en) Method of cutting a silicon wafer by orientation dependent etching
JP3699978B2 (ja) 集積回路の内部接続構造とその製造方法
EP0331333B1 (en) Method of making an article comprising a tandem groove, and article produced by the method
US3962052A (en) Process for forming apertures in silicon bodies
US4597003A (en) Chemical etching of a semiconductive wafer by undercutting an etch stopped layer
CA1286796C (en) Double wafer moated signal processor
EP0274801B1 (en) Method of manufacturing a semiconductor device of the "semiconductor on insulator" type
US5804314A (en) Silicon microstructures and process for their fabrication
US5528719A (en) Optical fiber guide structure and method of fabricating same
US4891255A (en) (110) Oriented silicon wafer latch accelerometer and process for forming the same
EP0331334A2 (en) Optical connector
EP0917733B1 (en) Integrated circuit device manufacture
US20070093026A1 (en) Method of Making Thin Silicon Sheets for Solar Cells
US4376872A (en) High voltage V-groove solar cell
US3844858A (en) Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
WO1996013062A1 (en) Apparatus and method of manufacturing stacked wafer array
EP0055322B1 (en) Miniature electrical connectors and methods of fabricating them
US5067233A (en) Method of forming an integrated circuit module
US20060186541A1 (en) Method and system for bonding a semiconductor chip onto a carrier using micro-pins
US20020048955A1 (en) Method for fabricating a thin, free-standing semiconductor device layer and for making a three-dimensionally integrated circuit
US6387851B1 (en) Micro-fabrication method and equipment thereby
JPS62229855A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19821220

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Designated state(s): DE FR GB

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 3170598

Country of ref document: DE

Date of ref document: 19850627

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19910621

Year of fee payment: 11

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19910723

Year of fee payment: 11

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19920721

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19921027

Year of fee payment: 12

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19920721

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19930331

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19930401

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST