Classifications

• • G—PHYSICS
  • G04—HOROLOGY
  • G04G—ELECTRONIC TIME-PIECES
  • G04G21/00—Input or output devices integrated in time-pieces
  • G04G21/02—Detectors of external physical values, e.g. temperature
  • G04G21/025—Detectors of external physical values, e.g. temperature for measuring physiological data
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B5/00—Measuring for diagnostic purposes; Identification of persons
  • A61B5/02—Detecting, measuring or recording for evaluating the cardiovascular system, e.g. pulse, heart rate, blood pressure or blood flow
  • A61B5/024—Measuring pulse rate or heart rate
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B5/00—Measuring for diagnostic purposes; Identification of persons
  • A61B5/02—Detecting, measuring or recording for evaluating the cardiovascular system, e.g. pulse, heart rate, blood pressure or blood flow
  • A61B5/024—Measuring pulse rate or heart rate
  • A61B5/02438—Measuring pulse rate or heart rate with portable devices, e.g. worn by the patient
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B5/00—Measuring for diagnostic purposes; Identification of persons
  • A61B5/68—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient
  • A61B5/6801—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient specially adapted to be attached to or worn on the body surface
  • A61B5/6802—Sensor mounted on worn items
  • A61B5/681—Wristwatch-type devices
• • A—HUMAN NECESSITIES
  • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
  • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
  • A61B2560/00—Constructional details of operational features of apparatus; Accessories for medical measuring apparatus
  • A61B2560/04—Constructional details of apparatus
  • A61B2560/0462—Apparatus with built-in sensors
  • A61B2560/0468—Built-in electrodes

Definitions

• the present invention relates to pulse monitors with visual readout, in general, and to a cardiotachometer which performs a comparison between selected heartbeat intervals such that when any plurality of the intervals are within a predetermined percentage of each other, the plurality of intervals are averaged, read out and held in the display until the next update.
• Heart rate is the basic parameter used to evaluate and determine the condition of the human body.
• the heart produces three wave complexes, designated as P, RS, and T, each of which corresponds to a particular electrical event within the heart. It has long been known that the R wave produces the greatest electrical activity, and for this reason the R-R interval has been used as a way of measuring the time between heartbeats. By knowing the time between heartbeats, it is easy to determine the number of beats per minute.
• the contraction, or period of contraction, of the heart is referred to as a systole. It coincides with the interval between first and second heart sounds, during which blood is forced into the aorta and the pulmonary trunk. In the same way the R-R interval may be used as a way of measuring the time between heartbeats, the interval between systoles may be used for the same purpose.
• the heart contracts and forces blood through the arteries, which respond by expanding.
• a systole may be detected by placing an appropriate transducer or sensor against any of the well known pressure points on the human body or in an area where blood flow is occurring.
• the transducer may be in the form of a pressure transducer, such as a piezoelectric crystal or a photo-transducer in the form of a light emitting diode and a photocell.
• a miniature, totally self-contained cardiotachometer to be worn or held by a user for numerically displaying a continuous readout of the user's heart beat rate.
• the device which may be housed in a wrist watch or a compact hand-held unit, basically comprises a sensor in the form of a light emitting diode and a photocell which is placed on the finger of the user.
• the photocell responds to the variations in light intensity reflected off the capillary bed within the finger to produce an analog voltage signal representative of the systolic beats. This signal is received by a slope detector where it is amplified and converted into a digital signal.
• the digital signal is delayed for a predeter- mined time and then fed into a pulse shaper to produce a pair of clean pulse trains.
• One pulse train is used to reset an up-counter and a 60/t computation block, while the other pulse train is used to latch data within the 60/t computation block.
• the 60/t computation circuitry produces an output signal which has a frequency representative of the heart rate in beats per minute. This signal is used to cause an up-counter to produce a binary number equal to the number of beats per minute. This number is fed to a latch and held.
• the binary number from the up-counter, with the two least significant bits excluded, is simultaneously fed to a comparator and a series of holding registers.
• the holding registers typically comprise a plurality of 10-bit shift registers, one being associated with each binary bit from the up-counter.
• the binary numbers from the up-counter are placed into the holding registers on a first-in first-out (FIFO) basis.
• FIFO first-in first-out
• the eleventh number placed into the holding registers will replace the first number previously stored therein.
• a compare signal is issued and fed to a detect up-counter. This comparison continues with the remaining numbers stored in the holding registers.
• the detect up-counter is advanced to produce a latch signal.
• the latch responds to this signal by causing the data stored therein to be transferred to a display where the data is converted into an array of integers in eye readable format.
• Figure 1 is a functional block diagram for a preferred embodiment of the subject invention
• Figure 2 is block circuit diagram showing examples of the sensor, the modulator and the slope detector
• Figure 3 is a block circuit diagram showing examples of the time delay and the pulse shaper
• Figure 4 is a block circuit diagram showing examples of the 60/t computation circuit and the up-counter;
• Figure 5 is a block circuit diagram showing the holding registers and the compare;
• Figure 6 is a perspective view of the hand-held embodiment of the subject cardiotachometer.
• Figure 7 is a perspective view of the subject cardiotachometer in the form of a wrist watch.
• Figure 8 is a schematic rear view of the cardiotachometer of Figure 7.
• the cardio- tachometer of the subject invention is generally noted as 10.
• the cardiotachometer 10 is a totally self-contained unit in the form of a wrist watch or a hand-held device.
• a sensor 12 which may be a conventional pressure transducer or a light emitting diode/ photocell combination, measures the systolic beats of the user.
• the beats are sensed at the wrist of the user in a conventional manner.
• the beats are sensed through a finger of the user in a conventional manner.
• the electrical signal produced by the sensor is fed into a modulator 16 via leads 14.
• the modulator 16 converts the incoming signal into a digital signal for interpretation by the slope detector 20.
• the output of the slope detector 20 appears on line 22 and is fed to a time delay 24.
• the output of the time delay appearing on leads 26 is fed to a pulse shaper 28 which produces two pulse trains on lines 30 and 32.
• the signals appearing on lines 30 and 32 are fed into 60/t computation circuitry 34.
• the signals on lines 30 and 32 cause the 60/t circuit 34 to produce at its output 36, a digital signal having
• a frequency equal to the number of heart beats per minute.
• An up-counter 38 responds to the signal on line 36 by producing an output signal 40 which is a digital representation in binary form of the number of beats per minute.
• the signal appearing on line 32 is used to reset the up-counter 38 between detected beats.
• the output of the up-counter is typically a 12-bit number, Dll-DO, which is fed to a multiplexer 46.
• the multiplexer 46 also receives the output of a time of day clock 66 on lines 68, and an elapsed time indicator 70 on lines 72.
• the holding registers 48 typically comprise a series of 10-bit shift registers, although shift registers having a capacity for a greater or lesser number of bits can be used.
• the holding registers are clocked at a rate such that the entire contents of the registers are presented to the compare 54 before the output of the up-counter is changed.
• the output of the holding registers 48 is also reinserted into the registers on a first-in first-out basis, along with the output of the up-counter so that the oldest piece of data is replaced by the output of the up-counter.
• the compare 54 contrasts the data from the up-counter 40, appearing on lines 44, with the data samples contained in the holding registers 48, appearing on lines 50.
• the compare 54 issues a compare signal on line 56.
• the detect up-counter which is typically a conventional up-counter, is caused to advance or count one unit by the compare signal 56.
• a latch pulse is issued on line 60.
• a function select switch 61 which is typically a multiposition switch or a series of push button switches located external to the device, provides a means for selecting between three functions for display, namely, time of day, elapsed time, or heart rate.
• heart rate When heart rate is selected the multi ⁇ plexer 46 feeds the output of the up-counter 38 to the latch 62.
• the signal appearing on line 60 from the detect up-counter 58 causes the latch 62 to issue appropriate signals on lines 74 to cause a conventional display 76 to display in eye readable form the heart rate of the user in beats per minute.
• the function select switch 61 also activates the latch 62 to produce the appropriate display in eye readable format on display 76.
• the sensor 12 comprises a light emitting diode (LED) 100 in series with a resistor 102 between a source of potential Vcc and ground.
• LED light emitting diode
• a photocell in the form of a phototransistor 104 in series with a resistor 106 between a source of potential Vcc and ground.
• the photocell senses the light from the LED bouncing off the capillary bed within the skin of the wearer as a beam of varying intensity caused by the systolic beats.
• the photocell responds by producing a varying voltage which is fed into the positive term of a comparator 110.
• the output of the comparator 110 is fed to the D input of flip-flop 122 via inverters 112 through 114.
• the flip-flop 122 produces a pulse train at its output which is fed back through resistor 118 to the negative input of the comparator 110.
• a capacitor 120 is connected between the negative input and ground. As the capacitor charges, it will trail the upgoing pulse from the phototransis ⁇ tor. When it catches the pulse, the output of the comparator 110 will be low, otherwise the output will be high. Therefore, the output of the flip-flop 122 will produce a series of logic ones when the slope of the output of the phototransistor is positive and will produce a series of logic zeros at all other times.
• the output of the flip-flop 122 is fed into a 16 bit shift register 126, although shift registers having a greater bit capacity can be used.
• the outputs of the shift registers are fed into a NAND gate 128 and then inverted by an inverter 134 to produce a signal on line 22. Should any of the outputs of the shift register become a logic zero then the output of the inverter 134 will be a logic zero, thus indicating that a pulse has not been detected. When the shift register is filled with logic ones, the output of the inverter 134 will also be a logic one, thus indicating that a pulse has been detected.
• the capacity of the shift register 126 as well as the clocking rate for the flip-flop 122 and the shift register 126 is chosen so that base line noise, including 60 and 120 Hz noise, at the sensor is not detected as a pulse. In other words, for a pulse to be detected it must have a fairly high slope, such as that caused by a systolic beat.
• the output of the slope detector 20 appearing on line 22 is fed into a NAND gate 140.
• the other input to the NAND gate is received from the output of a flip-flop 142.
• the output of the NAND gate 140 provides a clock signal to the flip-flop 142 on line 148.
• the Q output of flip-flop 142 is fed to the D input of an up-counter 144 which has its reset grounded.
• the up-counter issues a signal every 16th pulse to reset the flip-flop 142. In this way, a time-delayed , signal is issued on line 26 and fed into the pulse shaper 28.
• This time delay serves the purpose of providing a "dead time" interval where no spurious pulses, whether electronic or mechanical in origin, can -be counted.
• the pulse shaper 28 which is used to provide a pair of synchronized pulses on lines 30 and 32, comprises three flip-flops 150-152.
• Flip- flop 150 has its D input held high and is clocked by the signal on line 26.
• the output of flip-flop 150 is fed to the D input of flip-flop 151.
• the output of flip-flop 151 is fed to the D input of flip-flop 152 and also provides a signal on line 30.
• the output of the flip-flop 152 provides a signal on line 32 as well as a reset signal for flip-flop 150.
• a conventional 12-bit up-counter 160 is enabled and reset by the signal on line 32.
• the output of the up-counter is a 12-bit number chosen to represent the time interval between reset times. This number is fed via lines 162 into a latch 164 which is clocked at a rate determined by the signal on line 30.
• the latch has its reset high so as to dump it contents into the divide-by-N ( ⁇ N) 168.
• the divide-by-N is reset by the signal appearing on line 32 and is appropriately clocked by a signal on line 167 to produce at its output, a digital signal having a frequency equal to the number of heart beats per minute.
• the 60/t circuitry takes the time interval between systolic beats, and converts this time interval into a digital signal indicative of the number of heart beats per minute.
• This signal which appears on line 36, is used to clock an up- counter 38 which is reset between detected beat intervals by the signal on line 32.
• the output of the up-counter is a 12-bit binary number, Dll through DO, which appears on lines 40.
• the output of the up-counter is fed via lines 40 to the multiplexer 46. At the same time bits D7 through D2 from the up-counter are fed into the holding registers 48 and the compare 54.
• Bits D7-D2 from the output of the up-counter 38 are simultaneously fed into the inputs A through F of a multiplexer 180 and a series of exclusive OR gates 190 through 195 via lines 44-1 through 44-6.
• the outputs, A through F, of the multiplexer 180 are fed into a series of 10-bit shift registers 170 through 175.
• the outputs of the shift registers are fed to inputs of the exclusive OR gates 190 through 195 via lines 51-56, and to the inputs A-, through F, of the multiplexer 180 via lines 52-1 through 52-6.
• the shift registers 170 through 175 shift the incoming data received from the multiplexer 180 on a first-in first-out (FIFO) basis.
• the data is shifted through the shift registers at such a rate so that each of the data samples is presented for comparison by the compare 54 with the selected bits D7 through D2 from the up-counter 38.
• the outputs of the exclusive OR gates 190 through 192 are fed to a NOR gate 196 the output of which is fed to the input of a NAND gate 204.
• the outputs of exclusive OR gates 193 through 195 are fed to the inputs of NAND gate 204 via inverters 198 through 200, respectively.
• the exclusive OR gates 190 through 195 each issue a logic 1 when the inputs to those gates are different and issue a logic 0 when the inputs are the same.
• the outputs of all of the exclusive OR gates 190 through 195 are low, the output of the NAND gate 204 is high, indicating that a valid comparison has been made. If any of the outputs from the exclusive OR gates is high then the output of the NAND gate 204 will be low, indicating that a valid comparison has not been made.
• the output from the up-counter 38 is a binary number indicating that the heart rate is 72 beats per minute.
• the output, Dll-DO, of the up-counter 38 in binary notation is 0000, 0100, 1000.
• bits D7-D2 are fed into the exclusive OR gates.
• binary bits 010010 will be fed, respec- tively, to the inputs 41-1 through 44-6 of the exclusive OR gates. Since the two least significant bits of the output from the up-counter 38 have been excluded from the comparison, the output of the up-counter 38 will compare favorably to samples stored in the shift registers which are in the range between 72 and 75 beats per minute.
• the compare signal on line 56 indicates that a valid comparison has been made.
• This signal provides a pulse to advance the up-counter 58.
• the up-counter advances at least two, but typically three, units, it issues a latch signal on line 60 to latch the data previously stored in the latch 62, to appear on display 76.
• the multiplexer 46 is of conventional design, and may include a series of multiplexers designated as model number 4053 and manufactured by National Semiconductor, Inc., Santa Clara, California.
• the latch is of conventional design and may include a number of BCD-to-seven segment conversion devices. One such device is model number 4543, again, manufactured by National Semiconductor, Inc.
• the display 76 is typically of the type which converts the output of the latch 62 to an eye-readable array of integers.
• One such device is model number 741 manufactured by Beckman Instruments, Inc., Fullerton, California.
• a hand-held version of the unified, self-contained cardiotacho- meter with digital readout is generally designated as 200.
• the device comprises a unitized housing 202 shaped for convienent placement within the palm of the user.
• the light emitting diode 100 and the phototransistor 104 are positioned on the housing so as to receive the thumb of the user. In this way systoles are detected.
• the cardiotachometer circuitry, described hereinbefore, is mounted within the housing 200.
• the output of the phototransistor 104 is fed to the cardiotachometer circuitry, wherein it is processed and read out on the display 76 which is positioned on the housing for easy reading by the user.
• the cardiotachometer of the subject invention being mounted in a wrist watch is shown in Figures 7 and 8.
• the cardiotachometer circuitry is mounted in a watch housing 210 which is secured to the wrist of the user by straps 212.
• the sensor which is a piezoelectric transducer 214, is secured to the back of the housing 210 and detects systoles through the wrist of the user.
• a push button switch 216 is provided to select the function (heart rate, time of day, or elapsed time) to be displayed on the display 76.
• CMOS comp 1 imentary-metal-oxide-silicon

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• Health & Medical Sciences (AREA)
• Life Sciences & Earth Sciences (AREA)
• Cardiology (AREA)
• General Health & Medical Sciences (AREA)
• Physics & Mathematics (AREA)
• Biophysics (AREA)
• Biomedical Technology (AREA)
• Engineering & Computer Science (AREA)
• Pathology (AREA)
• Heart & Thoracic Surgery (AREA)
• Medical Informatics (AREA)
• Molecular Biology (AREA)
• Surgery (AREA)
• Animal Behavior & Ethology (AREA)
• Physiology (AREA)
• Public Health (AREA)
• Veterinary Medicine (AREA)
• General Physics & Mathematics (AREA)
• Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)

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• 1980
  • 1980-07-03 JP JP81500933A patent/JPS57501013A/ja active Pending
  • 1980-07-03 AU AU69213/81A patent/AU6921381A/en not_active Abandoned
  • 1980-07-03 WO PCT/US1980/000839 patent/WO1982000088A1/en unknown
  • 1980-07-03 EP EP19810900698 patent/EP0055255A1/en not_active Withdrawn

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