EP0054740A2 - Durch Zenerdiodendurchbruch progammierbarer Festwertspeicher - Google Patents

Durch Zenerdiodendurchbruch progammierbarer Festwertspeicher Download PDF

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Publication number
EP0054740A2
EP0054740A2 EP81109508A EP81109508A EP0054740A2 EP 0054740 A2 EP0054740 A2 EP 0054740A2 EP 81109508 A EP81109508 A EP 81109508A EP 81109508 A EP81109508 A EP 81109508A EP 0054740 A2 EP0054740 A2 EP 0054740A2
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EP
European Patent Office
Prior art keywords
zener diode
programming
word line
zener
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP81109508A
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English (en)
French (fr)
Inventor
Donald L. Wollesen
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American Microsystems Holding Corp
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American Microsystems Holding Corp
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Filing date
Publication date
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Publication of EP0054740A2 publication Critical patent/EP0054740A2/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor memory devices, and more particularly to a programmable read only memory (PROM) device utilizing diffused zener diodes as the programming means.
  • PROM programmable read only memory
  • PROMs Semiconductor programmable read only memories
  • PROMs are well-known in the prior art.
  • PROMs consist of an array of memory cells, each cell capable of storing one bit, which may be programmed after the PROM has been completely fabricated and assembled. Once an individual cell is programmed, it may not later be changed or "reprogrammed”.
  • Transistor 9 is comprised of collector 13 of a semiconductor material doped with an inpurity of a first conductivity type, base 12 which is doped with an impurity of a conductivity type opposite to that of collector 13, and emitter 11 which is doped with an impurity the same conductivity type as, but to a higher conductivity than collector 13. In this fashion, either an NPNor a PNP transistor is formed. In- order to program this type of cell, sufficient emitter-collector current must be applied to form an electrical short (i.e., a low resistance path) between emitter 11 and collector 13 through base 12.
  • Typical emitter-collector currents required to form short 14 depend upon a variety of factors (such as base doping concentration and base width) and are in the range of 70 to 150 milliamps. It is therefore generally recommended by manufacturers of such PROMs that a programming current on the order of 200 milliamps be used, in order to ensure that desired shorts are formed, thereby programming desired cells. Due to the high programming current required, access devices associated with the programming means of each cell must be capable of handling such currents without themselves being physically damaged. For this reason, bipolar transistors are used as access devices in prior art PROM devices, due to their high current carrying ability.
  • FIG. 2 shows a schematic diagram of a portion of a prior art PROM device utilizing bipolar transistors as the programming means.
  • PROM device 100 contains bit lines B 1 and B 2 , and word lines-W 1 and W 2 .
  • the cell accessed by word line W 1 and bit line B 1 is labeled 11.
  • the cell accessed by word line W 1 and bit line B 2 is labeled 12.
  • the cell accessed by word line W 2 and bit line B 1 is labeled 21, and the cell accessed by word line W 2 and bit line B 2 is labeled 22.
  • Each cell is similarly constructed, and thus the following discussion of cell 11 applies equally to all cells in the memory array 100.
  • Memory cell 11 comprises access transistor T l1 having collector 1, base 2, and emitter 3.
  • Collector 1 is connected to bit line B 1 , and base 2 is connected to word line W 1 .
  • Emitter 3 is connected to collector 4 of programming transistor P 11 as shown.
  • Base 5 of programming transistor P 11 is floating, and emitter 6 is connected to bias line 91.
  • Connected to bit line B 1 is sense amplifier A 1 having output terminal O 1 .
  • Bias line 91 is connected to ground.
  • Bit line B 1 is accessed by connecting to it a source of positive potential. All other bit lines at this time are kept low.
  • Word line W 1 is accessed by applying a logical high. All other word lines are kept low at this time. With a high on word line W 1 , access transistor T11 turns on. The source of high potential connected to bit line B 1 is connected to collector 4 of programming transistor P 11 through access transistor T 11 . Programming transistor P11 conducts, due to the source of high potential being connected to its collector 4, causing reverse breakdown of the collector-base junction.
  • bias line 91 is connected to ground, bit line B 1 is accessed by applying a logical high, and word line W 1 is accessed by applying a logical high.
  • bit line B 1 and word line W 1 high, access transistor T 11 will conduct, applying the logical high from bit line B 1 to collector 4 of programming transistor P 11 . If programming transistor P 11 has been programmed, the high applied to collector 4 will cause current to flow through the short created between collector 4 and emitter 6 of programming transistor P 11 to bias lead 91, which is at ground. The current flow through access transistor T 11 and programming transistor P 11 to ground causes bit line B 1 to be pulled low.
  • each access transistor associated with a single programming transistor must be capable of carrying the high programming current without itself being damaged. Since the current required to program a bipolar transistor is on the order of 200 milliamps, the access transistor must be constructed to be rather large in order to be able to handle 200 milliamps without incurring any damage. This causes the size of each cell in the memory array to become rather large, and thus the size of the entire memory array, typically containing thousands of individual memory cells, becomes quite large.
  • MOS transistors are typically unable to handle nearly as much current as a bipolar transistor of like size, programming currents in excess of about 50 mA effectively preclude the use of MOS technology for PROM structures of this type, due to the large size required of the MOS transistors.
  • PROMs Another prior art method of constructing PROMs is to utilize refractory metal, such as nichrome, or polycrystalline silicon in such a manner as to form a fusible link.
  • refractory metal such as nichrome
  • polycrystalline silicon such as polycrystalline silicon
  • Fusible link 71 contains narrowing 72 such that region 72 acts as a fuse.
  • Such a burn-in technique does not eliminate the reliability problem of individual devices, or decrease the yield loss due to this grow-back phenomenon.
  • Prior art PROMs are generally constructed using bipolar techniques due to the higher current carrying abilities of bipolar transistors. While it is possible to utilize metal oxide silicon (MOS) access devices utilizing prior art PROM techniques, it is disadvantageous to do so, because MOS transistors must be made significantly larger than their bipolar counterparts for a given current carrying capacity.
  • MOS transistors are disclosed for example, in.United States Patents Nos. 3,191,151; 3,733,690;. 3,742,592 and 3,848,238.
  • This invention overcomes prior art difficulties in the manufacture of programmable read only memories by utilizing a lateral diffused zener diode as the programming means. Such a technique allows currents required to program each cell to be significantly reduced over the programming currents required in prior art devices. This reduction in programming currents allows a significant reduction in the size of the access transistor required for each memory cell, thereby allowing an entire memory array to be reduced significantly in size. Furthermore, the quality and reliability problems associated with prior art fusible link technology is eliminated. This invention also allows each cell to be reduced in size over prior art memory cells, due to the fact that the program means used is a zener diode, rather than larger bipolar transistors or fusible links. opening 73 as shown in Figure 3b.
  • the circuit of Figure 2 can be used to construct a PROM utilizing fusible links, where each programming transistor P 11 , P 12' P 21' and P 22 is replaced by a single fusible link. Programming and reading takes place in precisely the same manner as in the circuit shown in Figure 2, with the exception that programmed cells contain open fuses rather than shorted transistors. Typical current required to blow open a fusible link is again on the order of 70 to 200 milliamps. Thus, this technique also requires that each access transistor be rather large in order to carry the current required to program each fusible link without itself incurring any damage.
  • fusible link technology While many manufacturers prefer fusible link technology, there are inherent quality, manufacturing and reliability problems in this technology. First, the width and thickness of fusible links must be precisely controlled to ensure that each fusible link which is desired to be programmed will blow under specified programming currents. If a fusible link becomes too thick or too wide, the quality of the device will be poor because the fusible link will not blow open under specified programming currents, thereby causing a bit failure in the memory array.
  • the inherent reliability problem in fusible link technology is that even for fusible links which satisfactorily blow open during programming, there is the possibility that a blown open fusible link will grow back together due to metal or polycrystalline silicon migration.
  • the access means for each cell is a diode, further reducing the cell size over cells utilizing bipolar or MOS transistors as access devices.
  • the number of process steps in the fabrication of PROMs of this invention is reduced over the number of process steps in prior art techniques utilizing fusible links, wherein specific additional process steps are required to fabricate PROMs. No additional process steps are required in the fabrication of devices in accordance with this invention, as compared to standard prior art metal oxide silicon (MOS) processes.
  • MOS metal oxide silicon
  • FIG. 4 shows a cross-sectional view of a typical zener diode used in semiconductor circuits.
  • P region 112 is formed within substrate 111 as shown.
  • N+ region 113 is formed. Because N+ region 113 is contained within P region 112, this type of zener diode is known as a vertical zener diode.
  • the zener diode junction 119 is formed between N+ region 113, which serves as the cathode, and P region 112, which serves as the anode.
  • a lateral zener diode is shown in Figure 5.
  • P region 122 which serves as the anode, is formed within substrate 121.
  • N+ region 123 which serves as the cathode, is formed adjacent to region 122 as shown.
  • Zener junction 129 is formed at the interface between anode 122 and cathode 123.
  • vertical zener diodes are preferred over lateral zener diodes in that they are less prone to damage due to excessive voltages or currents being applied to the zener diode, and may be made smaller than lateral zener diodes for a given current carrying capacity.
  • most semiconductor manufacturers have designed their circuits to utilize vertical zener diodes rather than lateral zener diodes in applications where the regulating or clamping characteristics of zener diodes are desired.
  • a zener diode is used as a novel programming means in a PROM device, thereby allowing a reduction in cell size over the cell size in prior art structures which utilize a larger bipolar transistor as the programming means.
  • a zener diode is provided that is capable of being programmed, i.e., shorted, with the least amount of current, thereby allowing each cell's accessing means to be reduced in size, due to its decreased current handling requirements as compared with prior art PROM circuits.
  • Several lateral zener diodes were constructed to determine their programming characteristics.
  • the substrate is a (100) silicon wafer having an N conductivity type of approximately 3-5 ohm-cm.
  • This diode is formed utilizing standard masking techniques, and the following process.
  • a highly N+ doped layer of silicon dioxide containing approximately 7% phosphorus is deposited above the to-be-formed cathode to a thickness of approximately 4000 angstroms, utilizing well-known techniques.
  • This silicon dioxide layer is covered with a layer of approximately 2000 angstroms of undoped silicon dioxide. The total thickness of these two layers is within the range of approximately 5400 to 6600 angstroms.
  • the anode is formed by subjecting the to-be-formed anode region, which is not masked by silicon dioxide, to a P+ Boron predeposition utilizing BBr 3 as a Boron source (other P+ doping sources may be used). This is accomplished by a 5 minute push (the time it takes to insert a boat of wafers into a furnace), followed by an 8 minute soak, to allow the wafers to reach a uniform temperature, followed by a 5 minute source (where the wafers are subjected to the BBr 3 Boron source), and a 3 minute pull (removal of boat from the furnace).
  • the furnace temperature is maintained at approximately 1025°C during the predeposition, where both Phosphorous (from the doping vapox) and Boron are simultaneously diffused.
  • the Boron predeposition results in a V/I of approximately 7 + 1/2 ohms. Because of this doping method of simultaneous N+ and P+ doping, a self-aligned (no mask misalignment) lateral zener diode is formed where desired, thus there is no additional process steps required to fabricate these zener cells, unlike other prior art cells which require additional processing and masking steps.
  • the deposited Phosphorous doped silicon dioxide is then removed by standard etch methods.
  • the anode and cathode dopants are then diffused to the desired depth of approximately 1.2 microns by a reoxidation of both anode and cathode regions by subjecting the wafer to dry 0 2 at approximately 950°C utilizing a 5 minute push, 40 minute soak and 5 minute pull, plus subsequnt heat treatment, such as the well-known oxide reflow techniques. This results in a silicon dioxide layer of approximately 400 + 75 angstroms.
  • Contacts 315 and 316 provide a metallic (preferably aluminum) interconnection to regions 311 and 312, respectively, thereby allowing simple and efficient connection to external test instrumentation.
  • Junction 319 is formed between regions 311 and 312 of opposite conductivity types, thereby forming the zener diode junction.
  • the length of junction 319, labelled “1" in Figure 6, also referred to "edge”, is preferably 3 microns or less.. This junction is destroyed by a current of approximately 15 milliamps at approximately 14 volts. Initial device testing was done with an "edge” dimension of 10 microns; these devices would “program” at about 50 mA with about 18 volts applied.
  • Region 312 is formed of a first conductivity, and region 311 is formed within region 312, to the opposite conductivity.
  • Contacts 315 and 316 are formed to provide interconnection with regions 311 and 312, respectively.
  • Junction 329 is formed between regions 311 and 312. Devices are constructed in this fashion, having 60 microns of edge (therefore the perimeter of region 311 is 60 microns), utilizing the same starting material and process parameters as the device of Figure 6.
  • the zener diode labeled "P4" is constructed as shown in Figure 6, having 10 microns of edge process.
  • the zener diode labeled "P5" is constructed as shown in Figure 7 having 60 microns of edge, with region 311 being doped to an N+ conductivity to serve as the cathode, and region 312, serving as the anode, being doped to a P + conductivity process.
  • the edge of a zener diode constructed as shown in Figure 6 can be reliably made as narrow as 2-3 microns. This decrease in edge length will further reduce the power requirements during programming of a cell utilizing a zener diode as the programming means.
  • Test data for zener diodes constructed in a manner similar to device P4 and having 5, 4, 3 and 2 microns of edge is given in Attchments 4, 5, 6 and 7, respectively.
  • Typical depth for zener diodes constructed in the manner described for zener diode P4 is approximately 1.2 microns.
  • the depletion spread during reverse bias totals approximately .15 microns on both sides of the zener junction (approximately .075 microns on each side of the junction).
  • the volume in which the zener action occurs is thus approximately .36 cubic microns.
  • the power available for destroying the zener diode and forming a short during programming is thus 90 milliwatts.
  • the PROMs of this invention do not exhibit the reliability problems associated with prior art fusible link PROMs.
  • the quality of PROM devices utilizing zener diodes as the programming means is also improved over prior art fusible link devices, because the characteristics of zener diodes are more highly controllable during fabrication processes than are the charactertistics of fusible links.
  • Memory cell 140 is comprised of word line 141, power line 142, and bit line 148.
  • N channel MOS access transistor 143 has its source 144 connected to word line 141, its gate 145 connected to bit line 148, and its drain 146 connected to anode 150 of programming means zener diode 147.
  • Cathode 151 of zener diode 147 is connected to power line 142 as shown.
  • the cell is accessed by applying a high to bit line 148 and a low to word line 141.
  • Power line 142 is maintained high, but at a voltage level (5 volts, for example) less than that applied to power line 142 during programming.
  • the high applied to word line 148 causes access transistor 143 to conduct.
  • zener diode 147 will be a short circuit of very low resistivity, and the high from power line 142 will be applied to word line 141.
  • a sense- amplifier (not shown) connected to word line 141 detects this high and provides an output signal indicative of-the fact that cell 140 has been programmed.
  • zener diode 147 will remain an open circuit, because the positive voltage applied to power line 142 during the read operation is insufficient to cause zener breakdown of zener diode 147.
  • the high from power line 142 is not connected to word line 141 and word line 141 remains low.
  • the sense amplifier connected to word line 141 detects this low and provides an output signal indicative of the fact that memory cell 140 has not been programmed.
  • FIG. 8b Another embodiment of memory cell 140 of this invention is shown at Figure 8b. Principles of operation of this circuit are similar to those of the circuit of Figure 8a just discussed, with the exception that zener diode 147 is reversed as shown. Utilizing an N channel access transistor 143, power line 142 is connected to ground during programming, and word line 141 is connected high during programming and reading. This approach allows smaller cell construction in that a single N doped region may serve as source 146 of access transistor 143 and cathode 151 of zener diode programming means 147. However, in the circuit of Figure 8b, access transistor 143 is a source follower, which has the disadvantage of having less gain than the common source configuration of Figure 8A due to body bias coefficient.
  • a parasitic junction field effect transistor is formed between the substrate and gate 145 of access transistor 143, thus tending to pinch off the channel.
  • the load (zener.) is connected between ground and the source with the drain being most positive, thus eliminating the tendency of the parasitic JFET to pinch off the channel (as shown in Figure 8a).
  • Figure 8c is a top view of two adjacent memory cells constructed in accordance with the embodiment of this invention shown in Figure 8b.
  • Figure 8d is a cross-sectional view of the structure of Figure 8c, taken along line 8d-8d.
  • Word line 148 forms gate 145a of access transistor 143a, and gate 145b of access transistor 143b.
  • Bit line 148a is connected through contact 244a to N+ region 144a which serves as the drain of access transistor 143a.
  • bit line 148b is connected through contact 244b to N+ region 144b which serves as the drain of access transistor 143b.
  • the memory cells of Figures 8a and 8b may be constructed utilizing N channel, P channel, CMOS and bipolar accessing transistors.
  • word lines 141 and power lines 142 may be interchanged without destroying the principals of this invention.
  • N channel access transistors are preferred over P channel access transistors due to the greater current carrying ability of an N channel transistor compared to a P channel transistor of the same size. This greater current carrying ability is caused by the greater mobilities of electrons, which form the N channel, than holes, which form the P channel.
  • N channel access transistor 143 in the circuit of Figure 8 Utilizing an N channel access transistor 143 in the circuit of Figure 8 is a practical approach. However, if a P channel access transistor 143 is utilized, the same P region may serve as source -146 of access transistor 143 and anode 150 of zener diode 147 in Figure 8a. However, using a P channel access transistor 143 in a source follower configuration requires access transistor 43 to be slightly larger with its decreased gain over common source circuits.
  • FIG. 9 Another embodiment of this invention is shown in the circuit of Figure 9. As shown, this embodiment utilizes zener diode 147 as the programming means, and diode 143 as the access means for cell 140. This is in contrast to prior art circuits such as disclosed in United States Patent Number 3,191,151, where semiconductor diodes are used as the programming, means, as opposed to the use in this invention of zener diodes which are programmed with very low power.
  • the cell 140 is accessed by placing a low on bit line 148 and a high on word line 141. The high potential placed on word line 141 is sufficient to cause programming means zener diode 147 to short out.
  • a high is again placed on word line 141; however, this high potential is selected to be insufficient to cause a zener breakdown of an unprogrammed zener diode 147.
  • the high applied to word line 141 will be applied through shorted zener diode 147 to access diode 143, which will become forward biased, thereby connecting the high to bit line 148.
  • the high placed on word line 141 will be insufficient to cause a zener breakdown of zener diode-147, and thus will not cause access diode 143 to be forward biased, and thus will not cause bit line 148 to go high.
  • a sense amplifier connected to bit line 148 (not shown) will provide an output signal indicative of whether memory cell 140 is a programmed or an unprogrammed cell.
  • zener diode access means 143 may be replaced with a semiconductor diode, rather than a zener diode.
  • Two common anode zener diodes 30 and 31 are formed within P- well 12 by N+ regions 16 and 18, and P+ region 17 formed therebetween.
  • the schematic diagram of Figure 11 shows the two memory cells contained in Figure 10.
  • Base terminal 21 is connected to word line 21 of Figure 11.
  • base terminal 25 of Figure 10 is connected to word line 25 of Figure 11.
  • Collectors 10 are connected in common to lead 10, which is the substrate.
  • Bit line 23 is connected to P+ region 17 which forms the anode of zener diodes 30 and 31.
  • Cathode 16 of zener diode 30 is connected to emitter 15 of transistor 40
  • Cathode 18 of zener diode 31 is connected to emitter 19 of transistor 41.
  • This technique allows the use of a parasitic bipolar transistor which is present in CMOS structures, thus allowing smaller cell size when fabricated with a CMOS process which uses epitaxial substrate material (with its resulting low collector saturation resistance) than circuits utilizing MOS transistors as the access device.
  • a parasitic bipolar access transistor Utilizing a parasitic bipolar access transistor, and 5 micron technology presently available to the semiconductor industry, a memory cell of approximately 6 square mils may be formed.
  • the zener diodes used in each embodiment of this invention may be either diffused zener diodes, ion-implanted zener diodes, or polycrystalline silicon zener diodes which are formed on the surface of the silicon wafer. Diffused ion-implanted and polycrystalline silicon zener diodes may be constructed as either lateral or vertical diodes. Typical thicknesses for diffused and ion implanted- zener diodes are on the order of 1.2 microns or less. Typical thicknesses for polycrystalline silicon zener diodes are on the order of .4 microns or less. Thus, because of their smaller junction area resulting from their small thickness, polycrystalline silicon diodes can be destroyed, or programmed, with less power.
  • bit lines, word lines and power lines As cell size decreases, the size of associated bit lines, word lines and power lines also decreases. For sufficiently small cells, these conductive lines must be formed of metal, with a typical resistivity of approximately 0.1 ohms/square or less. Polycrystalline silicon cannot be used as conductive lines in very small structures, because its resistivity is approximately 30-40 ohms/square which results in excessive IR drops, thus preventing sufficient current flow to program desired cells.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP81109508A 1980-12-23 1981-11-04 Durch Zenerdiodendurchbruch progammierbarer Festwertspeicher Withdrawn EP0054740A2 (de)

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US22020880A 1980-12-23 1980-12-23
US220208 1980-12-23

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0426241A2 (de) * 1989-10-31 1991-05-08 STMicroelectronics S.r.l. Verfahren zur Herstellung einer Komponente für die Begrenzung der Programmierungsspannung und für die Stabilisation der Spannung in einer elektrischen Anordnung mit EEPROM-Speicherzellen
WO2003054971A1 (de) * 2001-12-21 2003-07-03 Austriamicrosystems Ag Zenerdiode, zenerdiodenschaltung und verfahren zur herstellung einer zenerdiode
EP1920441A2 (de) * 2005-08-31 2008-05-14 International Business Machines Corporation Elektrisch programmierbares e-fuse-rom mit direktzugriff
CN114551237A (zh) * 2022-04-28 2022-05-27 广州粤芯半导体技术有限公司 集成在半导体结构中的烧录器的制作方法及其版图结构
CN114551238A (zh) * 2022-04-28 2022-05-27 广州粤芯半导体技术有限公司 集成在半导体结构中的烧录器的制作方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0426241A2 (de) * 1989-10-31 1991-05-08 STMicroelectronics S.r.l. Verfahren zur Herstellung einer Komponente für die Begrenzung der Programmierungsspannung und für die Stabilisation der Spannung in einer elektrischen Anordnung mit EEPROM-Speicherzellen
EP0426241A3 (en) * 1989-10-31 1991-11-27 Sgs Thomson Microelectronics Process for the manufacture of a component to limit the programming voltage and to stabilise the voltage incorporated in an electric device with eeprom memory cells
WO2003054971A1 (de) * 2001-12-21 2003-07-03 Austriamicrosystems Ag Zenerdiode, zenerdiodenschaltung und verfahren zur herstellung einer zenerdiode
US7485947B2 (en) 2001-12-21 2009-02-03 Austriamicrosystems Ag Zener diode and method for production thereof
EP1920441A2 (de) * 2005-08-31 2008-05-14 International Business Machines Corporation Elektrisch programmierbares e-fuse-rom mit direktzugriff
EP1920441A4 (de) * 2005-08-31 2009-04-29 Ibm Elektrisch programmierbares e-fuse-rom mit direktzugriff
US7817455B2 (en) 2005-08-31 2010-10-19 International Business Machines Corporation Random access electrically programmable e-fuse ROM
CN114551237A (zh) * 2022-04-28 2022-05-27 广州粤芯半导体技术有限公司 集成在半导体结构中的烧录器的制作方法及其版图结构
CN114551238A (zh) * 2022-04-28 2022-05-27 广州粤芯半导体技术有限公司 集成在半导体结构中的烧录器的制作方法

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