EP0031834B1 - Dwell circuitry for an ingnition control system - Google Patents

Dwell circuitry for an ingnition control system Download PDF

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Publication number
EP0031834B1
EP0031834B1 EP80901351A EP80901351A EP0031834B1 EP 0031834 B1 EP0031834 B1 EP 0031834B1 EP 80901351 A EP80901351 A EP 80901351A EP 80901351 A EP80901351 A EP 80901351A EP 0031834 B1 EP0031834 B1 EP 0031834B1
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EP
European Patent Office
Prior art keywords
count
terminal
dwell
signal
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
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EP80901351A
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German (de)
English (en)
French (fr)
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EP0031834A4 (en
EP0031834A1 (en
Inventor
Rupin Jayant Javeri
Adelore Francis Petrie
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Motorola Solutions Inc
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Motorola Inc
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Priority claimed from US06/049,013 external-priority patent/US4329959A/en
Priority claimed from US06/049,014 external-priority patent/US4300518A/en
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0031834A1 publication Critical patent/EP0031834A1/en
Publication of EP0031834A4 publication Critical patent/EP0031834A4/en
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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P3/00—Other installations
    • F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
    • F02P3/04—Layout of circuits
    • F02P3/045—Layout of circuits for control of the dwell or anti dwell time
    • F02P3/0453—Opening or closing the primary coil circuit with semiconductor devices
    • F02P3/0456—Opening or closing the primary coil circuit with semiconductor devices using digital techniques
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
    • F02P5/00—Advancing or retarding ignition; Control therefor
    • F02P5/04—Advancing or retarding ignition; Control therefor automatically, as a function of the working conditions of the engine or vehicle or of the atmospheric conditions

Definitions

  • the present invention relates generally to the field of digital signal processing circuitry, and more particularly to the field of digital electronic dwell circuits used in ignition control systems which control spark and dwell occurrence.
  • prior art dwell circuits such as U.S.-A-4,018,202 utilize a complex and costly cam structure having an extremely large number of individual teeth projections in order to produce a series of high resolution crankshaft position pulses, typically one pulse being produced for every one degree of crankshaft rotation.
  • the construction of these cams is costly and their utilization would tend to inhibit utilization of the same cam to produce other crankshaft position pulses which would occur at other than one degree increments of crankshaft rotation.
  • this deficiency can be overcome by utilizing additional cams and additional crankshaft position sensors, but then the cost of the ignition control system would be increased. While the one degree pulses can be electronically realized by dividing up large angular crankshaft pulses, this would also add to the cost of an ignition control system.
  • the one degree crankshaft position pulses produced by the prior art dwell circuits represent speed dependent crankshaft position pulses and enable the prior art circuits to readily calculate ignition dwell as a fixed number of degrees of crankshaft rotation.
  • these circuits have problems in realizing a constant dwell time, rather than constant dwell angle, which is desired for some engine operative conditions.
  • prior dwell circuits such as U.S.-A-4,018,202 require complex feedback circuits having marginal stability.
  • Some dwell circuits such as those in U.S.-A--3,908,616 utilize speed independent pulses in order to calculate ignition dwell. While these circuits have eliminated the need for a multi-tooth crankshaft cam or its electronic equivalent for producing high resolution crankshaft position pulses, the disclosed circuit designs cannot produce large dwell angles which are required at high engine speeds.
  • the dwell circuit in US-A-3,908,616 contemplates adjusting count thresholds in order to adjust the dwell occurrence and/or contemplates adjusting the rate at which pulse counting takes place. In order to implement either of these two functions, relatively complex and costly control structures are required.
  • a known digital circuitry for receiving a signal comprising periodic pulse transitions and producing indicative signals at times prior to the occurrence of the periodic pulse transitions is summarised in the precharacterizing portion of Claim 1 and is known from US-A-4052967.
  • the dwell circuitry includes means to develop a running count by counting oscillator pulses between first and second time occurrences corresponding to the ignition initiating signal.
  • the count occurring at the second time occurrence which is the maximum running count, is stored and subsequently has subtracted therefrom a predetermined number of counts to obtain a resultant subtracted count. Thereafter, the resultant subtracted count is compared with the current running count and upon the occurrence of an equality an indicating signal is produced which initiates dwell.
  • the present invention is summarized in the characterizing portion of Claim 1.
  • the present invention overcomes the problems of the prior art by having the first and second time occurrences directly related to the occurrence of the first and second pulse transitions of said periodic signal.
  • the provision of a means for counting down the resultant subtracted count avoids the necessity to use comparators in adddition to which the incrementing of the count is at a rate independent of the said variable repetition rate after the said second time occurrence.
  • the dwell circuit of the present invention is contemplated as being utilized in an ignition dwell and spark control system in which the circuitry which produced the running count also is utilized to determine spark occurrences. This double utilization of the running count by both the dwell and spark timing circuits of an ignition control system reduces the cost of the ignition control system.
  • FIG. 1 illustrates an electronic ignition control system 10 for a two cylinder internal combustion engine (not shown).
  • the control system 10 receives sensor input signals and develops control signals that determine the spark timing and dwell (coil excitation time) for a distributorless inductive ignition system.
  • the term "distributorless” contemplates the fact that no rotating mechanical distributor will be utilized, and that instead sparks will be created in each of the two cylinders simultaneously but at different times with respect to the compression cycle of each cylinder. In other words, when a spark is generated by cylinder 1 at the proper time of its compression cycle, a spark will also be generated in cylinder 2 but this spark will occur during the exhaust cycle of cylinder two and therefore will not result in igniting a fuel mixture.
  • Distributorless ignition systems are known and do not form an essential part of the present invention.
  • the control system 10 includes a rotating cam 11 synchronously rotatable with a crankshaft of a two cylinder engine, the crankshaft being shown schematically as an axis of rotation 12.
  • the cam 11 has a peripheral projection 13 spaced from the axis 12 and the cam 11 is contemplated as rotating in a clockwise direction.
  • An advance sensor 15 is contemplated as having a sensing probe 16 positioned at a fixed location with respect to the rotating cam 11, and a reference sensor 17 is contemplated as having a sensing probe 18 similarly positioned with the probes 16 and 18 being spaced apart by 35 degrees of angular rotation of the cam 11 (which corresponds to 35 degrees of engine crankshaft rotation).
  • the probes 16 and 18 produce crankshaft angular position pulses as the projection 13 rotates by these probes with the produced position sensing pulses initially occurring in response to the passage of a leading edge 13a of the projection passing by the sensing probes and the position pulses terminating after a trailing edge 13b has passed by the probes 16 and 18.
  • the advance sensors 15 and 17 receive input signals from their corresponding sensing probes and produce digital pulse outputs in correspondence thereto at output terminals 19 and 20, respectively.
  • the positioning of the sensing probes 16 and 18 with respect to the rotating cam 11 and its projection 13 is not totally arbitrary and that it is contemplated that the probe 16 is positioned such that it defines the maximum possible advance (earliest possible spark ignition occurrence for a cylinder compression cycle) for the ignition system 10 while the probe 18 defines the minimum possible advance (generally corresponding to top dead center of cylinder position which is generally termed zero or reference advance).
  • the positioning of the probes 16 and 18 define the earliest and latest possible occurrences of spark ignition, respectively, for the ignition control system 10. The significance of this will be demonstrated subsequently.
  • the advance and reference output terminals 19 and 20 are coupled as inputs to advance and reference buffers 21 and 22, respectively, which impedance isolate the sensors from subsequent circuitry and insure the production of precise, uniform magnitude corresponding digital pulses at the output terminals 23 and 24, respectively.
  • Figures 9A and 98 illustrate the sensing pulses produced at the terminals 23 and 24, respectively, and illustrate that these pulses occur periodically at times t A and t R corresponding to the passage of the leading edge 13a past the sensing probes 16 and 18.
  • the control system 10 includes a master clock oscillator 25 which produces clock timing pulses Cp at an output terminal 26 wherein the frequency of the clock oscillator is preferably 149.25 KHz.
  • the clock pulses Cp are illustrated schematically in Figure 9C on a greatly expanded horizontal time scale and are continuously produced by the oscillator 25 regardless of the angular position of the crankshaft of the engine.
  • a prescaler 27 is shown as being integral with the clock oscillator 25 and producing output signals C 1 through C 4 at the output terminals 28 through 31, respectively.
  • the prescaler essentially comprises a series of counters which receive the clock signals Cp and produce related lower frequency signals by essentially counting and thereby frequency dividing down the oscillator signal pulses Cp.
  • the prescaler 27 has a reset terminal 32 which causes resetting of the counters internal to the prescaler 27.
  • the signals developed by the clock oscillator 25 and prescaler 27 at the terminals 26 and 28 through 31 essentially determine the operation of the ignition control system 10 in conjunction with the pulses sensed by the advance and reference probes 16 and 18.
  • the signals produced at the terminals 28 through 31 are essentially used in various counters included in the ignition control system 10 and therefore the provision for resetting the internal counters in the prescaler 27 via the reset terminal 32 is required to insure that the counters receiving their inputs in accordance with the signals at the terminals 28 through 31 will be synchronized with the advace sensor signal S 1 described below.
  • a pulse synchronizer 33 receives an advance signal input from the terminal 23 and the clock pulse signal Cp from the terminal 26.
  • the pulse synchronizer produces a synchronized advance pulse S 1 at an output terminal 34.
  • the synchronizer 33 insures that a pulse S 1 is produced at the terminal 34 at a time t 1 which corresponds to the first clock pulse Cp that occurs after the time t A .
  • the signal S 1 (shown in Figure 9D) represents an advance pulse which is synchronized with the occurrence of the clock pulses Cp.
  • the pulse synchronizer 33 also receives an input at a terminal D from an output terminal 35 of an inhibit circuit 36.
  • the inhibit circuit 36 produces a 4 millisecond delay pulse at the terminal 35 in response to the occurrence of the spark ignition and this delay or inhibit signal at the terminal 35 prevents the pulse synchronizer from producing an output at the terminal 34 for 4 milliseconds after the occurrence of spark ignition. The reason for this is to quiet the output of the synchronizer 33 such that additional sparks will not be initiated by the synchronizer 33 until at least 4 milliseconds has elapsed since the last spark occurrence.
  • a pulse synchronizer 37 is similar to the synchronizer 33 and receives inputs from the reference sensor terminal 24 and the clock pulse terminal 26 and produces a synchronized reference pulse signal S 2 at an output terminal 38.
  • the synchronizer 37 merely insures that a reference signal S 2 has an initial time occurrence which precisely corresponds to the occurrence of one of the clock pulses Cp. Since it is contemplated that the frequency of occurrence of the clock pulse Cp is very high (higher than all other timing signals C 1 ⁇ C 4 ), this synchronization results in substantially no loss in accuracy for the present system, due to delaying advance and reference timing by one clock pulse, but does insure that the reference pulse S 2 , as well as the advance pulse S 1 , will occur in synchronism with the clock pulse Cp.
  • the reference signal S 2 is illustrated in Figure 9E as comprising periodic pulses which occur at the times t 2 . It should be remembered that the duration of time between the occurrence of the advance pulses S 1 at t, and the reference pulses S 2 at the times t 2 corresponds to 35 degrees of engine crankshaft rotation. Of course the actual time duration between t 1 and t 2 will vary directly as a function of engine speed.
  • a delay circuit 39 receives the signal S 1 along with the clock pulses Cpand produces a delayed output signal SD at an output terminal 40. Essentially, the delay circuit 39 receives the synchronized.signal S 1 , delays this signal by one full period of the clock pulse signal Cp and produces this delayed signal S 1 D at the terminal 40.
  • Figure 9F illustrates this delay advance signal S 1 D which has a time occurrence at t 1 D that is one clock pulse period later than the time occurrence t 1 .
  • the reason for creating the delayed advance signal S 1 D is that in many cases the control system 10 will transfer accumulated counts at the times t 1 in response to the pulses S 1 , and subsequently the accumulated counts are to be reset. Obviously the transference and resetting cannot occur simultaneously, thus the present system provides for delaying the resetting until after transference.
  • the ignition control system 10 essentially utilizes a main up-counter 41 to linearly count up C 1 pulses occurring at the terminal 28 in between the occurrence of delayed advance signal pulses S 1 D. This is accomplished by having the main up-counter 41 receive its counter input from the terminal 28 while its reset terminal is directly connected to the terminal 40. The counter 41 therefore periodically linearly accumulates a speed independent running count which has a maximum value directly related to engine speed since the counting occurs during the times t,D which occur every 360 degrees of crankshaft rotation.
  • Figure 9H illustrates a waveform representative of the linearly incremented running count of the counter 41. It should be noted that individual counting steps have not been illustrated in Figure 9H since these steps occur at the relatively high frequency of the signal C, produced by the prescaler 27. However, Figure 9N does illustrate the count in the main counter 41 on a very expanded horizontal time scale, and this figure clearly illustrates the incremental nature of the accumulated count in the counter 41.
  • the accumulated count of counter 41 is produced at 6 output terminals 42 through 47 with terminal 42 corresponding to the least significant bit and terminal 47 corresponding to the most significant bit.
  • the main up-counter 41 represents a 6 bit binary counter.
  • Such counters are well known and readily available. It should be noted that while the electronic ignition control system 10 utilizes the maximum accumulated count obtained by the counter 41 as an indication of engine speed, the ignition system 10 also utilizes each incremental count produced by the counter 41 at its output terminals 43 through 47 as control signal inputs to spark time occurrence circuitry within the system 10, and these incremental counts are utilized to produce a desired non-linear spark occurrence versus engine speed characteristic. The manner in which this is accomplished will now be discussed.
  • Each of the output terminals 43 through 47 of the main up-counter 41 are coupled as inputs to a read only memory (ROM) device 48 which has 4 output terminals 49 through 52 which are coupled as control signal inputs to a rate multiplier device 53.
  • the rate multiplier 53 receives a continuous stream of input clock pulses C 2 via a direct connection to the terminal 29 and produces a corresponding output pulse stream at an output terminal 54 in accordance with the control signals received from the terminals 49 through 52.
  • the rate multiplier device 53 is set by the pulse S, which is received via a direct connection from the terminal 34, and this reinitiates the operation of the rate multiplier 53.
  • the rate multiplier essentially functions as a controllable frequency divider which multiplies (actual divides) the frequency of the input pulse stream by predetermined integers which are determined by the control signals received from the ROM. Rate multipliers are well known and are readily available.
  • the ROM 48 functions as a look-up table device which produces different control signals at the terminals 49 through 52 that control the frequency multiplication (division) provided by the rate multiplier 53.
  • the end result is that the output pulse count produced at the terminal 54 is a non-linear function of engine speed such that a desired spark ignition occurrence versus engine speed characteristic can be obtained.
  • the accumulator means effectively integrates or accumulates the pulse count at the terminal 54 and determines, between S 1 pulses, a maximum pulse count non-linearly related to engine speed. This maximum pulse count is then utilized to determine spark ignition.
  • U.S.-A-4,104,997 illustrates an analog system in which a desired non-linear spark occurrence versus engine speed characteristic is produced by controlling the rates of charging and discharging a capacitor.
  • the ROM 48 and rate multiplier 53 digitally implement an equivalent function for controlling the rate of pulses produced at the terminal 54, and an accumulator means integrates these pulses to produce the desired result.
  • Figure 8 illustrates the desired advance angle (spark timing occurrence) versus engine speed characteristic which is desired by issued U.S.-A-4,104,997 and which is a typical characteristic also desired by the present system.
  • the present system contemplates providing the read only memory 48 with an additional input signal at an input terminal 55 wherein this additional signal represents the output of a pulse width modulator circuit 56 having its output terminal 57 directly connected to the terminal 55.
  • the pulse width modulator 56 receives an analog signal at an input terminal 58 wherein the magnitude of this analog signal is related to a predetermined engine condition, in the present case related to the magnitude of sensed engine vacuum pressure.
  • the pulse width modulator 56 will then produce a periodic digital two state signal which has a duty cycle (ratio of one logic state to the other during one cycle period) which is related to the magnitude of this analog signal.
  • the effect of applying a pulse width modulation signal as an input at the terminal 55 of the ready only memory 48 results in providing a continuous interpolation capability between the two extreme control output produced at the terminals 49 through 52 in response to the terminal 55 having a high or low logic state.
  • the ROM 48 need only store a maximum and minimum output corresponding to whether the signal at the terminal 55 is either high or low. In the present case these maximum and minimum outputs correspond to the sensed vacuum pressure being above or below a predetermined vacuum pressure.
  • the actual outputs produced at the terminals 49 through 52 are then made to represent a value more directly indicative of the magnitude of the analog voltage at the terminal 58 by first producing a digital two stage signal whose duty cycle varies in accordance with the analog signal magnitude and then by applying this signal to the input terminal 55.
  • the read only memory output will be switched back and forth between these two extreme outputs such that the average output of the read only memory will represent any output value in between these two extreme outputs which are stored in the read only memory.
  • the read only memory of the present system need only store two output limits in response to any desired engine condition and an average ROM output corresponding to any magnitude between these two output limits can be obtained merely by using a duty cycle pulse width modulated input signal to the read only memory. This permits saving an enormous amount of read only memory storage space while still enabling the output of the read only memory to have a high resolution correspondence with respect to the magnitude of the input analog signal. To obtain an equivalent resolution by any of the prior art references could not be digitally accomplished unless an extremely large read only memory capacity was utilized. The present system minimizes the read only memory capacity and therefore implements this function with a substantial cost savings.
  • the present system contemplates an engine vacuum pressure sensor 59 supplying an analog signal to the input terminal 58 of the pulse width modulator 56.
  • the analog signal magnitude is representative of the state of engine vacuum pressure.
  • Terminals 42 through 44 of the main counter 41 are also received by the pulse width modulator 56 which produces an output at terminal 57.
  • FIG. 2 illustrates typical embodiments for the vacuum sensor 59 and the pulse width modulator 56 both shown dashed in Figure 2.
  • the vacuum sensor 59 is contemplated as comprising a two position vacuum sensing switch 60 with a wiper arm terminal coupled to ground and the wiper varying between a first terminal 61 when sensed engine vacuum pressure is below a predetermined threshold value and a second terminal 62 when the sensed vacuum pressure is above this predetermined value.
  • the terminal 62 is coupled to a B+ terminal through a resistor 63 and is coupled to the terminal 58 through a resistor 64.
  • a capacitor 65 is coupled from the terminal 58 to ground.
  • the pulse width modulator circuit 56 comprises a DC level comparator 66 having a negative input terminal coupled to the input terminal 58 through a resistor 67. Limiting diodes 68 and 69 are also connected to the negative input terminal of the comparator 66 and essentially limit the signals received by the comparator to magnitudes either one diode drop above B+ or one diode drop below ground.
  • the terminals 42 through 44 are received as inputs to a NAND gate 70 whose output is coupled through an inverter 71 to a control terminal 76 of an FET gate 72.
  • An output terminal of the gate 72 is coupled to a positive input terminal 75 of the comparator 66 which is also coupled to B+ through a resistor 73 and to ground through a capacitor 74.
  • the output of the comparator 66 is directly coupled to the output terminal 57 of the pulse width modulator 56.
  • the signals at the terminals 42 through 44 are converted by the NAND gate 70 into a relatively slow periodically occurring pulse signal which is used as the control signal for the FET gate 72.
  • This control signal is illustrated in Figure 9K.
  • the positive input terminal (terminal 75) of the comparator 66 is shorted to a positive reference voltage just above ground potential by the gate 72.
  • the FET gate 72 is open circuited until the next occurrence of a control pulse at its control terminal 76.
  • Figure 9K illustrates the control signals at the terminal 76
  • Figure 9L illustrates the signal waveforms produced in response thereto at the positive input terminal 75 of the comparator 66.
  • Figure 9M shows the output signal of the comparator 66 produced in response to the signal shown in Figure 9L being created at the positive input terminal 75 while the negative terminal of the comparator 66 receives a transitional voltage corresponding to the dashed level 79 shown in Figure 9L.
  • Figure 9M illustrates that the output of the comparator 66 is a digital two state logic signal in which the duty cycle of this signal varies in accordance with the magnitude of the analog signal produced at the terminal 58. For a no vacuum condition corresponding to the level 77 present at the negative input terminal of the comparator 66, the output of the comparator 66 would remain at zero, and for a voltage at the negative input terminal corresponding to the level 78, the output of the comparator 66 would always be high.
  • Figure 9M illustrates that for interim values of vacuum (in the case of a continuous analog sensor being used instead of a two position vacuum sensing switch) or in the case of a slowly changing signal representing changing from vacuum to non-vacuum and back again (when a two position vacuum sensing switch is used), an analog signal is produced at the terminal 58 which results in a varying duty cycle signal being produced as the output of the comparator 66.
  • this varying duty cycle signal applied to the input of the ROM 48 allows the output of the ROM to vary, in a periodic stepwise manner, between two maximum limits and this produces an output whose average value will be directly related to the magnitude of the analog signal at the terminal 58.
  • an accumulator means essentially follows the rate multiplier 53 and effectively converts the pulse count at the terminal 54 into an integrated or accumulated maximum count. It is this accumulation step that results in effectively averaging the different control signal outputs produced at the ROM output terminals 49 and 52 by use of the pulse width modulator 56 altering the duty cycle of the input ROM control signal at the terminal 55.
  • Figure 9N represents the incremental count, incrementing at twice the frequency of the clock pulse signal C i , commenced at the times ti D by the main up-counter 41 on the control terminals 43 through 47 coupled to the ROM 48. After the main counter 41 receives two C 1 pulses the count of the main counter, as recorded on the output terminals 43 through 47, is incremented one count.
  • the horizontal axis represents an expanded time scale whereas the vertical axis represents the stepped count stored by the terminals 43 through 47.
  • Figure 90 represents maximum and minimum rates of increase SL, and SL 2 determined by the output terminals 49 through 52 of the read only memory 48.
  • the count of the main counter is incremented by counting C 1 pulses such that the terminal 43 now indicates a new count as an input signal to the read only memory 48.
  • a different input control signal is now received by the read only memory 48 and the output terminals 49 through 52 of the ROM now are able to implement different rates of increase SL 3 and SL 4 .
  • the rates of increase SL,-SL 4 represent different fixed integers used by the rate multiplier for frequency division.
  • the ROM 48 can select either of two different rates of increase for the count processed by the rate multiplier 53 because for any main count received as an input by the ROM 48 from the counter 41, either a zero or one logic state can be produced by the pulse width modulator 56 at the input terminal 55.
  • Figure 90 illustrates the different characteristics for rates of pulse count increase at terminal 54 that can be implemented by the rate multiplier 53 in accordance with the control input signals received by the read only memory 48 which supplies control inputs to the rate multiplier.
  • the present system contemplates selectively switching between maximum rates of increase such as SL 1 and SL 3 and minimum rates of increase such as SL 2 and SL 4 during the times t 1 D ⁇ T 1 and after t 1 , respectively, to obtain a composite (average) rate of increase which can be anywhere within the limits defined by the maximum and minimum rates of increase.
  • the output of the rate multiplier 53 at the output terminal 54 is effectively coupled to an accumulator means which accumulates a count related to the total pulse count produced at the output terminal 54.
  • This accumulator means essentially comprises a select decoder 80, a main advance up-down counter 81 and an auxiliary advance up counter 82.
  • the rate multiplier output terminal 54 is coupled as an input to both the select decoder 80 and a counter terminal (>) of the auxiliary advance up counter 82.
  • the auxiliary advance up counter 82 receives a reset signal by means of a direct connection to the terminal 34 at which the S 1 pulses are produced.
  • the up counter 82 is a four bit binary counter and produces count outputs at terminals 83 through 86 which are coupled as inputs to preset terminals P 1 through P 4 or the main advance up-down counter 81.
  • the select decoder 80 receives three inputs in addition to the input from the rate multiplier output terminal 54 and produces a main output at a pulse terminal 87 and a latched advance output signal S I L at a terminal 88.
  • the select decoder 80 receives the delayed advance pulses S ⁇ D by means of a direct connection to the terminal 40, and the decoder also receives the pulses C 3 from a direct input connection to the terminal 30.
  • the select decoder 80 also receives an input signal termed SSp from a spark logic circuit 90.
  • the signal SSp is a signal produced by the spark logic circuit 90 at the desired time occurrence t x of spark ignition and this signal is very short in duration (one period of the high frequency clock pulse signal Cp).
  • the manner in which the spark logic circuit 90 creates the signal SSp will be subsequently discussed. For the time being it is sufficient to note that this signal occurs at times tx which represents the time at which spark ignition will occur according to the ignition control system 10.
  • the latched output signal S,L produced at this terminal is initiated in response to the delayed advance signal S 1 D and is terminated at the time t x .
  • the output produced by the select decoder 80 at the main output terminal 87 essentially comprises the pulse signal C 3 during the pulses S,D (occurring at the times t,D) until the time t x at which spark ignition occurs. After the times t x until times t 1 D the decoder 80 directly couples pulses at the rate multiplier output terminal 54 to the main terminal 87.
  • the terminal 88 of the select decoder 80 is directly coupled as an input to an up-down control terminal (U/D) of the main up-down advance counter 81.
  • the terminal 87 of the select decoder is directly coupled to an input clock terminal (>) of the advance counter 81.
  • a preset enable (PE) input terminal of the advance counter 81 directly receives the signal SSp by means of a direct connection to the output terminal 89 of the spark logic circuit 90.
  • An input reset terminal of the advance counter 81 receives a power on reset signal POR by means of a direct connection to a terminal 91.
  • This power on reset signal is merely utilized to initiate operation of the ignition control system 10 in response to the initial application of power to the ignition control system. This is accomplished by means of a capacitor 92 coupled between the terminal 91 and a power on reset terminal 93 that receives positive power when power is applied to the ignition system control 10.
  • the terminal 91 is coupled to ground through a resistor 94A.
  • the components 92, 93, 94A provide for a positive impulse at terminal 91 upon the first application of power to the power on reset terminal 93, and this is utilized to initiate the resetting of the advance counter 81.
  • the advance counter 81 produces an output at a zero detect terminal 94 and this output is produced whenever the advance counter counts down to or through a count of zero.
  • the auxiliary advance counter 82 is reset at the times t 1 by the S 1 pulses.
  • the counter 82 then proceeds to count up in accordance with the pulses passed by the rate multiplier 53 and provided at the output terminal 54. This count is registered in the four bit binary output terminals 83 through 86.
  • the signal SSp produces a positive spike at the present enable terminal of the main advance counter 81. This results in instantaneously transferring the count at the output terminals 83 through 86 of the auxiliary advance counter 82 into the main advance counter 81 at the times t x .
  • the latch signal at the terminal 88 (S 1 L) is terminated resulting in the up-down control terminal of the advance counter 81 receiving a control input which tells it to count up any subsequently received clock pulses at its clock input terminal.
  • the select decoder 80 now channels the pulses produced at the output terminal 54 of the rate multiplier through the select decoder 80 and its output terminal 87 into the input clock terminal of the advance counter 81. The result of this is that the advance counter 81, after the time t, essentially acts as if it had continuously counted all of the pulses produced at the terminal 54 since the initial time t 1 .
  • the advance counter 81 continues to count up all of the pulses produced at the output terminal 54 of the rate multiplier 53.
  • a maximum count is obtained by the main advance counter 81 which is related to the actual time difference between the periodic occurrence of synchronized advance sensor pulses S 1 at the times t 1 .
  • the maximum count obtained by the counter 81 is related to engine speed and that the ROM 48 and rate multiplier 53 control this relationship in a piecewise linear manner to obtain the correct non-linear relationship between the maximum count in the advance counter 81 and engine speed, as well as the relationship between the maximum count and the sensed engine vacuum pressure.
  • the select decoder 80 At the time occurrences t,D, which occur just after each of the synchronized advance pulses S 1' the select decoder 80 produces a latched signal S,L at the terminal 88 which now instructs the advance counter 81 to count down instead of up. Simultaneously, the select decoder 80 now channels the fixed frequency clock pulses C 3 to its output terminal 87. The end result is that the main advance counter 81 will now count down at a fixed rate determined by the occurrence of the pulses C 3 until a zero count is obtained and a zero detect signal is produced at the terminal 94.
  • this zero detect signal will be received by the spark logic circuit 90 and result in producing the spark occurrence signal SSp which will terminate further down counting, load the count of the auxiliary advance counter 82 into the main counter 81 and initiate the main counter 81 up counting the pulses produced at the terminal 54.
  • Figure 91 represents the accumulated count in the auxiliary advance counter 82. This count is essentially the non-linear pulse occurrences which occur at the output terminal 54 of the rate multiplier 53. At the times t x at which the pulses SSp occur, the count of this counter is directly transferred to the advance counter 81 by means of preset enable circuitry. Preset enable circuitry for counters is very well known and merely results in loading a counter with a preset count in response to an actuation pulse being received at a preset enable terminal.
  • Figure 9J illustrates the count in the main advance counter 81. This figure illustrates that at the times t 1 a maximum count is obtained by the advance counter 81. Then at times t 1 D the counter 81 will count down at the fixed rate determined by the rate occurrence of the signal C 3 , whereas the up counting of this counter was determined by the ROM 48 and rate multiplier 53 implementing a steepwise rate of increase of pulse counts.
  • U.S.-A-4,104,997 clearly illustrates how such a stepwise increasing rate combined with a linear decreasing rate will result in accurately determining the spark time occurrence for internal combustion engines so that a proper advance versus engine speed relationship is developed. Since the equations demonstrating this relationship are contained in the referred to issued U.S. patent, they will not be repeated here.
  • the decoder 80 and counters 81 and 82 effectively form an accumulating means for the pulses produced at the output terminal 54 of the rate multiplier 53. At the times t 1 D, this accumulated count is then linearly decreased at a fixed rate determined by the time occurrence of the pulses C 3 until a zero detect signal is produced at the terminal 94. This zero detect signal represents the desired spark timing occurrence, and the spark logic circuit 90 utilizes this signal to produce the signal SSp at the terminal 89 as well as produce a composite signal (dwell/spark) at an output terminal 100 which contains both dwell and spark timing information.
  • This composite signal at the terminal 100 is then coupled to an input terminal 101 of an output pre-driver 99 which supplies an output at a terminal 102 to a final driver stage 103, in an ignition coil power stage 98 (shown dashed), that controls the excitation of the primary winding 104 of an ignition coil.
  • a high voltage secondary winding 105 of the ignition coil is coupled to the spark gaps of a two cylinder engine to produce ignition pulses therein.
  • a primary ignition coil current sensing resistor 106 is contemplated as sensing the current through the primary coil 104 and providing a feedback signal at a terminal 107 which is coupled as an input to the output pre-driver. This is utilized to maintain constant primary ignition coil current excitation in a well known manner.
  • the output pre-driver 99 also receives an input at the terminal 109 related to actual battery voltage magnitude and another input at a terminal 110 related to whether or not an engine stall condition has occurred. If engine stall, abrupt slow crankshaft rotation, has been detected, then the current through the primary coil 104 will be slowly decreased so as to remove energization from this coil without generating a spark until the engine stall condition has been rectified.
  • the battery voltage magnitude signal at the terminal 109 is utilized to alter the ignition coil current driving signal to obtain constant energy spark ignition despite variations in battery voltage.
  • the output pre-driver 99 and the ignition coil power stage 98 are contemplated as comprising standard electronic ignition system components and therefore the details of these components will not be discussed since they do not form part of the present invention.
  • the spark logic circuit 90 which creates the dwell/spark control signal at terminal 100 receives the master clock pulses Cp from a direct connection to the terminal 26.
  • the circuit 90 also is directly connected to the terminals 34 and 38 for receiving the signals S 1 and S 2 , respectively.
  • the spark logic circuit 90 receives the POR signal at a reset terminal for initiating the logic components contained in the circuit 90 in response to the initial application of power to the electronic ignition control system 10.
  • the circuit 90 also receives the zero detect signal produced at the terminal 94 of the main advance counter 81.
  • the spark logic 90 also receives a dwell initiation signal by means of a direct connection to an output terminal 120 of a dwell circuit 121, and the circuit 90 also receives a slow speed detect signal from an output terminal 122 of a slow speed decoder 123. In response to all of these inputs the spark logic circuit 90 produces the signal SSp at the terminal 89 wherein the SSp signal is a pulse at t x which exists for one clock pulse period of the pulses Cp. The circuit 90 will also create a combined dwell initiate and spark timing occurrence output signal at the output terminal 100.
  • the logic circuit 90 will receive dwell initiate signals from the terminal 120 and spark timing occurrence signals from the terminal 94 for each cycle of cylinder compression. If for some reason a dwell initiating signal has not been received by the spark logic circuit 90 prior to the occurrence of the pulse S 1 which is generated at the maximum possible advance point of crankshaft rotation, then the spark logic circuit 90 will initiate dwell at the times t 1 corresponding to the occurrence of the pulses S i . Similarly, if for some reason a spark ignition has not occurred by the times t 2 at which the pulses S 2 occur, then the spark logic 90 will create a spark occurrence at these times.
  • the signal at the terminal 122 insures that dwell will be initiated at the times t 1 and that spark will occur at the times t 2 . This provide a dwell equal to 35 degrees of crankshaft rotation for slow speed conditions and provides for spark ignition at essentially top dead center of the cylinder compression cycle.
  • the signal at the terminal 122 allows dwell to be initiated by the signal at the terminal 120 and spark to be determined by the zero detect provided at the terminal 94.
  • the signal produced at the terminal 100 is initiated in response to when dwell is desired to commence (t Dw ) and is terminated in response to when the spark logic 90 determines spark ignition should occur (t x ).
  • FIG. 6 A typical embodiment for the spark logic circuit 90 is illustrated in Figure 6.
  • the power on reset connection has not been shown in Figure 6 in order to simplify the diagram. All of the components in Figure 6 correspond to standard logic gate components and flip-flop devices.
  • the engine stall indicating signal produced at the terminal 110 is the output of an engine stall counter 125 which receives a reset input signal by a direct connection to the terminal 34.
  • the counter 125 receives a counting clock input signal by means of an input direct connection to the terminal 47 of the main up counter 41. In this manner, if the stall counter 125 determines that between consecutive times t 1 at which the synchronized advance pulses S 1 occur, the main up counter 41 has registered a predetermined number of changes in the most significant bit of the counter which is connected to the terminal 47, then the counter 125 will indicate that the count being registered by the main up counter 41 is too high.
  • stall counter 125 merely consists of a resettable pulse counter which develops an output whenever the pulse count is above a predetermined threshold. Readily available logic circuits can implement such a function.
  • the slow speed decoder 123 essentially works on a similar principle to the stall counter 125.
  • the slow speed decoder 123 determines when the count in the main up counter 41 exceeds a predetermined maximum count. This is accomplished by coupling the terminals 43 through 47 as inmputs to the slow speed decoder 123.
  • the decoder 123 is reset at times t l D via a connection to terminal 40.
  • the decoder also receives the pulses S 1 via a direct connection to the terminal 34 and it receives a power on reset pulse via a direct connection to the terminal 91.
  • the decoder 123 In response to all of these inputs the decoder 123 produces a slow speed detection at the terminal 122 at times t 1 whenever the count of the main counter indicates that the actual time between the S I D pulses exceeds a predetermined maximum time. Whenever this occurs, this indicates that the engine speed is below a predetermined minimum speed, and the signal at the terminal 122 is received by the spark logic circuit 90 and results in initiating dwell at the times t 1 and causing spark ignition to occur at the times t 2 .
  • the engine speed which actuates the stall counter 125 is an engine speed much less than the predetermined engine speed which resulted in actuating the slow speed decoder 123.
  • Figure 5 illustrates a typical embodiment for the slow speed decoder 123 and the components in Figure 5 represent standard logic circuit components used for a typical implementation.
  • Figure 4 illustrates a typical digital circuit implementation for the select decoder 80.
  • controllable gates 126 and 127 are illustrated. These gates operate as selective open or short circuits between their throughput terminals in response to the digital logic signals present at their respective control terminals 128 and 129.
  • Figure 3 illustrates a typical digital circuit implementation for the advance and reference buffers 21 and 22, the pulse synchronizers 33 and 37, the delay circuit 39 and the inhibit circuit 36.
  • the logic circuit implementations shown in Figure 3 comprise standard digital logic circuits.
  • the inhibit circuit 36 besides producing a four millisecond delay pulse at the terminal 35 in response to receiving a spark ignition signal (SSp) and in response to the received C, pulses provided as a timing duration input, also provides a two millisecond delay signal after spark ignition at an output terminal 130.
  • the terminal 130 is coupled to the dwell circuit 121 and the two millisecond signal serves to inhibit the operation of the dwell circuit until at least two milliseconds after the occurrence of spark ignition. This is required in order to prevent 100 percent dwell from occurring at very high engine speeds. If 100 percent dwell were to occur then no spark ignition would be permitted since current excitation for the ignition coil primary winding 104 would always be applied.
  • the inhibit circuit 36 merely utilizes the signal (SSp) at the times t x to initiate two different monostable time periods which are provided at the terminals 35 and 130 to implement different delays for circuitry in the electronic spark ignition control system 10.
  • the detailed configuration of the inhibit circuit 36 will not be specifically recited since the embodiment in Figure 4 is a typical embodiment using standard components and many other embodiments could accomplish this desired function.
  • output count terminals 42 through 47 of the main counter 41 are connected to preset inputs P, through P6 of the dwell down counter 131.
  • a preset enable terminal of the dwell counter 131 is directly coupled to the terminal 34 such that the counter will be preset in response to the pulses S I .
  • a dwell counter overflow terminal is directly connected to a terminal 139 which is coupled to a terminal 140 that is directly connected to the set terminal of a latch 141 having its output connected to the terminal 120 through a controllable gate 144.
  • a reset terminal of the latch 141 is directly connected to the terminal 34 thus providing for resetting the latch 141 in response to the signal S,.
  • the controllable gate 144 has a control terminal 143 which is directly connected to the terminal 130 such that the controllable gate 144will implement a minimum 2 millisecond delay after SSp for initiating a dwell signal at terminal 120.
  • the dwell down counter 131 has a clock input terminal 132 which is coupled through a controllable gate 133 and an OR gate 160 to the terminal 31 at which the pulses C 4 are present.
  • An auxiliary dwell counter 134 has a reset terminal directly connected to the terminal 40 and a clock signal input terminal directly connected to an output terminal 159 of gate 133.
  • the output count of the auxiliary dwell counter 134 is coupled to a maximum count logic circuit 135 which produces an output signal at a terminal 137 whenever the auxiliary dwell counter count equals or exceeds a predetermined count.
  • the terminal 137 is directly connected as a control input terminal to the controllable gate 133, and this terminal is also coupled through an inverter stage to a control input terminal 150 of a controllable gate 151 coupled, together with OR gate 160 between the terminal 132 and the terminal 28 at which the pulses C, are present.
  • the OR gate 160 permits pulses passed by either of the controllable gates 133 or 151 to reach the terminal 132.
  • the dwell circuit 121 illustrated in Figure 7 will now be described with reference to the graph shown in Figure 9Q which essentially illustrates the operation of the dwell circuit 121 by illustrating the count of the dwell down counter 131 as a function of time.
  • the dwell down counter 131 is preset with the maximum count obtained by the main up counter 41.
  • the count of the auxiliary dwell counter 134 is set to zero resulting in the controllable gate 133 passing a predetermined number of the rapidly occurring clock pulses C 4 .
  • the maximum count logic circuit 135 will open the controllable gate 133 and result in closing the controllable gate 151.
  • the dwell down counter 131 has effectively, instantaneously subtracted this predetermined number of counts from the maximum count which was preset into the dwell counter 131. Subsequent to this subtraction, the dwell down counter 131 will continue down counting at a rate determined by the occurrence of the pulses C l . It should be noted that this occurrence rate is the same occurrence rate at which the main counter 41 is being linearly incremented up to its maximum count representative of engine crankshaft speed. At a subsequent time t DW the count in the dwell down counter 131 will reach zero and on the next count an overflow indication will be produced at the terminal 139. This will result in setting the latch 141 and providing a dwell initiation signal at the output terminal 120 assuming at least a two millisecond delay between spark occurrence and dwell initiation.
  • the dwell circuit in Figure 7 avoids the need for a complex count comparator by having the dwell down counter 131 continue to count down at a rate determined by the C, pulses after effectively subtracting a predetermined number of counts occurring at the rapid frequency of the signal C 4 . In this manner, the output of the dwell down counter 131 will reach zero at predetermined times t Dw ahead of the predetermined times t,. This occurs since if no counts were subtracted and engine speed remained the same, then the dwell down count would overflow exactly at times t,. Thus the dwell circuit 121 insures that dwell initiation will occur at a predetermined time prior to the occurrence of the advance pulses S 1 , at the times t,. The circuit 121 in Figure 7 accomplishes this end result without the use of a complex comparator and is therefore believed to be more economical since fewer connecting lines and logic gates are required than hitherto known.
  • the controllable gate 144 is utilized to insurethat the dwell initiation signal at terminal 120 will not start until at least 2 milliseconds after the occurrence of spark ignition. This insures that 100 percent dwell will not be obtained, and that therefore the primary ignition coil winding 104 will not be constantly excited. This insures the occurrence of a spark for each cylinder when it is in its compression cycle, since if the primary winding always received current excitation no spark could be generated.
  • the present invention contemplates utilizing the crankshaft position sensor signal S 1 as the periodic signal having periodicsignal pulse transitions occurring at predetermined variable (speed dependent) rate
  • the present invention also contemplates the use of the spark occurrence signal SSp as the periodic signal having pulse transitions which occur at a variable (speed dependent) rate.
  • the present invention can implement dwell at a predetermined time prior to spark ignition occurrence rather than at a predetermined time prior to the occurrence of a specific engine crankshaft position.
  • minor modifications of the disclosed circuitry are necessary and these modifications are within the capability of those of average skill in the art.
  • the count of the dwell counter 131 is illustrated as a solid line whereas the count of the main up counter 41 is illustrated as a dashed line.
  • Figure 9P illustrates at the times t, a maximum count is preset into the dwell down counter 131 and then a predetermined number of counts is rapidly subtracted (at times t 1 D) from this number. Subsequently the dwell counter 131 maintains this subtracted count as its output.
  • the count in the main counter 41 is set to zero and this counterwill commence up counting in response to the pulses C, resulting in linear incrementing of the count of the counter 41.
  • the count in the main counter 41 will equal the subtracted count being maintained by the dwell counter 131.
  • the comparator 138 will produce a logic signal that will setthe latch 141 and thereby signal the initiation of the dwell by the signal produced at the latch output terminal 120.
  • the latch 141 will be reset upon the occurrence of the pulse signal S,.
  • the preset invention by utilizing substantially all of the time duration between identical polarity pulse transitions of the crankshaft position sensor signal S 1 to determine the maximum running count which is related to engine speed, has provided a maximum running count which is an extremely accurate indication of engine speed. Since this running count is updated for each engine crankshaft rotation of 360 degrees, the engine speed information is similarly updated for each crankshaft revolution thus providing an up-to-date indication of engine speed.
  • the present invention is capable of producing large dwell angles which is something that has not been obtained by similar prior art circuits (U.S.-A-3 908 616) which illustrate utilizing a first portion of the crankshaft revolution cycle to calculate engine speed and a second portion of the same crankshaft revolution cycle to calculate dwell occurrence.
  • U.S.-A-3 908 616 illustrates utilizing a first portion of the crankshaft revolution cycle to calculate engine speed and a second portion of the same crankshaft revolution cycle to calculate dwell occurrence.
  • the prior art circuits limit dwell occurrence to this second portion of the crankshaft revolution cycle.
  • the present invention implements dwell without adjusting count threshold levels of count comparators and without adjusting the various rates of count accumulating. While adjusting the rate of count accumulating was found to be necessary for the spark control circuitry disclosed herein, it is obvious that the rate adjustment circuitry is much more complex and costly than the dwell control circuitry. Thus the present invention is believed to be superior to prior dwell control circuits which require adjusting pulse accumulation rates or pulse count switching threshold levels in order to implement a desired dwell excitation mode over a range of different engine speeds.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Electrical Control Of Ignition Timing (AREA)
  • Combined Controls Of Internal Combustion Engines (AREA)
  • Ignition Installations For Internal Combustion Engines (AREA)
EP80901351A 1979-06-15 1980-06-09 Dwell circuitry for an ingnition control system Expired EP0031834B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US06/049,013 US4329959A (en) 1979-06-15 1979-06-15 Dwell circuitry for an ignition control system
US06/049,014 US4300518A (en) 1979-06-15 1979-06-15 Digital dwell circuit
US49013 1979-06-15
US49014 1997-06-09

Publications (3)

Publication Number Publication Date
EP0031834A1 EP0031834A1 (en) 1981-07-15
EP0031834A4 EP0031834A4 (en) 1981-10-27
EP0031834B1 true EP0031834B1 (en) 1986-09-10

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EP80901351A Expired EP0031834B1 (en) 1979-06-15 1980-06-09 Dwell circuitry for an ingnition control system

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EP (1) EP0031834B1 (es)
KR (2) KR840002246B1 (es)
BR (1) BR8008711A (es)
DE (1) DE3071748D1 (es)
MX (1) MX148469A (es)
WO (1) WO1980002862A1 (es)

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FR2493412A1 (fr) * 1980-11-04 1982-05-07 Renix Electronique Sa Dispositif de commande de bobine d'allumage a regulation de temps de conduction optimal pour moteur a explosion
JPS58501729A (ja) * 1981-10-13 1983-10-13 モトロ−ラ・インコ−ポレ−テッド センサ入力を有する点火アドバンス回路
JPH0223268A (ja) * 1988-07-13 1990-01-25 Toyota Motor Corp 内燃機関用点火時期制御装置

Citations (1)

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Publication number Priority date Publication date Assignee Title
DE2812325A1 (de) * 1977-03-22 1978-09-28 Motorola Inc Elektronisches zuendsteuersystem

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US3532866A (en) * 1966-11-30 1970-10-06 Nasa Ripple add and ripple subtract binary counters
JPS5310216B2 (es) * 1972-12-18 1978-04-12
CH565946A5 (es) * 1973-07-23 1975-08-29 Hartig Gunter
IT1049544B (it) * 1974-07-31 1981-02-10 Ducellier & Cie Dispositivo di anticipo automatico d accensione in funzione della velo cita di rotazione di un motore a combustione interna
JPS51114535A (en) * 1975-03-31 1976-10-08 Nippon Denso Co Ltd Ignition system of internal combustion engine
US4018202A (en) * 1975-11-20 1977-04-19 Motorola, Inc. High energy adaptive ignition via digital control
US4052967A (en) * 1976-06-24 1977-10-11 General Motors Corporation Digital electronic ignition spark timing system
DE2655948C2 (de) * 1976-12-10 1982-09-16 Robert Bosch Gmbh, 7000 Stuttgart Zündanlage für Brennkraftmaschinen
US4081995A (en) * 1977-02-22 1978-04-04 Rockwell International Corporation Apparatus and method for extrapolating the angular position of a rotating body

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DE2812325A1 (de) * 1977-03-22 1978-09-28 Motorola Inc Elektronisches zuendsteuersystem

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WO1980002862A1 (en) 1980-12-24
EP0031834A4 (en) 1981-10-27
EP0031834A1 (en) 1981-07-15
BR8008711A (pt) 1981-04-14
KR840002246B1 (en) 1984-12-07
MX148469A (es) 1983-04-25
KR840002247B1 (en) 1984-12-07
DE3071748D1 (en) 1986-10-16

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