EP0030864A1 - Carrier wave recovery circuit - Google Patents
Carrier wave recovery circuit Download PDFInfo
- Publication number
- EP0030864A1 EP0030864A1 EP19800304533 EP80304533A EP0030864A1 EP 0030864 A1 EP0030864 A1 EP 0030864A1 EP 19800304533 EP19800304533 EP 19800304533 EP 80304533 A EP80304533 A EP 80304533A EP 0030864 A1 EP0030864 A1 EP 0030864A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- carrier wave
- circuit
- bit counter
- frequency
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/06—Demodulator circuits; Receiver circuits
- H04L27/066—Carrier recovery circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/32—Circuits or arrangements for control or supervision between transmitter and receiver or between image input and image output device, e.g. between a still-image camera and its memory or between a still-image camera and a printer device
- H04N1/327—Initiating, continuing or ending a single-mode communication; Handshaking therefor
Definitions
- the present invention relates in general to a carrier wave recovery circuit and, more particularly, to a circuit wherein a carrier wave is reproduced by means of a digital synthesizer for use in the receiving portion of an image information transmitting apparatus such as facsimile.
- the invention as claimed is intended to provide a remedy for the problems set forth above by providing a carrier wave recovery circuit wherein the voltage controlled oscillator (VCO) of the conventional circuit is replaced for the purpose of digitalizing the entire circuit and providing advantageous features.
- the advantageous features include being highly stable and reliable, easy to manufacture and adaptable to being used in image-information transmitting apparatus such as facsimile. Since the circuit of this invention is of a digital nature, and since a discriminating function is assigned to a counter that determines the frequency-dividing ratio, any erroneous operation of the circuit can be avoided even if an instantaneous interruption occurs in the image information transmission line.
- the digital construction of the circuit further affords advantageous features such as reducing the number of adjusting points, enhancing the resistance to noise and power source variation and reducing the variation in value of the various circuit components after a long period of usage. Furthermore, since the inventive circuit is free from frequency-drift, the circuit can be used for carrier waves of different frequencies and therefore economy of the circuit can be achieved.
- a comparator 10 acts as a multiplier for two AC input signals having frequencies f s and f c and respective phases 0 and ⁇ c ,and delivers,through a low-pass filter 12 and an amplifier 14, a voltage V d (on conductor 15), which is proportional to the variation in time of the detected phase difference ⁇ s ⁇ ⁇ c .
- a voltage. controlled oscillator (VCO) 16 is controlled by the voltage Vd on conductor 15 so that the VCO 16 produces an output on conductor 18 of the frequency f , which is ultimately made equal to the frequency f in the stabilized state of the circuit.
- FIG. 2 there is illustrated one embodiment of the present invention wherein a synthesizer is used instead of the phase-locked loop.
- an image information transmitting apparatus such as facsimile
- there is a protocol period or synchronizing period (prior to the actual transmission of image information) during which signals relating only to the carrier component are transmitted.
- reference clock pulses (CLK) arriving in a one-cycle period of the carrier wave are firstly counted during the synchronizing period for initial setting of the circuit, and fine correction of the set value is then carried out utilizing a received line synchronizing signal or a signal component obtained after the initiation of the image information transmission.
- CLK reference clock pulses
- an N-bit counter 18 counts reference clock pulses CLK arriving on conductor 20 from the local facsimile receiver in a period corresponding to 2 L (L is an integer) cycle periods of the carrier wave (first count), and the count of the N-bit counter 18 is held in latches 22 and 24. A complement of the number count held in the latches 22 and 24 is then preset in the N-bit counter 18 via cable 26. Then the clock pulses CLK on conductor 20 are again counted, as described above, by the N-bit counter 18, and when the result now counted is equal to the count of the first counting operation, a zero output signal is delivered from the counter 18 to a discrimination circuit 28.
- the discrimination circuit 28 investigates at a predetermined time whether the zero signal exists or not at its inlet. When a zero signal is not found, the discrimination circuit 28 delivers an instruction to circuitry in the local receiver (not shown) to resume the counting operation once again.
- an auxiliary counter 30 is further provided in the circuit shown in Figure 2 to prohibit the counting operation in the frequency divider 32 a number of times corresponding to the L bits stored in the latch 22, for every 2 (L is an integer) cycle period of the received carrier wave, each time for a one-cycle period of the clock pulse CLK.
- the error in the newly-produced carrier wave on conductor 34 can be corrected or reduced to less than one cycle period of the clock pulse CLK for every 2 L cycle period of the received carrier wave.
- N-bit counter 18 in this embodiment is of a binary type
- the operational principle is the same for a binary counter and a decimal counter, and for the purpose of simplifying the description, the operation is described for the case of a decimal counter.
- the first latch 24 holds a value "1250" obtained by discarding the lower two bits from the count of the N-bit counter 18, which value is accompanied with a quantized error of "0.35" less than one-cycle period of the reference clock pulse CLK, for every one-cycle period of the received carrier wave.
- the frequency- dividing ratio of the frequency divider 32 is set at the value "1250" held in the latch 24, a quantized error less than one cycle periods of the clock pulse CLK will be added in every three cycle period of the carrier wave.
- the quantized error can be reduced to less than one cycle period of the clock pulse for every 60 cycle period of the carrier wave.
- the quantized error can be reduced to a value less than one cycle period of the clock pulse for every 100 cycle period of the carrier wave.
- zero cross points of the received carrier wave included in the image information signal obtained from the transmission line are detected by a zero cross detector 36 or the like, and the deviation of the zero cross points and those of the reproduced carrier wave may be compared and discriminated by an error-detection circuit 38 for correcting the operation of the frequency divider 32 to correct the phase of the recovered carrier.
- the N-bit counter 18 is made of five 4-bit binary counters 40
- the latches 22 and 24 are made of five 4-bit latches 42 each consisting of a D type flip-flop
- the discrimination circuit 28 is made of a JK flip-flop 44 and an AND gate 46.
- E designates an enabling terminal
- C designates a carrying terminal.
- a reset signal is applied to the counters 40 and the JK flip-flop 44 to reset these circuits.
- a gate signal is applied to the counters 40 for enabling the counters to count a reference clock CLK for a period corresponding to 236 cycle periods of the received carrier wave.
- a latch signal is applied from outside to latch the latch circuits 42 so as to hold the counts of the counters 40 in the latches 42.
- the outputs of the latches 42 are the outputs of the counters 40 at the latched time, and the complement of the outputs of the latches is set by an external set signal into the counters 40.
- a gate signal is again applied to the counters 12 for operating the counters 40 to count the clock pulses CLK for a time corresponding to 256 cycle periods of the received carrier wave.
- v hen the first count is equal to the second count of the counter, each of the counters 40 is reset to zero, and a carry signal is delivered from the end terminal of the last stage counter 40 to the J terminal of the JK flip-flop 44.
- a discrimination timing signal is applied to the gate 46 to open the same gate for delivering an output from the Q terminal of the JK flip-flop 44.
- a value corresponding to the required frequency-dividing ratio is set in the frequency divider 32, and a correction value required for reducing the quantized error for the 256 cycle periods of the carrier wave to less than one cycle period of the clock pulse, is set in the auxiliary counter 30.
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Multimedia (AREA)
- Computer Networks & Wireless Communication (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Facsimile Image Signal Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
- The present invention relates in general to a carrier wave recovery circuit and, more particularly, to a circuit wherein a carrier wave is reproduced by means of a digital synthesizer for use in the receiving portion of an image information transmitting apparatus such as facsimile.
- With the increased emphasis on an automated office and the increased use and popularity of electronic apparatus in the office environment, reliable and high-quality information -transmitting apparatus, such as facsimile, is of greater importance. In known information-transmitting apparatus utilizing vestigial sideband (VSB) where a part of the carrier frequencies is suppressed, a signal synchronized in its frequency and phase angle with the carrier wave has been recovered and reproduced in a demodulator utilizing the phase-locked-loop (PLL) technique. In information-transmitting apparatus utilizing the analog PLL technique, various problems are encountered, which include a circuit that is susceptible to noise, a circuit that must be adjusted at too many locations or elements, and a circuit whose circuit constants are susceptible to variations and changes after a long period of usage.
- The invention as claimed is intended to provide a remedy for the problems set forth above by providing a carrier wave recovery circuit wherein the voltage controlled oscillator (VCO) of the conventional circuit is replaced for the purpose of digitalizing the entire circuit and providing advantageous features. The advantageous features include being highly stable and reliable, easy to manufacture and adaptable to being used in image-information transmitting apparatus such as facsimile. Since the circuit of this invention is of a digital nature, and since a discriminating function is assigned to a counter that determines the frequency-dividing ratio, any erroneous operation of the circuit can be avoided even if an instantaneous interruption occurs in the image information transmission line. The digital construction of the circuit further affords advantageous features such as reducing the number of adjusting points, enhancing the resistance to noise and power source variation and reducing the variation in value of the various circuit components after a long period of usage. Furthermore, since the inventive circuit is free from frequency-drift, the circuit can be used for carrier waves of different frequencies and therefore economy of the circuit can be achieved.
- One means for carrying out the invention is described in detail below with reference to the accompanying drawings, which illustrate only one specific embodiment, in which drawings:
- Figure 1 is a simplified functional block diagram of a known phase-locked-loop circuit utilized in a conventional carrier wave recovery circuit;
- Figure 2 is a simplified functional block diagram showing an embodiment of a carrier wave recovery circuit according to the present invention;
- Figures 3A and 3B are simplified explanatory diagrams of the operation of an N-bit counter in the circuit shown in Figure 2; and
- Figure 4 is a simplified schematic showing a practical embodiment of one portion of the inventive circuit shown in Figure 2.
- Referring now to Figure 1, there is illustrated a typical example of a known phase-locked-loop (PLL) circuit. In this circuit, a
comparator 10 acts as a multiplier for two AC input signals having frequencies fs and fc andrespective phases 0 and θc,and delivers,through a low-pass filter 12 and anamplifier 14, a voltage Vd (on conductor 15), which is proportional to the variation in time of the detected phase difference θs~ θc. A voltage. controlled oscillator (VCO) 16 is controlled by the voltage Vd onconductor 15 so that theVCO 16 produces an output onconductor 18 of the frequency f , which is ultimately made equal to the frequency f in the stabilized state of the circuit. In another example of this known circuit, where a phase comparator of the digital type is used, difficulties with the circuitry are still encountered. Since the output frequency of the voltage-controlled oscillator is still controlled by an analog voltage, the output frequency of the VCO is still susceptible to changes caused by noise and power source variations. - With reference to Figure 2, there is illustrated one embodiment of the present invention wherein a synthesizer is used instead of the phase-locked loop. In the operation of an image information transmitting apparatus, such as facsimile, there is a protocol period or synchronizing period (prior to the actual transmission of image information) during which signals relating only to the carrier component are transmitted. According to the present invention, reference clock pulses (CLK) arriving in a one-cycle period of the carrier wave are firstly counted during the synchronizing period for initial setting of the circuit, and fine correction of the set value is then carried out utilizing a received line synchronizing signal or a signal component obtained after the initiation of the image information transmission.
- During the synchronizing period of the protocol time, an N-
bit counter 18 counts reference clock pulses CLK arriving onconductor 20 from the local facsimile receiver in a period corresponding to 2L (L is an integer) cycle periods of the carrier wave (first count), and the count of the N-bit counter 18 is held inlatches latches bit counter 18 viacable 26. Then the clock pulses CLK onconductor 20 are again counted, as described above, by the N-bit counter 18, and when the result now counted is equal to the count of the first counting operation, a zero output signal is delivered from thecounter 18 to adiscrimination circuit 28. Thediscrimination circuit 28 investigates at a predetermined time whether the zero signal exists or not at its inlet. When a zero signal is not found, thediscrimination circuit 28 delivers an instruction to circuitry in the local receiver (not shown) to resume the counting operation once again. - On the other hand, when a zero signal is found in the inlet to the
discrimination circuit 28, M bits, excepting lower L bits within the count of theN bit counter 18,are stored in thelatch 24. Assuming that T represents a one-cycle period of the received carrier wave, and T2 represents a one-cycle period of the clock pulse onconductor 20, and L and M satisfy following relation, - However, such an approximation tends to result in an excessive amount of error due to the accumulation of the quantizing errors. For overcoming the difficulty, an
auxiliary counter 30 is further provided in the circuit shown in Figure 2 to prohibit the counting operation in the frequency divider 32 a number of times corresponding to the L bits stored in thelatch 22, for every 2 (L is an integer) cycle period of the received carrier wave, each time for a one-cycle period of the clock pulse CLK. As a result, the error in the newly-produced carrier wave onconductor 34 can be corrected or reduced to less than one cycle period of the clock pulse CLK for every 2L cycle period of the received carrier wave. - The above-described operation will now be described in more detail. Although the N-
bit counter 18 in this embodiment is of a binary type, the operational principle is the same for a binary counter and a decimal counter, and for the purpose of simplifying the description, the operation is described for the case of a decimal counter. - Now it is assumed that a number equal to 1250.35 of the reference clock pulses CLK is counted for each cycle period of the received carrier wave. In a case of L = 0 and M = 4, as shown in Figure 3A, the N-
bit counter 18 counts "1250", while the N-bit counter 18 counts "125035" in the other case shown in Figure 3B, where L = 2 and M = 4. In the latter case, thefirst latch 24 in the circuit shown in Figure 2 holds "1250" while thesecond latch 22 holds "35". That is, thefirst latch 24 holds a value "1250" obtained by discarding the lower two bits from the count of the N-bit counter 18, which value is accompanied with a quantized error of "0.35" less than one-cycle period of the reference clock pulse CLK, for every one-cycle period of the received carrier wave. - Accordingly, if the frequency- dividing ratio of the
frequency divider 32 is set at the value "1250" held in thelatch 24, a quantized error less than one cycle periods of the clock pulse CLK will be added in every three cycle period of the carrier wave. Thus, by simply delivering an inhibit signal from theauxiliary counter 30 in every three cycle periodsof the carrier wave to thefrequency divider 32, the quantized error can be reduced to less than one cycle period of the clock pulse for every 60 cycle period of the carrier wave. In other words, by inhibiting the operation of thefrequency divider 32 35 times for each 100 cycle period of the carrier wave, the quantized error can be reduced to a value less than one cycle period of the clock pulse for every 100 cycle period of the carrier wave. - For the purpose of enabling the frequency of the recovered and reproduced carrier wave on
conductor 34 to follow the slow variation of the frequency of the carrier wave in the transmitting side during the transmitting time, zero cross points of the received carrier wave included in the image information signal obtained from the transmission line are detected by a zerocross detector 36 or the like, and the deviation of the zero cross points and those of the reproduced carrier wave may be compared and discriminated by an error-detection circuit 38 for correcting the operation of thefrequency divider 32 to correct the phase of the recovered carrier. - More practical examples of the N-
bit counter 18,latches discrimination circuit 28 and their operation will now be described in detail. - In Figure 4, the N-
bit counter 18 is made of five 4-bitbinary counters 40, thelatches bit latches 42 each consisting of a D type flip-flop, and thediscrimination circuit 28 is made of a JK flip-flop 44 and anAND gate 46. In each of thebinary counters 40, E designates an enabling terminal, and C designates a carrying terminal. - At first, a reset signal is applied to the
counters 40 and the JK flip-flop 44 to reset these circuits. Then a gate signal is applied to thecounters 40 for enabling the counters to count a reference clock CLK for a period corresponding to 236 cycle periods of the received carrier wave. - When the gate signal is turned off, a latch signal is applied from outside to latch the
latch circuits 42 so as to hold the counts of thecounters 40 in thelatches 42. The outputs of thelatches 42 are the outputs of thecounters 40 at the latched time, and the complement of the outputs of the latches is set by an external set signal into thecounters 40. - When the setting operation terminates, a gate signal is again applied to the
counters 12 for operating thecounters 40 to count the clock pulses CLK for a time corresponding to 256 cycle periods of the received carrier wave. In the case v hen the first count is equal to the second count of the counter, each of thecounters 40 is reset to zero, and a carry signal is delivered from the end terminal of thelast stage counter 40 to the J terminal of the JK flip-flop 44. - After the termination of the second counting operation, a discrimination timing signal is applied to the
gate 46 to open the same gate for delivering an output from the Q terminal of the JK flip-flop 44. When the output from the terminal Q) indicative of the result of the discrimination is found to be allowable, a value corresponding to the required frequency-dividing ratio is set in thefrequency divider 32, and a correction value required for reducing the quantized error for the 256 cycle periods of the carrier wave to less than one cycle period of the clock pulse, is set in theauxiliary counter 30.
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54163594A JPS596101B2 (en) | 1979-12-18 | 1979-12-18 | Carrier wave regeneration circuit |
JP163594/79 | 1979-12-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0030864A1 true EP0030864A1 (en) | 1981-06-24 |
EP0030864B1 EP0030864B1 (en) | 1983-08-17 |
Family
ID=15776879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19800304533 Expired EP0030864B1 (en) | 1979-12-18 | 1980-12-16 | Carrier wave recovery circuit |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0030864B1 (en) |
JP (1) | JPS596101B2 (en) |
DE (1) | DE3064606D1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2136247A (en) * | 1983-02-04 | 1984-09-12 | Sony Corp | Digital pal colour television signal demodulators |
GB2201868A (en) * | 1987-03-04 | 1988-09-07 | Nat Semiconductor Corp | Second-order carrier/symbol synchronizer |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3614639A (en) * | 1969-07-30 | 1971-10-19 | Ibm | Fsk digital demodulator with majority decision filtering |
GB1364064A (en) * | 1970-09-24 | 1974-08-21 | Siemens Ag | Demodulating circuits for differential phase-modulated data signals |
GB1506517A (en) * | 1974-09-16 | 1978-04-05 | Philips Ltd | Vestigial-sideband transmission system for synchronous data signals |
GB2017436A (en) * | 1978-03-10 | 1979-10-03 | Cit Alcatel | A circuit for recovering the carrier of an amplitude modulated synchronous digital signal |
-
1979
- 1979-12-18 JP JP54163594A patent/JPS596101B2/en not_active Expired
-
1980
- 1980-12-16 EP EP19800304533 patent/EP0030864B1/en not_active Expired
- 1980-12-16 DE DE8080304533T patent/DE3064606D1/en not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3614639A (en) * | 1969-07-30 | 1971-10-19 | Ibm | Fsk digital demodulator with majority decision filtering |
GB1364064A (en) * | 1970-09-24 | 1974-08-21 | Siemens Ag | Demodulating circuits for differential phase-modulated data signals |
GB1506517A (en) * | 1974-09-16 | 1978-04-05 | Philips Ltd | Vestigial-sideband transmission system for synchronous data signals |
GB2017436A (en) * | 1978-03-10 | 1979-10-03 | Cit Alcatel | A circuit for recovering the carrier of an amplitude modulated synchronous digital signal |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2136247A (en) * | 1983-02-04 | 1984-09-12 | Sony Corp | Digital pal colour television signal demodulators |
GB2201868A (en) * | 1987-03-04 | 1988-09-07 | Nat Semiconductor Corp | Second-order carrier/symbol synchronizer |
GB2201868B (en) * | 1987-03-04 | 1991-08-14 | Nat Semiconductor Corp | Second-order carrier/symbol synchronizer |
Also Published As
Publication number | Publication date |
---|---|
JPS596101B2 (en) | 1984-02-09 |
JPS5686557A (en) | 1981-07-14 |
DE3064606D1 (en) | 1983-09-22 |
EP0030864B1 (en) | 1983-08-17 |
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