Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/66—Digital/analogue converters
  • H03M1/74—Simultaneous conversion
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
  • H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
  • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter

Definitions

• This invention relates to electronic devices for converting digital data to an analog output and more particularly to such a device that may be implemented as monolithically fabricated MOS-type integrated circuit device.
• Digital-to-analog and analog-to-digital converters are required for many types of electronic apparatus, in fact, wherever it is necessary to interface analog data with digital operation and vice versa.
• analog voice signal In the transmission of voice information by telephone, it is desirable to convert the analog voice signal to a digital format in order to substantially reduce the effects of noise and signal distortion normally introduced.
• a digital signal consisting of zero and one levels is easier to reconstruct or amplify faithfully than an analog signal comprised of a large number of levels.
• PCM pulse code modulated
• an encoderdecoder (codec) is used.
• analog voice input is coverted into digital data for transmission over a telephone line, and in the decoder section a digitalto-analog conversion must be provided to restore the sound of the voice after transmission.
• the present invention provides a digital analog converter utilizing only MOSFET elements in an integrated circuit device which does not rely on capacitor ladders or arrays and thus avoids the aforesaid problems and disadvantages .
• a digital-to-analog converter which utilizes controlled MOS current mirrors.
• MOS current mirrors In such a mirror the ratio of the saturated drain current of two connected MOS transistors is proportional to the widths of their channels assuming their surface mobilities, oxide thicknesses, channel lengths, device thresholds and gate voltages are identical in value.
• the output current is produced by the mirroring MOS transistor.
• a transmission gate in combination with another switching device provides on-off control of the mirrored current output.
• the mirroring MOS transistors controlled by the transmission gates with their control devices are connected in parallel.
• Each transmission gate is connected to a source of digital data such as a microprocessor and the mirroring device for each transmission gate has a channel width with some predetermined proportional relationship to the channel widths of the input and mirroring output transistor.
• the input transistor connected to a constant current source I 1
• the total output mirroring current I 2 of the output mirroring transistors in analog form varies according to the mirrored current contributions from the mirroring MOS transistors in a quantising process as they are activated.
• the aforesaid principles of the invention may be applied to implement linear, multiplying and companding converters fabricated as either P-channel, N-channel or complementary MOS structures.
• the objects of the present invention are: to provide a digital-to-analog converter utilizing MOS devices and therefore capable of being fabricated using conventional or known MOS process techniques; to provide a digital-to-analog converter in a monolithic integrated circuit form with a minimum of chip area; and to provide a D/A converter that can be implemented in various forms to accommodate different electronic apparatus.
• Fig. 1 is a circuit diagram of an N-channel MOS current mirror
• Fig. 1A is a circuit diagram of a P-channel MOS current mirror
• Fig. 2-1 is a circuit diagram of a controlled N-channe MOS current mirror
• Fig. 2-2 is the circuit of Fig. 2-1 using a logic symbol for the control gate elements with current mirror;
• Fig. 2A-1 is a circuit diagram of controlled P-channel MOS current mirror
• Fig. 2A-2 is the circuit of Fig. 2A-1 using a logic symbol for the control elements with current mirror;
• Fig. 3 is a circuit diagram of a six-bit N-channel linear current mirror digital-to-analog converter embodying principles of the present invention
• Fig. 4 is a circuit diagram of a six-bit CMOS linear current mirror digital-to-analog converter according to the invention.
• Fig. 5 is a graphical representation of the " ⁇ 255 law" for a digital encoder
• Fig. 6 is a circuit diagram for a companding non linear current mirror digital-to-analog converter embodying principles of the present invention
• Fig. 6A is a circuit diagram of a P-channel current mirror control gate element used in the converter of Fig. 6;
• Fig. 6B is a circuit diagram of an N-channel current mirror control gate element used for implementing step portions of the " ⁇ 255 law" in the converter of Fig. 6;
• Fig. 6C is a circuit diagram of a mirror control gate element for implementing segment portions of the " ⁇ 255 law" in the converter of Fig. 6;
• Fig. 7 is a block diagram showing an arrangement for multiplying signals using current mirror digital-to-analog converters according to the present invention.
• Fig. 8 is a block diagram showing a current mirror digital-to-analog converter in a successive approximation circuit to implement an analog-to-digital converter.
• Figs. 1 and 1A show diagrammatically a basic form of current mirror 10 using MOSFET elements.
• a pair of MOSFET's 12 and 14 are provided whose gates are connected by a common lead 16 and whose source contacts are connected to a common ground 18.
• the drain connected lead 20 of one element is connected by a lead 22 to the common gate lead 16 so that the voltage applied to the gates of both MOSFET's is equal.
• the ratio of the saturated drain currents of the two elements in the mirror may be expressed as follows:
• W 2 and W 1 are the channel widths of the MOSFET's 12 and 14.
• Equation 1 the mirroring current I 2 in the drain connected lead 24 for MOSFET 14 is a function of both input current I 1 and the device channel widths.
• Equation 1 some of the parameters of Equation 1 will vary to some degree depending on variations in processing and layout procedures and electrical parameters. However, such variations can be kept to a minimum by design and production controls, so essentially the relationship of Equation 2 is valid without introducing compensating factors.
• V DD common positive power supply
• the current mirror as shown in Figs. 1 and 1A is not easily controlled, so to solve this problem, as shown in Fig. 2-1, the common lead 16 between the two current elements 12 and 14 is broken and a transmission gate 26 comprising an additional pair of MOSFET elements 28 and 30 is inserted.
• One MOSFET element 28 has its gate connected to a control voltage C, its drain connected to the I 1 side of the lead 16 and its source to the I 2 side of lead 16.
• the other gate element 30 has a gate connected to an inverted control voltage C which is supplied by applying the control voltage C through an inverter 32.
• the source of MOSFET element 30 is connected to the I 1 current lead 18 and its drain is connected to the I 2 current lead 24.
• another MOSFET device 34 is provided having its drain connected to the common lead 16, its source connected to ground and its gate connected to the inverted control voltage (in the N-channel MOS version of Fig. 2-1).
• the element 34 is essentially a pull-down transistor, which when activated pulls down the gate of the mirroring element 14 and therefore turns it off. In some instances, device 30 need not be used.
• Fig. 2-2 is a representation of the circuit of Fig. 2-1 using a logic and gate 36 to symbolize the transmission gate 26 and pulldown transistor 34, and hereafter called a control gate.
• Fig. 2A-1 is shown a P-channel MOS implementation of the basic mirror circuit with the same control elements as in the N-channel MOS version of Fig. 2-1.
• the control input C is applied to the gate of the other pullup transistor 34a.
• the sources of MOS devices 12a and 14a are connected to a positive power source (V DD ) while the drain of the transistor 12a is connected to a current source I 1 and the drain of transistor 14a provides the current weighted output of the circuit.
• V DD positive power source
• I 1 current source
• the diagram using a logic symbol for the transmission gate and its control device and designated by the numeral 36a is shown in Fig. 2A-2.
• Fig. 3 shows a six-bit N-channel linear current mirror digital-to-analog converter 40 comprising a series of parallel connected mirror cells 42 each of which is similar to the mirror cell of Fig. 2-2.
• Each cell is comprised of a control gate 36 and a mirroring transistor 44.
• the channel width of each mirroring transistor in this converter is carefully proportioned and in normal application is one-half the channel width of the mirroring transistor for the next adjacent cell toward the input transistor 12.
• the converter 40 comprises an input lead 20 connected to a power source producing a constant current I 1 and to the drain of the first or input transistor 12 whose source terminal is connected to a common ground lead 18.
• the input lead 20 is also connected to a common branch lead 46 to which each of the other control gates 36 are connected by a lead 48.
• Each of these transmission gates has another input lead 50 which is connected to a control voltage source, e.g., C 0 , C 1 , C 2 , C 3 , C 4 and C 5 .
• the output of each control gate 36 is connected to the gate electrode of the mirroring transistor 44 whose source is connected to the ground line 18 and whose drain terminals are connected to a common line 52 attached to the drain connected output line 24 for the first mirroring transistor 14.
• the first mirroring transistor 14 has unit width 1W
• the adjacent cell has twice the channel width of unit 2.
• the next mirroring transistor has a channel width of unit 4.
• the next mirroring transistor has a channel width of unit 8, the next, a width of unit 16, and the next transistor in order has a channel width of 32, with the input transistor 12 connected directly to the I-. power source having a chnnel width of unit 64.
• the output current I 2 may be represented mathematically as follows:
• the lead 20 is connected to the reference power source that produces a constant current I 1 , and the I 2 output lead 24 is connected to whatever device is adapted to receive the developed analog signal output.
• the control or data inputs C 0 to C 5 are connected to a six bit data input for the digital source that is to be converted. When all data inputs are zero, no current will flow in the output lead 24 because all of the transmission gates 36 are off and their respective pulldown transistors are on, thereby keeping each mirroring transistor 44 off.
• I 2 will equal 1/64th of the current of I 1 because the ratio of the channel widths of these two devices is 1 to 64 and the device receiving the input C 0 will mirror the I 1 current of the input device in proportion to the input and mirroring device channel widths. Now, if input C 0 is turned off (becomes zero) and C 1 is turned on, the device will again mirror the I 1 current, but this time in the ratio of 2 to 64. This binary relationship also applies if different input combinations of C 0 to C 5 are selected, and the output current I 2 will vary accordingly.
• the data inputs C 0 to C 5 may be connected to a microprocessor or the like that supplies digital data in bit groups or in a clocked data stream.
• a microprocessor or the like that supplies digital data in bit groups or in a clocked data stream.
• any number of bit inputs other than six can be applied up to practical limits, and of course the resolution of the analog output increases with the number of control inputs provided.
• a D/A converter as just described, could be fabricated in either the N-channel, using either conventional planar or V-MOS design rules and processing techniques.
• a modified form of the invention is exemplified by a six-bit complementary MOS (CMOS) linear current mirror digital-to-analog converter 60.
• CMOS complementary MOS
• the constant current (I 1 ) input is connected by a lead 20 to the drain of a first input transistor 12 whose source is connected to ground in the N-channel section 62 of the converter.
• the gate of the input transistor 12 is connected to the gate of a non-controlled current mirroring transistor 64 of the same size, and the gates of these two transistors are connected to the constant current (I 1 ) source via a lead 66.
• Also connected to transistors 12 and 64 are three control gate elements 66, 68 and 70, all similar to the elements shown in Fig.
• each of the mirroring transistors 44 has a channel width that has some predetermined size ratio with the input transistor 12.
• the first transmission gate having a data input “C 0 " has a control transistor with a channel width of "1W”.”
• the adjacent or second transmission gate, having a digital input of “C 1 " has a control transistor with a channel width of 2W, and the third transmission gate, having a digital input of "C 2 " has a control transistor with a channel width of "4W.
• a mirroring transistor 14a has its source connected to a constant power source (V DD ), its drain being connected to the analog output terminal 80.
• a second transistor 82 whose gate is common also has its source connected to the V DD line, but its channel width is a predetermined size greater (e.g., 8W) than the transistor 14a.
• the gates of transistors 14a and 82 are connected to the drain of transistor 82 and, via a lead 84 to the drains of the three control transistors 44 for the gate elements 66, 68 and 70 in the N-channel section.
• each mirroring transistor 86 for each control gate element has a channel width which is sized in a predetermined proportion to the transistor 96, and the source of each control transistor is connected to a common V DD line 94.
• the channel widths for the mirroring transistors of control gate elements 88, 90 and 92 are 1W, 2W and 4W, as indicated on the drawing.
• To each of the P-channel control gates 88, 90 and 92 are furnished another input which comes from the digital data source.
• gate element 88 receives an input C 3 through lead 99
• gate element 90 receives an input C 4 through lead 100
• gate element 92 receives an input C 5 through lead 101.
• the value of the output current I 4 may be derived as follows : - -
• the converter 60 provides its digitalto-analog function as follows: Assuming that all the digital data bits C 1 to C 5 are at logic zero except C 0 , the circuit on its left end, as shown in Fig. 4, is a strict current mirror without any control and generates a current I 2 from the constant current input I 1 . In the example shown, I 2 should be equal to I 1 because the ratio of the transistor 12 and its mirroring transistor 64 is 8W compared to 8W. The I 2 current is fed into the upper current mirror section 78, but since the bits C 3 , C 4 and C 5 are low or zero, the upper mirroring devices are turned off. Since C 1 and C 2 are also zero, these devices are off and there is a current I 3 which is generated strictly by C 0 .
• the control transistor for the transmission gate 70 has a channel width of IW
• the value of I 1 is 1/8 of I 1 .
• logarithmic analog to digital conversion was required.
• One form of logarithmic curve used is commonly referred to as the " ⁇ 255 law" curve and is based on 8 bits of code (PCM).
• PCM bits of code
• the code is similar to scientific notation in that it consists of a sign bit, four bits for the mantissa, and three bits for the exponent.
• the sign bit determines the quadrant of operation, the three bits the chord within the quadrant, and the four bits the step within the chord.
• Fig. 5 shows an approximate version of the law composed of two quadrants and segments within the quadrants for a digital-to-analog converter used in conjunction with the encoder (transmitter).
• the approximate law used has the same property as the one specified in that the range of each increasing segment is twice the range of the previous segment. The only difference is that the first step in the first segment uses the value 2 rather than the specified value 1.
• the term 128(16) is the end value of the previous segment, and is required since the law is built from the sum of each previous segment encountered.
• the next segment (-6) is encountered and its value consists of the steps weighted in this case by 32, the value of the previous segment 64(16), and the sum of all other previous segments before that.
• the algorithm proceeds through each segment in a similar manner. From the algorithm an equation is developed as shown in the following Table 2.
• Each code number has a unique code signal word consisting of the control signal bits, and these words may be formed arbitrarily from combinations of zeros and ones and designated for the code numbers in the conventional manner.
• Tables 3A and 3B showing typical code signal bits required to operate the A 255 law converter in Fig. 4 and provide the number and values which may be found in Orange Book Volume III-2 of The International Telecommunications Union, Geneva, Switzerland.
• the circuit representing a digital-to-analog converter 104 for implementing the " ⁇ 255" law according to the present invention is shown in Fig. 6.
• the circuit is comprised of controlled and uncontrolled current mirrors including a first (or lower) series of N-channel current mirrors 106 for implementing the step values of the law (having values 1,2,...16 for the negative quadrant, and values 0.1,...,15 for the positive quadrant), and a second (or upper) series of current mirrors 108 for implementing the segment portion of the law (having weighted values 1,2,4, ...128).
• a single current mirror 110 is provided for implementing the sign bit to determine the quadrant of operation.
• a reference current I R is supplied by a lead 112 to the drain and gate of a first input transistor 114 and also to the gate of a mirroring transistor 116 whose drain is connected by a lead 118 to the upper series of current mirrors 108.
• the I R current is also furnished as one input to each of the control gates 106.
• a detailed circuit diagram for these N-channel current mirrors is shown in Fig. 6B.
• the other input leads 120 to these N-channel control gates are connected to separate data inputs S 0 , S 1 , S 2 and S 3 .
• the output of each control gate 106 is connected to the gate of a mirroring MOSFET 122 whose channel has a preselected width (as indicated) so that it will conduct a proportionate amount of current.
• the source electrodes for all five of these mirroring transistors 122 as well as the transistors 114 and 116 are connected to a common lead 124 from a ground of V SS terminal.
• the drain electrodes for the mirroring transistors 122 are connected to a common lead 126 extending to the upper series of current mirrors.
• the current mirrors 108 in the upper bank or series as shown in a detailed circuit diagram of Fig. 6C have two signal input terminals c and d for receiving the coded input data signals (C0 C0', C1 C1', etc.) and two input terminals a and b.
• the "a" terminals for all eight of the current mirrors are connected in parallel to a common lead 128 and the "b" terminals are connected to a common lead 130.
• Each of the current mirrors 108 has an output terminal "e" which is connected to the gate of a mirroring transistor 132 whose source is connected to a common lead 134 from a positive voltage supply V DD .
• each mirroring transistor 132 in the upper series has a channel width that is one-half the size of the next adjacent transistor of the series so as to provide a proportional current output.
• the mirroring transistors for the eight current mirrors 108 have channel widths of 1W to 128W.
• the P-channel control gate 110 (having the circuitry of Fig. 6A) has an output connected to the gate of a mirroring transistor 138 whose channel width is 255W and whose source is connected to the V lead 134. Its drain electrode is connected to the common output lead 136.
• a pair of first and second input transistors 140 and 142 are connected in parallel with the mirroring transistors 132 and both have channel widths of 255W.
• the sources of these transistors are connected to the commonV DD lead 134.
• the drain and gate electrodes of the first transistor 140 are connected to the I 1 lead 128 which in turn is connected to the linear "AND" gate 110 and to the "a" inlet terminal of each of the control gates 108, while the drain and gate electrodes of the second transistor 142 are connected to the "b" inlet terminals on these control gates.
• the linear AND gate 110 receives a sign data input (C+) through a lead 144 which is also connected via a lead 146 through an inverter 148 to a lower current mirror 106a.
• upper current mirrors 108 (having weighted channel values 1,2,4, ... ,128) implement the segment portion of the " ⁇ 255" law
• the lower current mirrors 106 implement the step values of the law (having values 1,2,..., 16 for the negative quadrant, and values 0,1,...15 for the positive quadrant).
• a selected code number e.g., 31
• the step bits S 3 to S 0
• the current I 2 consists of the sum of currents from the associated mirrors controlled by those bit values.
• the value within the parenthesis is the value v n indicated in a predetermined code word table and is normalized according to the value 255 ⁇ 32(8160). To compare to the actual values (v n 's) of the ⁇ 255 law, the value v n is adjusted by the equation 2 (v n -4080). The factor 2 accounts for the simplification made previously and cancels in the normalization procedure.
• the term 4080 is needed to reposition the origin to the center of the ⁇ 255 graph, and in the actual circuit, this is accomplished by defining the voltage drop created by the current (I OUT ) in the center of the graph by ground potential.
• the multiplication of signals is an important signal processing procedure. For example, modulation and conversion of signals from one frequency to another requires such processing.
• multiplication of signals is easily accomplished using four current-mirror digital-to-analog converters 150, 152, 154 and 156 as shown in Figure 7. These two P-channel and two N-channel current mirror digital-to-analog converters are cascaded by connecting the output of one to the input of another.
• the input current I 1 to the converter 150 may be a reference (constant) current or it may be varying.
• the current-mirror D to A's may be linear weighted (i.e., the weights of each increasing bit will double compared to the previous bit) or non-linear weighted with the bit weights selected as desired.
• the current from each D to A converter may be represented by the equation:
• I OUT I IN The output and input current
• w n The control bit weight
• C n The control bit input (having value 0 or 1)
• d i The general control vector consisting of a sum of products of the control weights and bits
• Fig. 7 shows a multiplication of four vectors, the size of the multiplication of the digital variables may be of any value (i.e., from two to a value limited by the performance requirements of the multiplying D to A converter) .
• Current-mirror D to A converters may also be incorporated into an A to D conversion scheme utilizing a conversion technique known as successive approximation.
• a voltage reference 158 provides a constant voltage V R to a voltage to current converter consisting of a suitable operational amplifier 160.
• the output of this op-amp is connected to the gate of an N-channel MOS transistor 162 whose drain is connected to a negative feedback lead 164 that is also connected through a resistor R 1 to ground.
• a current (V R/R1 ) is supplied by a lead 166 to a D to A current mirror 168 which receives data inputs from a successive approximation register 170 (SAR).
• the output of the comparator is connected by a lead 176 to the SAR 170, and the positive input to the op-amp 172 is connected by a lead 178 to the reference voltage 158.
• the algorithm of the conversion process is as follows with some unknown voltage v in applied to the comparator: the unknown voltage has a value between zero and the reference voltage V R .
• bit C 3 (the most significant bit) is set to a value zero, thus and the voltage to the comparator's negative input v equals ( R ⁇ 7 R since the input value and the value v is (i.e., below v in ), the comparator provides a digital value zero to the SAR.
• the SAR will store that value on the signal line C 3 for the remaining cycles.
• bit C 2 is set to value one, thus v equals and with v equaling (i.e., above v in ), the value provided by the compa rator is one and is stored on bit C 2 .
• bit C is set to value one, thus v equals With v in
• bit C 0 is set to value one, thus v equals ) or With v. equaling v, the value provided by the comparator is zero and is stored on bit C 0 .

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• 1980
  • 1980-06-20 JP JP50165380A patent/JPS56501184A/ja active Pending
  • 1980-06-20 WO PCT/US1980/000814 patent/WO1981000033A1/en not_active Ceased
  • 1980-06-20 GB GB8029139A patent/GB2078454A/en not_active Withdrawn
  • 1980-06-23 NL NL8003634A patent/NL8003634A/nl not_active Application Discontinuation
  • 1980-06-23 FR FR8013936A patent/FR2510328A1/fr not_active Withdrawn
• 1981
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