EP0016692B1 - Frequenzvergleichsschaltung und eine solche Schaltung enthaltende Selektivrufvorrichtung - Google Patents

Frequenzvergleichsschaltung und eine solche Schaltung enthaltende Selektivrufvorrichtung Download PDF

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Publication number
EP0016692B1
EP0016692B1 EP80400336A EP80400336A EP0016692B1 EP 0016692 B1 EP0016692 B1 EP 0016692B1 EP 80400336 A EP80400336 A EP 80400336A EP 80400336 A EP80400336 A EP 80400336A EP 0016692 B1 EP0016692 B1 EP 0016692B1
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Prior art keywords
signal
circuit
frequency
frequency comparator
duration
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Expired
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EP80400336A
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English (en)
French (fr)
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EP0016692A1 (de
Inventor
Henri Butin
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Thales SA
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Thomson CSF SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H04W88/022—Selective call receivers
    • H04W88/025—Selective call decoders
    • H04W88/027—Selective call decoders using frequency address codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/30—Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44—Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/446—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using one signalling frequency
    • H04Q1/448—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using one signalling frequency with conversion of a single frequency signal into a digital signal

Definitions

  • the present invention relates to a frequency comparator circuit of the type of frequency comparator circuits which include means for comparing the signs A, F, Fq of the respective instantaneous amplitudes of a received signal, of a reference signal of period T and of the reference signal phase shifted by counting means providing a first signal proportional to the difference between the sums of the time intervals where A is different from F and F and where A is identical to F and Fq and a second signal proportional to the difference between the sums of the intervals of time where A is different from F and identical to F and where A is identical to F and different from Fq.
  • the present invention is intended, in particular, for selective calling devices used in radiotelephony or used for selective calling of people.
  • the call numbers are transmitted in the form of successive tones, each tone representing for example a digit. If an extension with a three-digit call number, for example 3-9-2, receives a sequence of tones, this extension, to find out if the selective call is intended for it, will search for the tone corresponding to the number 3 then, if it finds it, the tone corresponding to the number 9, then, if the tone corresponding to the number 9 immediately follows the tone corresponding to the number 3, it will search for the tone corresponding to the number 2.
  • the station must therefore be able to recognize a predetermined tone, called expected tone.
  • Such frequency comparator circuits work well but do not make it possible to carry out, with the counting means, countings which, at a given moment, relate to the duration of the expected tone; it would indeed be necessary for that that the command impulse is sent at the time of the changes of tones, or this is generally not possible, especially during the search for the first tone of a series of successive tones expected and does not may be due to chance.
  • These frequency comparator circuits therefore do not make it possible to take full advantage of the fact that, generally, the duration of the tones received is known; they are therefore more sensitive to noise than if counting by the counting means could be systematically carried out over the duration of the tone.
  • the object of the present invention is to reduce this sensitivity to noise.
  • a frequency comparator circuit of the type indicated at the start of this description is characterized in that it comprises a delay circuit whose duration of the delay is KT (K positive integer), receiving a signal representative of A, and a blocking circuit blocking the operation of the counting means when the signs of the amplitudes of the input and output signals of the delay circuit are identical.
  • the two counters have their count which varies more in one direction (counting or counting down) than in the other; the passage of a counter by a predetermined value is significant because the frequency of A is equal to f or very close to f. It should also be noted that, insofar as the signal A is at the frequency F, one of the two down-counters has its account which increases (or decreases), for a period of a value equal to a permanent count for the duration and this whatever the phase difference between signal A and signal F.
  • the two up-down counters count up and down during periods of time which, on average, balance each other, so that then their count n 'not reached the predetermined value.
  • the up-down counters are reset to zero (or to a given value) by regularly spaced signals which do not necessarily coincide with the transitions between successive tones. At the start of such a transition the content of the counters is therefore not strictly zero (or equal to the given value), which is a cause of performance degradation because the predetermined value must be chosen lower than that which, without this would be strictly necessary.
  • the circuit according to the figure is a circuit in which the up-down counters have, at a given moment, their count which corresponds to a count-up or down counting carried out over the entire duration of a tone or at least over a whole number of spheres as close as possible to the duration of the expected tone.
  • the figure shows a signal A which is a signal received by a receiver and which has been clipped for use as a two-level logic signal "0" and "1".
  • This signal is applied to the first input of a logic circuit 1 which receives, from a signal generator 2, signals F and F respectively on its second and third inputs.
  • the signals F and Fq are square signals of frequency f and are offset by a quarter of a period with respect to each other.
  • Logic circuit 1 which includes inverters, AND gates and OR gates, processes the signals these signals are respectively applied to the first inputs of four AND gates, 3, 4, 5, 6. These AND gates receive on their second input pulses p at a frequency much greater than f, which are supplied by a pulse generator 7.
  • the outputs of AND gates 3 and 4 are respectively connected to the counting input (+) and the countdown input (-) of a first comp countdown 8; the outputs of AND gates 5 and 6 are respectively connected to the counting input (+) and to the down counting input (-) of a second up-down counter 9.
  • the up-down counters 8 and 9 have a reset input at a given value (the value corresponding in this example to their half-capacity: M) on which a signal is applied which will be defined later (signal R ').
  • the multiple outputs of the up-down counters 8 and 9 are connected to the inputs of a decoding circuit 10 which provides an output signal when one of the two down-counters goes through a predetermined value.
  • the part of the diagram which has just been described and which comprises the elements marked from 1 to 10 corresponds to the diagram of a frequency comparator circuit according to the known art.
  • the signal R ', applied to the up-down counters 8 and 9 is generally a signal composed of regularly spaced pulses.
  • the frequency comparator circuit comprises, in addition to elements 1 to 10, a binary delay line, 11, and an "exclusive OR" gate 13.
  • the delay line 11, is, in the example described, a shift register (Anglo-Saxon literature).
  • the signal A is applied to the signal input of the delay line 11 which receives respectively on its two clock inputs an input clock signal h 1 and an output clock signal h 2 ; these signals h 1 and h 2 are produced by the signal generator 2.
  • the delay line 11 provides an output signal A r .
  • the "exclusive OR" gate 13 receives the signals A and A r and at its output connected to the third inputs of the AND gates 3, 4, 5, 6.
  • An initialization signal R constituted by a pulse, is produced when the frequency comparator circuit according to the figure is started up; it is applied to a monostable rocker 12 of duration slightly greater than the duration of a tone. During its quasi-stable state, the monostable rocker provides an output signal, R ', which keeps the up-counters 8, 9 at a predetermined initial count M.
  • the delay line 11 operates under the action of the sianals h, and h 2 chosen with a frequency equal to where N is the number of stages of the delay line and K is an integer.
  • N is the number of stages of the delay line and K is an integer.
  • K is an integer.
  • K satisfies the double inequality:
  • the delay brought by the delay line has for value the whole number of periods T included in the duration B of the expected tone.
  • the signals h 1 and h 2 are rectangular signals offset with respect to each other by a half period.
  • the delay line supplies signal A, which is identical to signal A but delayed by the duration KT.
  • the "exclusive OR” gate 13 blocks the AND gates 3, 4, 5, 6 when the signal A r which it receives on one of its inputs is equal to the signal A which it receives on its other input.
  • the "exclusive OR” gate, 13, authorizes the counting (or counting down) of the pulses p only when A, is different from A.
  • the signals F and Fq have the same value as at time t-KT since they are at the frequency Therefore, if A r is different from A (i.e. if A at time t-KT is different from A at time t) and if for example the up-down counter 8 counted at time it breaks down at time t (because then the relation will be checked). Likewise, with A r different from A, the up-down counter 8 will count at time t if it was down at time t-KT and the up-down counter 9 will count or down at time t depending on whether it counted or counted at the instant t-KT.
  • the up-down counters 8 and 9 have at all times t, accounts which are respectively representative of the functions S and D (as defined above) between the times t-KT and t, i.e. accounts representative of the integration between t-KT and t of durations in these equations the sign + has the without of the logical AND function while the sign-has the meaning of the least arithmetic.
  • the count of one of the up-down counters 8, 9 will reach, by counting and / or counting down, one of the two values of which the difference with the value of his initial account M will be equal to to the possible parasitic pulses near (T 'being the number of pulses p supplied by the generator 7 during the time T); this results from what has been said previously, namely that, whatever the phase difference between A and F, one of the two up-down counters has its account which varies from during a period T if A is at the frequency f.
  • the decoding circuit 10 is designed so as to give an output signal when one or the other of the counters 8 and 9 goes through one of the values where E is a low number of pulses in front to take account of any parasitic pulses.
  • the description which has just been given relates to a frequency comparator circuit of a selective call device with 11 different tones, the respective frequencies of which are those defined by the standards C C I R for selective calls. Duration B is 100 mS.
  • the delay line 11 is a 1024 bit shift register, manufactured by the company INTERSIL under the reference IM 7722.
  • the frequency comparator circuit includes a set of control circuits which makes it possible to change the frequencies of the signals supplied by the signal generator 2 and the pulse generator 7 as a function of the tone. expected and its duration when this duration is not the same for all tones.
  • This set of control circuits not being necessary for understanding the invention has not been shown in the figure.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Manipulation Of Pulses (AREA)

Claims (4)

1. Frequenzvergleicherschaltung mit Mitteln (1,3-7) zum Vergleichen der Vorzeichen A, F, Fq der Augenblicks-amplituden eines empfangenen Signals, eines Bezugssignals der Periode T bzw. eines um
Figure imgb0038
phasenverschobenen Bezugssignals, mit Zähleinrichtungen (8, 9), die ein erstes Signal abgeben, das proportional zu der Differenz zwischen den Summen der Zeitintervalle ist, wo A verschieden von F und F ist und wo A identisch mit F und Fq ist, und ein zweites Signal abgeben, das proportional zu der Differenz zwischen den Summen der Zeitintervalle ist, wo A verschieden von F und gleich F ist und wo A gleich F und verschieden von F ist, dadurch gekennzeichnet, daß sie eine Verzögerungsschaltung (11) umfaßt, deren Verzögerungsdauer KT beträgt (K ganzzahlig positiv) und die ein für A representatives Signal empfängt, und eine Blockierschaltung (13) enthält, welche die Funktion der Zähleinrichtungen blockiert, wenn die Vorzeichen der Amplituden des Eingangssignals (A) und des Ausgangssignals (Ar) der Verzögerungsschaltung gleich sind.
2. Frequenzvergleicherschaltung nach Anspruch 1, die dazu bestimmt ist, in dem empfangenen Signal ein Signal der Periode T zu erkennen, dessen Dauer B bekannt ist und größer als T ist, dadurch gekennzeichnet, daß K die folgende doppelte Ungleichung erfüllt:
Figure imgb0039
3. Frequenzvergleicherschaltung nach einem der vorstehenden Ansprüche, dadurch gekennzeichnet, daß die Verzögerungsschaltung (11) eine Verzögerungsleitung vom Typ eines Schieberegisters umfaßt, dessen Anzahl von Stufen N beträgt und dessen Taktsignalfrequenz (h,, h2)
Figure imgb0040
beträgt.
4. Selektive Rufvorrichtung, dadurch gekennzeichnet, daß sie mit wenigstens einer Frequenzvergleicherschaltung nach einem der vorstehenden Ansprüche ausgerüstet ist.
EP80400336A 1979-03-16 1980-03-14 Frequenzvergleichsschaltung und eine solche Schaltung enthaltende Selektivrufvorrichtung Expired EP0016692B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR7906742A FR2451691A1 (fr) 1979-03-16 1979-03-16 Circuit comparateur de frequences et dispositif d'appel selectif comportant un tel circuit
FR7906742 1979-03-16

Publications (2)

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EP0016692A1 EP0016692A1 (de) 1980-10-01
EP0016692B1 true EP0016692B1 (de) 1983-04-13

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US (1) US4322686A (de)
EP (1) EP0016692B1 (de)
DE (1) DE3062680D1 (de)
FR (1) FR2451691A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1259146A (en) * 1986-11-26 1989-09-05 Anthony K.D. Brown Dial tone detector
US4864158A (en) * 1988-01-28 1989-09-05 Amtech Corporation Rapid signal validity checking apparatus
US7873130B2 (en) * 2005-08-10 2011-01-18 Ludwig Lester F Frequency comparator utilizing enveloping-event detection via symbolic dynamics of fixed or modulated waveforms

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818358A (en) * 1972-12-29 1974-06-18 Stromberg Carlson Corp Noise rejection circuit for digital systems
GB1482629A (en) * 1973-09-11 1977-08-10 Trend Communications Ltd Tone detectors
US3942125A (en) * 1975-01-08 1976-03-02 Gte Automatic Electric Laboratories Incorporated Digital repetition rate check circuit
DE2515769A1 (de) * 1975-04-10 1976-10-21 Standard Elektrik Lorenz Ag Frequenzselektiver signalempfaenger
US4128812A (en) * 1977-08-09 1978-12-05 The United States Of America As Represented By The Secretary Of The Army Phase discriminator
US4220924A (en) * 1978-03-16 1980-09-02 Osann Robert Jr Digital phase decoding technique for quadrature phased signals
US4169264A (en) * 1978-07-03 1979-09-25 Sperry Rand Corporation Synchronous digital delay line pulse spacing decoder

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Publication number Publication date
FR2451691B1 (de) 1981-10-30
EP0016692A1 (de) 1980-10-01
FR2451691A1 (fr) 1980-10-10
DE3062680D1 (en) 1983-05-19
US4322686A (en) 1982-03-30

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