EP0016256B1 - Circuit arrangement for correcting the step distortions during the transmission of data with frequency modulation - Google Patents

Description

The invention relates to a circuit arrangement for correcting step distortions in the transmission of data using frequency-modulated data signals, a demodulator being provided which compares the time periods between edges of the frequency-modulated data signals with a measurement period generated by a timing element and demodulated after filtering Generates data signals which have step distortions in the event of frequency deviations of the frequency-modulated data signals.

A demodulator for demodulating frequency-modulated data signals is known from DE-AS 2606515. generates the signals which are proportional to the difference between the time period between two edges or zero crossings of the frequency-modulated data signals and a constant measurement time period. These signals are integrated using a low-pass filter and converted into binary demodulated data signals using a threshold value stage. The binary values of these demodulated data signals are assigned to the characteristic frequencies of the frequency-modulated data signals.

The known circuit arrangement contains a timer for generating the measuring period, which is designed as a counter which is advanced by clock pulses with a constant repetition frequency. In the event of edges or zero crossings of the frequency-modulated data signals, the counter is reset to an initial value. At the same time, a flip-flop is also reset. The counter is then advanced by the clock pulses to a predetermined counter reading, which, together with the starting counter reading and the repetition frequency of the clock pulses, defines the measurement period. When the counter has reached this predetermined counter reading, the flip-flop is set and remains set until it is reset by the next edge or a corresponding zero crossing of the frequency-modulated data signals. If the counter is blocked at the same time as the flip-flop is set, the duration of the signal which sets the flip-flop immediately indicates the difference between the time between the edges or the zero crossings of the frequency-modulated data signals and the measurement time. This signal is filtered using a low pass. The instantaneous values of the signals at the output of the low pass are assigned to the repetition frequencies of the corresponding frequency-modulated data signals at the input of the demodulator. The low-pass filter is followed by a threshold value stage, which generates binary demodulated data signals, the binary values of which are assigned to the characteristic frequencies of the frequency-modulated data signals.

If the frequency-modulated data signals are affected by frequency deviations, the demodulated data signals have distortion which occurs as a result. that a DC voltage corresponding to the frequency deviation is superimposed on the signals at the input of the threshold value stage.

To eliminate these step distortions, it is already known from DE-PS 1 939 067 to compensate for the superimposed DC voltage at the output of the low-pass filter. However, this circuit requires a relatively large outlay, since it uses switching elements of the analog circuit technology. It is also dependent on temperature and voltage fluctuations and also for intermittent: operation not to be used.

The invention is therefore based on the object of specifying a circuit arrangement for correcting the step distortions which is largely independent of ambient conditions and which requires little effort.

According to the invention, the object is achieved in the circuit arrangement of the type mentioned at the outset by a comparator which compares the instantaneous values of the demodulated data signals with the instantaneous values of reference signals, the repetition frequency of which is equal to twice the step frequency of the demodulated data signals, and by an integrating element which integrates the output signal of the comparator and emits control signals to the demodulator, which counteract the step distortions of the demodulated data signals by changing the measurement period.

The circuit arrangement has the advantage that it can be manufactured inexpensively because of its low outlay and can largely be implemented as an integrated semiconductor module. Even with small frequency deviations of the frequency-modulated signals, it works with great accuracy and with great reliability. The number of transmission errors in the event of frequency deviations is significantly reduced by using the circuit arrangement. It is also suitable for use in the intermittent transmission of data.

If the demodulator generates the measuring period in a digital manner and for this purpose a counter is provided as a timer, which is advanced by clock pulses with a constant repetition frequency and whose counting range determines the measuring period, the measuring period is changed in a particularly advantageous manner by the fact that the integrator emitted control signals are fed to the counter and change its counting range.

In the case of a constant greatest counter reading of the first counter stage, it is particularly favorable if the control signals change the starting counter reading of the counter in the timing element.

An advantageous embodiment of the scarf The arrangement is achieved in that the integrating element contains a first counter stage, which is counted up or down depending on the output signal of the comparator for specified periods of time, and contains a second counter stage, which is counted up or down whenever the first counter stage is predetermined Has exceeded or fallen below meter readings and which emits the control signals.

The predefined counter readings are determined in a particularly simple manner if the integrating element contains a decoder which recognizes the predefined counter readings of the first counter stage and outputs corresponding signals to the second counter stage.

The instantaneous values of the demodulated data signals are compared with the instantaneous values of the reference signals in a particularly simple manner if an equivalence element is provided as the comparator.

• Fig. 1 ein Blockschaltbild der Schaltungsanordnung,
• Fig. 2 Signale an verschiedenen Punkten eines Demodulators,
• Fig. 3 unverzerrte und mit Schrittverzerrungen versehene demodulierte Datensignale,
• Fig.4 4 weitere Signale an verschiedenen Punkten der Schaltungsanordnung.

An exemplary embodiment of the circuit arrangement is explained in more detail below with reference to drawings. It shows

• 1 is a block diagram of the circuit arrangement,
• 2 signals at different points of a demodulator,
• 3 undistorted and demodulated data signals provided with step distortions,
• Fig.4 4 further signals at different points in the circuit arrangement.

The circuit arrangement shown in FIG. 1 for correcting step distortions contains a demodulator DM, a comparator VG, an integrator JG and a clock generator TG. Frequency-modulated data signals D1 are fed to the demodulator DM. When binary coded data is transmitted, a characteristic frequency is assigned to each binary value of the transmitted data. When the binary value to be transmitted changes, the repetition frequency of the data signals D1 changes continuously between these two characteristic frequencies.

The demodulator DM is designed, for example, similar to a demodulator described in DE-AS 2606515. The operation of the demodulator DM is described below together with the time diagrams shown in FIGS. 2 and 3. In the time diagrams shown in FIG. 2, the time t is shown in the abscissa direction and the instantaneous values of signals at different points of the demodulator DM in the ordinate direction.

Between times t1 and t4 it is assumed that the repetition frequency of the data signals D1 is equal to the upper characteristic frequency which is assigned to a binary value 0, whereas between times t5 and t8 it is assumed that the repetition frequency of the data signals D1 is equal to the binary value 1 assigned lower characteristic frequency. The data signals D1 are supplied to a differentiator DIF, which at each edge or any corresponding 1 _\ "of the data signals ulldurchgang D1 generates a pulse S1. The pulses S1 on the one hand trigger a measurement period in a timer Z and on the other hand reset a flip-flop F. For example, at time t1, when the data signal D1 changes its binary value from 0 to 1, a pulse S1 is generated which triggers the measurement period and resets the flip-flop F. When the flip-flop F is reset, the signal S3 assumes the binary value 0 at its output. At the time t2, the measurement period has expired and the timer Z outputs a signal S2 which sets the flip-flop F. The signal S3 thus assumes the binary value 1. At time t3, the data signal D1 changes its binary value from 1 to 0 and a pulse S1 is generated again, which resets the flip-flop F, so that the signal S3 again assumes the binary value 0.

The timing element Z is designed, for example, as a monostable multivibrator or as a counter. which is reset to an initial value with each pulse S1, is advanced by clock pulses T1 generated in a clock generator TG and generates the signal S2 when a predetermined counter reading is reached. This signal S2 is, for example, a carry signal issued by commercially available counters. The initial counter reading, the final counter reading and the repetition frequency of the clock pulses T1 determine the measuring time period and it is determined so that it is less than the time period between the edges of the data signals D1 or less than the period of the data signals D1. The pulse duration of the signals S3 is in any case proportional to the difference between the time period between the edges of the data signals D1 and the measurement time period. Between the times t5 and t7, corresponding processes are repeated as between the times t1 and t3. Since the repetition frequency of the data signals D1 is lower and the same measurement period occurs between times t5 and t6 as between times t1 and t2, the pulse duration of signals S3 between times t6 and t7 is greater than between times t2 and t3. The pulse durations of the signals S3 are therefore a measure of the repetition frequency of the data signals D1.

The signals S3 are fed to a low-pass filter TP, which emits signals S4 at its output which correspond to the integrated signals S3. The signals S4 are fed to a sampling stage AS, which outputs binary demodulated data signals D1 at its output as a function of the signals S4. If, as between the times t1 and t4, the repetition frequency of the data signals D1 is equal to the upper characteristic frequency and thus the signals S3 have a narrow pulse duration, the instantaneous value of the signals S4 is below a predetermined, dash-dotted threshold and the sampling stage AS then outputs a data signal D2 with the binary value 0. If, as between times t5 and t8, the repetition frequency of the data signals Dl is the same lower characteristic frequency and the pulse duration of the signals S3 is greater, the instantaneous value of the signals S4 is above the threshold value and the sampling stage AS then outputs a data signal D2 with the binary value 1.

In the time diagrams shown in FIG. 3, the time t is shown in the abscissa direction and the signals S4 and the data signals D2 are shown in the ordinate direction in the event that the frequency-modulated data signals D1 have no and a predetermined frequency deviation

If the data signals D1 have no frequency deviation and the binary values 1 and 0 are alternately transmitted, the signal S4 exceeds the dash-dotted threshold at equidistant times t1, t2, t5 and t6 and the demodulated data signal D21 changes its binary value at these times.

If the data signals D1 have a frequency deviation towards low frequencies, the pulse durations of the signals S3 are longer and the signals S4 thus have larger instantaneous values. The threshold in the sampling stage is thus exceeded or fallen below at times t0, t3, t4 and t7. The time periods between the edges of the data signals D22 are therefore no longer the same, so that step distortions occur.

The correction of these step distortions will now be described in connection with the time diagrams shown in FIG. 4.

In the time diagrams shown in FIG. 4, the time t is shown in the abscissa direction and the instantaneous values of signals at different points in the circuit arrangement in the ordinate direction. For reasons of clarity, the counter readings of a first counter stage Z1 are shown in an analog form, as would be given, for example, at the output of a digital-to-analog converter downstream of this counter stage

It is assumed that the data signals D2 have no step distortions between times t1 and t5 and step distortions between times t6 and t7. In both cases it is assumed that binary values 1 and 0 are transmitted alternately.

The clock generator TG generates reference signals B, the repetition frequency of which is equal to twice the step frequency of the data signals D2 and which are synchronized with the data signals D2 such that the edges of the data signals D2 each fall in the middle between two edges of the reference signals B. The data signals D2 and the reference signals B are fed to a comparator VG, which is designed, for example, as an equivalence element. The comparator VG generates signals S5 which always assume the binary value 1 or 0 when the data signals D2 and the reference signals B have the same or different binary values. The signals S5 are fed to the integrator JG.

The integrating element JG integrates the signals S5 and outputs control signals R to the timing element Z, which changes the measuring time in the event of a step distortion in such a way that the step distortion is counteracted.

The integrator JG contains a first counter stage Z1, which is advanced by clock pulses T2 for two periods of the data signals D2. The counter level is increased respectively. counted down when the signal S5 has the binary value i or 0. A decoder DC checks the counter readings represented by signals S6 or counter stage Z1 whether they exceed predetermined upper counter readings or fall below lower counter readings.

Between the times t1 and t2 and between the times t3 and t4, the data signals D2 and the reference signals B have different binary values and the signal S5 therefore has the binary value 0. Between the times t2 and t3, the data signals D2 and the reference signals B have the same sign , so that the signal S5 has the binary value 1. Between the times t1 and t2 and t3 and t4, the counter stage Z1 is thus counted down, while it is counted up between the times t2 and t3. Between the times t4 and t5, the counter stage Z1 is similarly counted up and down alternately between the times t1 and t4. At time t5, a signal S7 emitted by the clock generator TG queries whether the count is within or outside the upper and lower counter values. Since it was assumed that there was no step distortion, the counter stage Z has the counter reading 0 at time t5, which lies within the predetermined counter readings. No signal is thus emitted at the output of the decoder DC.

In a manner similar to that between times t1 and t5, the counting stage Z1 is alternately counted up and down between times t6 and t7. However, since a step distortion was assumed between the times t6 and t7, the counter stage Z1 is counted more frequently in one direction, here downwards than in the other direction, here upwards, so that there is a negative counter reading at time t7. This negative counter reading falls below a lower counter reading CLOSE. When the signal S7 occurs, the decoder DC outputs a signal S8 to a second counter stage Z2, which is counted down by one unit by the signal S8. If the count at the end of the count is greater than the upper count, a corresponding signal S9 is emitted, which counts the counting stage Z2 by one unit.

If there is no step distortion, the counter reading of counter stage Z2 is equal to the initial counter reading of the counter in timer Z. The counter reading of counter stage Z2 is determined by Control signals R shown, which are fed to the parallel inputs of the counter in the timer Z. If the count of the counter S2 is reduced by the signal S8, the initial count of the counter in the timer Z is also reduced, so that the measuring time is increased since more clock pulses T are required until the counter with the timer Z reaches the predetermined final counter. The pulse durations of the signals S3 are thus shortened and the DC voltage component due to the frequency deviation is reduced. This process is repeated until the DC voltage component caused by the frequency deviation has been completely corrected.

In order not to change the measuring time for each step distortion, for example as a result of one-time disturbances, it is expedient if the control signals R are only taken from the higher-order stages of the counter stage Z2. In this case, the counter stage Z2 must first be counted in one direction several times in succession before the control signals R change.

The counter in the timing element Z and the counting stages Z1 and Z2 are designed as commercially available counters, the counting stages Z1 and Z2 being able to be advanced in the upward and downward directions. The low-pass filter TP is preferably designed as an active low-pass filter in a known manner, and the sampling stage AS is preferably designed using an operational amplifier as a Schmitt trigger with low hysteresis.

Claims (6)

1. A circuit arrangement for correcting signal element distortions during a data transmission employing frequency-modulated signals, wherein a demodulator is provided which compares the time lapse between flanks of the frequency-modulated data signals with a test period produced by a timer unit and which after filtering produces demodulated data signals which exhibit signal element distortions in the case of frequency deviations of the frequency-modulated data signals, characterised by a comparator (VG) which compares the instantaneous values of the demodulated data signals (D2) with the instantaneous values of reference signals (B) having a repetition frequency twice that of the signal element frequency of the demodulated data signals (D2), and by an integrating stage (JG) which integrates the output signals (S5) of the comparator (VG) and emits to the demodulator (DM) regulating signals (R) that counteract the signal element distortions of the demodulated data signals (D2) by changing the test period duration.

2. A circuit arrangement as claimed in claim 1, wherein the timer unit in the demodulator is formed by a counter which is advanced by clock pulses having a constant repetition frequency and whose counting range determines the test period duration, characterised in that the regulating signals (R) emitted by the integrating stage (JG) are fed to the counter in the timer unit (Z) and change the counting range thereof.

3. A circuit arrangement as claimed in claim 2, characterised in that the regulating signals (R) change the initial count of the counter in the timer unit (Z).

4. A circuit arrangement as claimed in one of claim 1 to 3, characterised in that the integrating stage (JG) comprises a first counting stage (Z1) which, in dependence upon the output signal (S5) of the comparator (VG), counts up or down during predetermined periods of time and comprises a second counting stage (Z2) which counts up or down, as the case may be, when the first counting stage has overshot or undershot predetermined counts and which emits the regulating signals (R).

5. A circuit arrangement as claimed in claim 4, characterised in that the integrating stage (JG) comprises a decoder (DC) which recognises the predetermined counts of the first counting stage (Z1) and emits corresponding signals (S8, S9) to the second counting stage (Z2).

6. A circuit arrangement as claimed in one of claims 1 to 5, characterised in that an equivalence gate is provided as comparator (VG).

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