EP0003308A1 - Correction circuit for frequency errors in data transmission - Google Patents

Abstract

The invention relates to a circuit arrangement for correcting frequency errors in the transmission of data by data signals (D) which are modulated in accordance with a frequency differential phase modulation. The circuit arrangement corrects frequency errors which occur during the transmission of the data signals (D) from a data transmitter to a data receiver. The data receiver contains a control stage (R), in which the data signals (D) are implemented using mixed signals (MS). The repetition frequency of the mixed signals (MS) is controlled with the aid of a first control unit (R1) which carries out fine control and a second control unit (R2) which carries out coarse control so that frequency errors in the data signal (D) are corrected. A controller (RG) generates the mixed signals (MS) from clock pulses of a given repetition frequency with the help of frequency multipliers. The frequency multipliers are controlled by control signals (RS), which selectively connects a selection unit (AW) from the first control unit (R1) or the second control unit (R2) to the controller (RG).

Description

The invention relates to a circuit arrangement for correcting frequency errors in a transmission of data by data signals which are modulated according to a frequency differential phase modulation, in which a control stage is provided which generates corrected data signals from the data signals and in which from the corrected data signals by means of a Demodulator the transmitted data can be recovered.

For the transmission of data via short-wave connections, it is already known to modulate the data signals in accordance with a frequency-differential phase modulation. This type of modulation is particularly suitable for short-wave connections, since two adjacent transmission channels differ only slightly in the phase distortions and in the modulatics sections. In the case of frequency-differential phase modulation, the data in the phase differences are therefore several contain simultaneously transmitted data signals with neighboring frequencies. The frequency band in which the frequencies of the data signals are contained is referred to as the baseband. The two frequencies that limit the baseband are the reference frequencies. In the data receiver, the data signals are converted into two group signals with two mixed signals. A demodulator retrieves the transmitted data from the group signals.

In order to achieve great insensitivity to frequency distortions, a circuit arrangement for: correcting frequency errors is required. Special requirements are placed on this circuit arrangement. The frequency errors related to the center frequency of the data signals must be corrected to less than 1 Hz. The circuit arrangement should have a large frequency range and the control range and the control speed should be able to be changed in a simple manner, depending on the application. If the received data signals fail, the control status must be maintained. Furthermore, radio interference must not influence the control and the control should take place without the use of pilot signals.

It is already known to use control loops to correct frequency errors. With these control loops, the repetition frequency of an oscillator is changed depending on control signals. The oscillator is, for example, a voltage-controlled oscillator or a quartz oscillator, which is followed by a frequency divider with a variable division ratio. A circuit arrangement for correcting frequency errors in a frequency differential phase modulation, which meets the above requirements, is not yet known.

The invention is therefore based on the object of specifying a circuit arrangement for correcting frequency errors when transmitting data using frequency-differential phase modulation, which has a high degree of accuracy.

According to the invention, the object is achieved in the circuit arrangement of the type mentioned at the outset by a modulator which, by converting the data signals with mixed signals, generates group signals which represent the corrected data signals, by a first control unit which generates fine control signals from the group signals when the frequency error of the mixed signals is smaller than a predetermined amount, by a second control unit that generates coarse control signals from the group signals if the frequency error is greater than the predetermined amount, by a selection stage that generates control signals depending on the size of the frequency error from the fine control signals and the coarse control signals, and by a controller which generates the mixed signals from clock pulses of a predetermined repetition frequency as a function of the control signals.

The circuit arrangement according to the invention has the advantage that very small frequency errors can be detected and corrected by using the first control unit. As a result of the second control unit, the circuit arrangement has a large capture range. Due to the use of integrated digital circuits, the circuit arrangement requires little effort and can be easily adapted to the desired application. If the data signals are interrupted, no control signals are generated and the repetition frequencies of the mixed signals are maintained until control signals appear again.

An advantageous embodiment of the circuit arrangement is achieved if the first control unit contains a first frequency divider that divides the repetition frequency of the group signals by a predetermined factor and that generates measurement signals, contains a second frequency divider that is released during the time period defined by the measurement signals, which divides the repetition frequency of the clock pulses by a predetermined factor and that generates control signals and that the first control unit contains a counter that is counted up or down depending on the control signals and that generates the fine control signals when predetermined values are reached. In order to ensure that the measurement signals only occur at times at which the group signals have settled, it is advantageous if the first control unit contains a phase detector which resets the frequency dividers whenever the phase of the group signals changes.

The criterion for the rough regulation is generated in a simple manner if the second regulating unit has two discriminatory rules. Contains nators that generate signals with first or second binary values if the frequencies of the group signals are within or outside a predetermined frequency range and contains an encoder that generates the coarse control signals from the signals generated by the discriminators.

In order to be able to check the quality of the received data signals in a simple manner, it is advantageous if the second control stage contains a frequency divider which is advanced by clock pulses of a lower repetition frequency, which is reset with every change in the signals emitted by the discriminators and the blocking signals to the encoder delivers.

To generate the group signals, it is advantageous if the controller contains a first and a second frequency multiplier, which can change the repetition frequency of the clock pulses as a function of output signals output by a counter. Division factors and which produce the mixed signals if the output signals are fed directly to the first frequency multiplier and to the second frequency multiplier via an adder which subtracts a constant dual number from the dual number represented by the output signals and if the controller contains an encoder which is dependent on the control signals up the counter. or counts down.

To eliminate short-term fluctuations in the group signals, it is advantageous if each frequency multiplier is followed by a frequency divider which divides the sequence frequencies of the mixed signals by a predetermined division factor.

In the following an embodiment of the circuit arrangement according to the invention will be described with reference to drawings.

• Fig. 1 ein Blockschaltbild einer Anordnung zum Ubertragen von Daten,
• Fig. 2 ein Schaltbild einer ersten Regeleinheit,
• Fig. 3 ein Zeitdiagramm von Signalen an verschiedenen Punkten der ersten Regeleinheit,
• Fig. 4 ein Schaltbild eines Modulators und einer zweiten Regeleinheit,
• Fig. 5 ein Zeitdiagramm von Signalen an verschiedenen Punkten der zweiten Regeleinheit,
• Fig. 6 ein Schaltbild einer Auswahlstufe und eines Reglers.

Show it:

• 1 is a block diagram of an arrangement for transmitting data,
• 2 shows a circuit diagram of a first control unit,
• 3 shows a time diagram of signals at different points of the first control unit,
• 4 is a circuit diagram of a modulator and a second control unit,
• 5 shows a time diagram of signals at different points of the second control unit,
• Fig. 6 is a circuit diagram of a selection stage and a controller.

In the circuit arrangement shown in FIG. 1, a data source DQ provided in a data transmitter generates data and outputs it to a transmitter SE. The transmitter SE generates data signals and transmits them to a data receiver via a transmission link UB. The data signals are modulated in a known manner in accordance with frequency differential phase modulation. The data receiver contains a receiver EM, which converts the data signals transmitted over the transmission link UB into data signals D suitable for further processing. The frequencies of the data signals D are, for example, inside the voice band in the range between 1040 and 240C Rz. The data signals D are therefore also referred to as baseband signals. The data signals D are present at a control stage R, in which the data signals D are modulated with mixed signals MS and the group signals GR are generated, from which a demodulator DM recovers the transmitted data and outputs it to a data sink DS.

The control stage R contains a first control unit R1, which generates fine control signals F from tract pulses T1 with a high repetition frequency, with which the repetition frequency of the line signals MS is fine-tuned. Furthermore, the control stage R contains a second control unit R2, which generates coarse control signals G from the group signals GR and clock pulses T2 with a low repetition frequency, with which a coarse control of the mixed signal MS is carried out. The fine control signals F and the coarse control signals G are optionally supplied via a selection call AW to a controller RG which, depending on the deviation of the repetition frequency of the mixing signals M from a desired frequency, regulates these deviations either with the aid of the fine control signals F or the coarse control signals G.

The control unit R1 shown in FIG. 2 contains one Bandpass B1, a limiter stage BG, a phase detector PH, two frequency dividers FT1 and FT2, a counter Z1, a flip-flop FF and two AND gates U1 and U2. Further details of the control unit R1 are described together with the time diagrams shown in FIG. 3.

In the time diagrams shown in FIG. 3, the time t is shown in the abscissa direction and the instantaneous values of signals at different points of the control unit R1 in the ordinate direction. The modulator MD generates the group signals GR1 and GR2 by converting the data signals D. The group signals GR1 are present at bandpass B1. The bandpass has a center frequency of 4160 Hz and a bandwidth of 40 Hz. The group signals GR1 have frequencies in the range from 3520 to 4160 Hz. The signals at the output of the bandpass B1 are fed to the limiter BG, which amplifies and limits the signals and outputs data signals DA. These data signals DA are present on the one hand at a phase detector PH which detects phase jumps in the data signals DA and on the other hand at the clock inputs of a frequency divider FT1 designed as a counter and a counter Z1 designed as a two-direction counter. The frequency divider FT1 divides the repetition frequency of the data signals DA by a factor of 64 and outputs measurement signals S2 at its output. The phase detector PH outputs signals S1 at its output, which reset the frequency dividers FT1 and FT2 and the flip-flop FF.

At time t1, the group signal GR1 takes a positive value. At the same time, the data signal DA assumes the binary value 1. Assuming that the measurement signal S2 also has the binary value 1, the AND gate U2 emits clock pulses T3, the repetition frequency of which corresponds to the repetition frequency of the clock pulses T1 of 3.9936 MHz. The clock pulses T3 are present at the clock input of the frequency divider FT2, which divides the repetition frequency of the clock pulses T3 by the division factor 30720. The frequency divider FT2 is followed by the AND gate U1, which always outputs the signal S3 with the binary value 1 when the counter readings of the frequency divider FT2 correspond to a repetition frequency of the group signals GR1, which is greater than 4176 Hz and less than 4144 Hz. Always if the signal S3 assumes the binary value 1, the counter Z1 is blocked. This prevents the control unit R1 from emitting a fine control signal if the repetition frequency of the group signals GR1 deviates from the nominal frequency of 4160 Hz by more than ± 16 Hz. The signal S3 assumes the binary value 0 at the time t2.

The signal at the most significant output of the frequency divider FT2 is present at the clock input of the flip-flop FF. The flip-flop FF outputs the signal S4, which determines the direction in which the counter Z1 counts. The signal S4 assumes the binary value 1 at the time t3 and causes the counter Z1 to count up while it was counting down until the time t3.

At time t4, the measurement signal S2 assumes the binary value 0. The AND gate U2. thus no longer emits clock pulses T3. The counter Z1 has reached a predetermined counter reading, which depends on whether more clock pulses have occurred while the counter has been counting down or up. For example, it is assumed that the count = Z1 has reached a counter reading at time t4 which is greater than half of its counting range.

At time t5, a phase jump of 180 ° occurs in the group signal GR1. The phase detector PH detects the phase jump and generates a pulse S1, which the Fre quenzteiler FT1 and FT2 and the flip-flop FF resets. Subsequently, similar processes are repeated between times t5 and t6 as between times t1 and t5. It is assumed that between the times t5 and t6 more clock pulses T3 have occurred which count the counter Z1 upwards than those which count it down. Similar processes are repeated after time t6. Again more clock pulses T3 occur, which count the counter Z1 upwards, so that the counter Z1 reaches its greatest counter reading at the time t7 and generates a carry signal. The counter Z1 transmits this transmission signal as a fine control signal F1 to the controller RG via the selection stage AW as a control signal RS. In addition, the counter Z1 emits a fine control signal F2, which indicates that the carry signal is emitted when counting up. The fine control signal F2 thus corresponds to the sign, while the pure control signal F1 corresponds to the amount of the counter reading.

The modulator MD shown in FIG. 4 contains two mixer stages M1 and M2, to each of which the data signals D, the baseband signals, are supplied at a first input. The mixed signals MS1 and MS2 are present at second inputs. The mixed signals MS1 and MS2 are generated in the controller RG and they have repetition frequencies of 5200 Hz and 5920 Hz. The mixing stages M1 and M2 are followed by low-pass filters TP1 and TP2, which emit the group signals GR1 and GR2.

The group signals GR1 and GR2 are applied to the control unit R2. It contains two discriminators D1 and D2, an encoder CD1, a differentiator DIF, a frequency divider FT3 and an AND gate U3. With the help of the control unit R2, the criterion for the rough control is generated. The control unit R2 emits coarse control signals G1 and G2, which indicate the sign of the frequency error if its magnitude is also greater than 15 Hz. The coarse control signals G1 and G2 are generated by reacting ent, each with a band-pass filter in the discriminators D1 and D2 _- separates whether spectral lines fall of group signals in the pass band or not. The pass band passbands are arranged so that if there is a frequency error greater than 15 Hz, one of the band passes will not produce a signal. The output signal of this bandpass then determines the sign of the frequency error.

The discriminators D1 and D2 each contain a bandpass filter B2 and B3, the center frequency of which is set to 4110 and 3570 Hz, and each of which has a bandwidth of 80 Hz. The pass bands of these bandpasses B2 and B3 are thus arranged at the upper and lower limits of the frequencies of the group signals of 4160 and 3520 Hz. Each band pass is followed by a rectifier, which generates DC voltage signals and sends them to a threshold level. Each threshold level compares the signal at the output of the rectifier with a threshold value. If the frequencies of the group signals GR1 and GR2 are shifted such that they exceed the frequency range from 3520 to 4160 Hz by more than 15 Hz, the discriminators D1 and D2 emit signals G1 and S5 with the binary value 0. Otherwise, the signals have the binary value 1. Further details of the control unit R2 are described together with the diagrams shown in FIG. 5.

5 shows the frequency range of the group signals GR1 and GR2 and the pass bands of the bandpasses B2 and B3 in the discriminators D1 and D2. The coarse control signals G1 and G2 and a blocking signal S6 are shown in the associated time diagrams.

At time t1 it is assumed that the frequencies of the group signals GR1 are shifted to the left by more than 15 Hz, so that the coarse control signal G1 assumes the binary value 0, while the signal S5 has the binary value 1. It is also assumed that radio interference occurs. In this case, no rough regulation should take place. The coarse control signals G1 and the signals S5 are fed to the differentiator DIF, which resets the frequency divider FT3 whenever the coarse control signals G1 and the signals S5 change. Counting pulses are present at the clock input of the frequency divider FT3 and are output at the output of the AND gate U3. The clock pulses T2 with a repetition frequency of 2.5 Hz, for example, and the blocking signals S6 output at the most significant output of the frequency divider FT3 are present at the inputs of the AND gate U3. The counting range of the frequency divider FT3 is designed such that the blocking signal S6 always assumes the binary value 1 if no changes in the coarse control signals G1 and the signals S5 occur within 6 seconds. During the radio interference, the blocking signal S6 blocks the encoder CD1 and the coarse control signal G2 assumes the binary value 0.

At time t2 it is assumed that the radio interference has ended and the blocking signal S6 assumes the binary value 1. The coarse control signal G2 thus also assumes the binary value 1. Between times t2 and t3, the coarse control signal G1 has the binary value O, while the coarse control signal G2 has the binary value 1. In this case there is a rough synchronization. Between the times t3 and t4 it is assumed that frequencies of the group signals GR1 and GR2 lie within the pass bands of the bandpasses B2 and B3 and thus the discriminators D1 and D2 each emit signals G1 and S5 with the binary value 1. In this case, the frequency deviation is less than 15 Hz and there is no coarse synchronization.

Between times t4 and t5 it is assumed that the frequencies at the lower limit of the frequency band of the group signals GR2 no longer lie in the pass band of the band pass B3 and the signal S5 thus has the binary value O. In this case, a rough control takes place, just like between the times t2 and t3.

The selection stage AW shown in FIG. 6 contains two switches which are controlled by the coarse control signal G2. Switch in the solid position. the switches through the fine control signals F1 and F2 as control signals RS1 and RS2 to the controller RG. In this case, the coarse control signal G2 has the binary value O. If the coarse control signal G2 has the binary value 1 and thus indicates that a coarse control is being carried out, the coarse control signals G1 and the clock pulses T2 are switched through to the controller RG as control signals RS1 and RS2.

The controller RG contains an encoder CD2, a counter Z2, an adder AD, two frequency multipliers FM1 and FM2 and two frequency dividers FT4 and FTS. The frequency multipliers FM1 and FM2 are supplied with the clock pulses T1 at the clock inputs. They divide the repetition frequency of the clock pulses T1 by division factors which are determined by signals emitted by the counter Z2 and by the adder AD. Frequency multipliers of this type are generally known and can be assembled, for example, from three integrated digital modules which are commercially available under the designation SN7497. The counter Z2 is designed as a two-direction counter and is counted up or down as a function of two vcm encoders CD2. When the circuit arrangement is switched on, the counter is set to a value by closing the switch SW, which is set such that the mixed signals MS1 and MS2 reach the setpoints of 5200 or 5920 Hz. For this purpose, the outputs of the counter Z2 are connected to the inputs of the frequency multiplier FM1 and to the inputs of an adder AD, which always subtracts the value 12 represented as a binary number from the counter reading of the counter Z2. The outputs of the adder AD are connected to the inputs of the frequency multiplier FM2. The frequency multipliers FM1 and FM2 are at their Ausgän- ^g s output signals, the frequency divider FT4 and FT5 having a constant division factor of 512, for example, downstream to eliminate short-term fluctuations of the repetition frequency. Immediately after switching on the circuit arrangement, the frequency multipliers FM1 and FM2 have division ratios with which the repetition frequency of the clock pulses T1 is divided such that on the one hand the mixed signals MS1 have the repetition frequency 5200 Hz and on the other hand the mix signals MS2 have the repetition frequency 5920 Hz.

In the case of the rough control, controlled by the rough control signal G2, the switches in the selection stage AW assume the position shown in dashed lines. In this case, the encoder CD2 generates from the control signals RS1 and RS2 counting pulses with the repetition frequency of the clock pulses T2, which count the counter Z2 up or down depending on the coarse control signal G1. As a result of the changed counter reading of the counter Z2, the frequency multipliers FM1 and FM2 change the division factor and the repetition frequency of the mixed signals MS1 and MS2 is changed. If . no coarse control is carried out, the coarse control signal G2 assumes the binary value 0 and brings the switches in the selection stage AW to the position shown in solid lines. In this case, the encoder CD2 generates counting pulses from the control signals RS1 and RS2, which counter Z2 with the repetition frequency of the fine control signals F1 count up or down. The counting direction is determined by the fine control signal F2.

In order to prevent the sequence frequencies of the mixed signals MS1 and MS2 from exceeding predetermined limit values, the outputs of the counter Z2 are connected to the encoder CD2. The encoder CD2 prevents the generation of counting pulses if the counter readings of the counter Z2 exceed or fall below corresponding limit values.

Claims (7)

1. Circuit arrangement for correcting frequency errors in a transmission of data by data signals which are modulated according to a frequency differential phase modulation, in which a level stage is provided which generates corrected data signals from the data signals and in which the corrected data signals by means of a demodulator transmitted data are recovered, characterized by a modulator (MD) which, by converting the data signals (D) with mixed signals (MS1, MS2), generates group signals (GR1 and GR2), which represent the corrected data signals, by a first control unit (R1), which generates fine control signals (F1, F2) from the group signals (GR1) when the frequency error of the measurement signals (MS1, MS2) is less than a predetermined amount, by a second control unit (R2) which generates coarse control signals from the group signals (GR1, GR2) (G1, G2) generated when the frequency error is larger than the predetermined amount by a selection stage e (AW), which, depending on the size of the frequency error, generates control signals (RS1, RS2) from the fine control signals (F1, F2) and the coarse control signals (G1, G2) and by a controller (RG), which consists of clock pulses (T1) predefined repetition frequency depending on the control signals (RS1, RS2) generates the mixed signals (MS1, MS2). 2. Circuit arrangement according to claim 1, characterized in that the first control unit (R1) contains a first frequency divider (FT1) which divides the repetition frequency of the group signals (GR1) by a predetermined factor and generates the measurement signals (S2), a second frequency divider (FT2) contains the time during the time determined by the measurement signals (S2) duration is released, which divides the repetition frequency of the clock pulses (T1) by a predetermined factor and generates the control signals (S3) and that the first control unit (R1) contains a counter (Z1) which is dependent on the control signals (S3) or up is counted down and which generates the fine control signals (F1, F2) when predetermined values are reached. 3. Circuit arrangement according to claim 1, characterized in that the first control unit (R1) contains a phase detector (PH) which resets the frequency dividers (FT1, FT2) with each change in the phase of the group signals (GR1). 4. Circuit arrangement according to one of claims 1 to 3, characterized in that the second control unit (R2) contains two discriminators (D1, 2), the signals (G1, S5) with first or second unit values ("1" or " 0 ") if the frequencies of the group signals (GR1, GR2) lie within or outside of its predetermined frequency range and contain a cofier (CD1) which uses the signals (G1, S5) generated by the discriminators (D1, D2) Coarse control signals (G1, G2) are generated. 3. A circuit arrangement according to claim 4, characterized in that the second Regeleinmeit (R2) contains a frequency divider (FT3) which is stepped by Maktimpulse (T2) low repetition frequency, the signals emitted by the discriminators (D1, D2) with each change (G1, S5) is reset and the blocking signals (S6) are emitted to the encoder (CD1). - .. Circuit arrangement according to one of the preceding claims, characterized in that the controller (RG) contains a first and second frequency multiplier (FM1, FM2) which divide the repetition frequency of the clock pulses (T1) as a function of output signals output by a counter (Z2) by variable division factors and which divide the mixed signals (MS1, MS2) generate that the output signals are fed directly to the first frequency multiplier (FM1) and to the second frequency multiplier (FM2) via an adder (AD) which subtracts a constant dual number from the dual number represented by the output signals and that the controller (RG) unites Contains encoder (CD2), which counts the counter (Z2) up or down depending on the control signals (RS1, RS2). 7. Circuit arrangement according to claim 6, characterized in that each frequency multiplier (FM1, FM2) is followed by a frequency divider (FT4, FTS) which divides the repetition frequencies of the mixed signals (MS1, MS2) each by a predetermined division factor.

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