EA201700119A1 - DEVICE FOR DIRECT DISPLAY OF ADDRESSES OF DATA, LOCATED IN EXTERNAL SEQUENTIAL ROM, INTO ADDRESS OF MICROPROCESSOR CORE, COMPUTER SYSTEM AND DATA TRANSMISSION METHOD - Google Patents
DEVICE FOR DIRECT DISPLAY OF ADDRESSES OF DATA, LOCATED IN EXTERNAL SEQUENTIAL ROM, INTO ADDRESS OF MICROPROCESSOR CORE, COMPUTER SYSTEM AND DATA TRANSMISSION METHODInfo
- Publication number
- EA201700119A1 EA201700119A1 EA201700119A EA201700119A EA201700119A1 EA 201700119 A1 EA201700119 A1 EA 201700119A1 EA 201700119 A EA201700119 A EA 201700119A EA 201700119 A EA201700119 A EA 201700119A EA 201700119 A1 EA201700119 A1 EA 201700119A1
- Authority
- EA
- Eurasian Patent Office
- Prior art keywords
- data
- address
- microprocessor core
- rom
- addresses
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Stored Programmes (AREA)
- Microcomputers (AREA)
- Digital Computer Display Output (AREA)
Abstract
Изобретение относится к системам памяти и способам управления ими с возможностью выполнять программу с того же накопителя, где она размещена, без ее предварительной загрузки в оперативную память микропроцессора применительно к недорогим компьютерным системам с небольшим объемом оперативной памяти и к способам передачи данных в них. Компьютерная система, включающая в себя систему на кристалле и внешнее последовательное ПЗУ, и соответствующий способ передачи данных основаны на работе устройства прямого отображения адресов данных внешнего последовательного ПЗУ в адресное пространство микропроцессорного ядра, которое характеризуется тем, что включает в себя регистр считанных данных, регистр адреса и конечный автомат устройства прямого отображения адресов, с возможностью осуществления прямого отображения адресов данных внешнего последовательного ПЗУ, в адресное пространство микропроцессорного ядра, преобразования запросов на чтение со стороны микропроцессорного ядра в последовательность обращений к контроллеру внешнего последовательного ПЗУ и передачи по шине данных последовательности слов данных, считанных из внешнего последовательного ПЗУ, в микропроцессорное ядро.The invention relates to memory systems and methods for managing them with the ability to execute a program from the same drive where it is located, without preloading it into the microprocessor’s main memory as applied to low-cost computer systems with a small amount of RAM and to methods for transmitting data to them. The computer system, which includes a system-on-chip and an external serial ROM, and the corresponding data transfer method are based on the operation of a device for directly mapping data addresses of an external serial ROM to the address space of the microprocessor core, which is characterized by the fact that it includes the read data register, the address register and the state machine of the device for direct address mapping, with the possibility of realizing the direct mapping of data addresses of the external sequential ROM, to the address a space of the microprocessor core, the conversion of requests to read from the microprocessor core in a sequence of calls to a controller external serial ROM and transmission over the data bus the sequence of data words read from the external serial ROM in the microprocessor core.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RU2014135505/08A RU2579942C2 (en) | 2014-09-01 | 2014-09-01 | Device for direct mapping of data addresses, located in external serial rom, to address space of microprocessor core, computer system and method of transmitting data |
PCT/RU2015/000553 WO2016036281A1 (en) | 2014-09-01 | 2015-09-01 | Device for the direct mapping of data addresses |
Publications (2)
Publication Number | Publication Date |
---|---|
EA201700119A1 true EA201700119A1 (en) | 2017-10-31 |
EA039007B1 EA039007B1 (en) | 2021-11-22 |
Family
ID=53284987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EA201700119A EA039007B1 (en) | 2014-09-01 | 2015-09-01 | Device for direct mapping of data addresses located in the external serial rom into the address space of microprocessor core, computer system, and data transmission method |
Country Status (3)
Country | Link |
---|---|
EA (1) | EA039007B1 (en) |
RU (1) | RU2579942C2 (en) |
WO (1) | WO2016036281A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111858457B (en) * | 2020-07-15 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
CN112817902B (en) * | 2021-02-05 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Interconnected bare chip interface management system and initialization method thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5546546A (en) * | 1994-05-20 | 1996-08-13 | Intel Corporation | Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge |
US5535360A (en) * | 1994-08-31 | 1996-07-09 | Vlsi Technology, Inc. | Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor |
US6601167B1 (en) * | 2000-01-14 | 2003-07-29 | Advanced Micro Devices, Inc. | Computer system initialization with boot program stored in sequential access memory, controlled by a boot loader to control and execute the boot program |
JP2004334486A (en) * | 2003-05-07 | 2004-11-25 | Internatl Business Mach Corp <Ibm> | Starting system using boot code and starting method |
KR100693924B1 (en) * | 2005-01-31 | 2007-03-12 | 삼성전자주식회사 | Booting system using high speed serial interface and booting method of the same |
-
2014
- 2014-09-01 RU RU2014135505/08A patent/RU2579942C2/en active
-
2015
- 2015-09-01 EA EA201700119A patent/EA039007B1/en unknown
- 2015-09-01 WO PCT/RU2015/000553 patent/WO2016036281A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
RU2014135505A (en) | 2015-05-27 |
WO2016036281A1 (en) | 2016-03-10 |
EA039007B1 (en) | 2021-11-22 |
RU2579942C2 (en) | 2016-04-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW201612909A (en) | Semiconductor memory device, memory controller and memory system | |
MX2018004966A (en) | Parking support method and parking support device. | |
EP3129887A4 (en) | Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type | |
MX364759B (en) | Wearable data management during an incident. | |
EP3314363A4 (en) | Opportunistic power management for managing intermittent power available to data processing device having semi-non-volatile memory or non-volatile memory | |
IN2015DN01261A (en) | ||
EP2857952A4 (en) | Method for processing input/output request, host, server, and virtual machine | |
BR112013033792A2 (en) | computer system, method for accessing an express peripheral component interconnect endpoint device and device | |
EP3286640A4 (en) | Computer processor with separate registers for addressing memory | |
NZ621204A (en) | System including operation device and information storing apparatus, method performed by the system, and the information storing apparatus | |
PH12016501374A1 (en) | Computer, control device, and data processing method | |
JP2017073129A5 (en) | ||
MX362169B (en) | Process system managmenet system, server device, management program, and management method. | |
BR112015032781A2 (en) | data acquisition module, data processing unit, pixel matrix driver, display device and data acquisition method | |
EP2804109A3 (en) | Computer system, server module, and storage module | |
JP2016509714A5 (en) | ||
GB201002728D0 (en) | Trace data priority selection | |
FR3029376B1 (en) | METHOD FOR PROCESSING A DATA DELIVERY REQUEST, DEVICE, PROXY MODULE, CLIENT TERMINAL AND COMPUTER PROGRAM | |
MX2017007060A (en) | Method for accessing data in a memory at an unaligned address. | |
EA201700119A1 (en) | DEVICE FOR DIRECT DISPLAY OF ADDRESSES OF DATA, LOCATED IN EXTERNAL SEQUENTIAL ROM, INTO ADDRESS OF MICROPROCESSOR CORE, COMPUTER SYSTEM AND DATA TRANSMISSION METHOD | |
GB2512548A (en) | Equalizing bandwidth for multiple requesters using a shared memory system | |
WO2013109234A3 (en) | Method to accelerate message signaled interrupt processing | |
BR112017013537A2 (en) | computer-implemented method | |
MX361508B (en) | System and method for inter-module communication. | |
CL2018001109A1 (en) | Systems and procedures for tax collection, analysis and compliance |