EA200000641A1 - Многослойная коммутационная плата - Google Patents

Многослойная коммутационная плата

Info

Publication number
EA200000641A1
EA200000641A1 EA200000641A EA200000641A EA200000641A1 EA 200000641 A1 EA200000641 A1 EA 200000641A1 EA 200000641 A EA200000641 A EA 200000641A EA 200000641 A EA200000641 A EA 200000641A EA 200000641 A1 EA200000641 A1 EA 200000641A1
Authority
EA
Eurasian Patent Office
Prior art keywords
multilayer box
multilayer
box
Prior art date
Application number
EA200000641A
Other languages
English (en)
Other versions
EA001812B1 (ru
Original Assignee
Таран, Александр Иванович
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Таран, Александр Иванович filed Critical Таран, Александр Иванович
Publication of EA200000641A1 publication Critical patent/EA200000641A1/ru
Publication of EA001812B1 publication Critical patent/EA001812B1/ru

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10666—Plated through-hole for surface mounting on PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
EA200000641A 1998-12-08 1999-03-01 Многослойная коммутационная плата EA001812B1 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RU98121772A RU2133081C1 (ru) 1998-12-08 1998-12-08 Многослойная коммутационная плата (варианты)
PCT/RU1999/000053 WO2000035258A1 (en) 1998-12-08 1999-03-01 Multilayered switching plate

Publications (2)

Publication Number Publication Date
EA200000641A1 true EA200000641A1 (ru) 2001-02-26
EA001812B1 EA001812B1 (ru) 2001-08-27

Family

ID=20212938

Family Applications (1)

Application Number Title Priority Date Filing Date
EA200000641A EA001812B1 (ru) 1998-12-08 1999-03-01 Многослойная коммутационная плата

Country Status (6)

Country Link
US (1) US6627823B1 (ru)
KR (1) KR20010089564A (ru)
AU (1) AU2646199A (ru)
EA (1) EA001812B1 (ru)
RU (1) RU2133081C1 (ru)
WO (1) WO2000035258A1 (ru)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084354B2 (en) * 2002-06-14 2006-08-01 Intel Corporation PCB method and apparatus for producing landless interconnects
US6809269B2 (en) * 2002-12-19 2004-10-26 Endicott Interconnect Technologies, Inc. Circuitized substrate assembly and method of making same
EA010269B1 (ru) * 2008-02-14 2008-06-30 АЛЬТЕРА СОЛЮШИОНС Эс.Эй. Контактный узел на встречных контактах с капиллярным соединительным элементом и способ его изготовления
JP2011049664A (ja) * 2009-08-25 2011-03-10 Seiko Instruments Inc パッケージの製造方法、圧電振動子の製造方法、発振器、電子機器および電波時計
RU2459314C1 (ru) * 2011-04-06 2012-08-20 Российская Федерация, от имени которой выступает Государственная корпорация по атомной энергии "Росатом" Способ изготовления тонкопленочных многоуровневых плат для многокристальных модулей, гибридных интегральных схем и микросборок
RU2534024C1 (ru) * 2013-05-29 2014-11-27 Открытое акционерное общество "Российская корпорация ракетно-космического приборостроения и информационных системы" (ОАО "Российские космические системы") Способ изготовления многослойной печатной платы сверхплотного монтажа

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729185U (ru) * 1980-07-28 1982-02-16
DE3918423A1 (de) * 1989-06-06 1990-12-13 Schoeller & Co Elektronik Zweilagige, durchkontaktierte starr-flexible schaltung und verfahren zu ihrer herstellung
US5340947A (en) * 1992-06-22 1994-08-23 Cirqon Technologies Corporation Ceramic substrates with highly conductive metal vias
RU2088057C1 (ru) * 1992-07-27 1997-08-20 Государственное научно-производственное предприятие "Исток" Многослойная гибридная интегральная схема свч и квч диапазонов
US5355283A (en) * 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
JP3290041B2 (ja) * 1995-02-17 2002-06-10 インターナショナル・ビジネス・マシーンズ・コーポレーション 多層プリント基板、多層プリント基板の製造方法
US5621193A (en) * 1995-05-23 1997-04-15 Northrop Grumman Corporation Ceramic edge connect process
US5874770A (en) * 1996-10-10 1999-02-23 General Electric Company Flexible interconnect film including resistor and capacitor layers
JP2000101245A (ja) * 1998-09-24 2000-04-07 Ngk Spark Plug Co Ltd 積層樹脂配線基板及びその製造方法
US6054761A (en) * 1998-12-01 2000-04-25 Fujitsu Limited Multi-layer circuit substrates and electrical assemblies having conductive composition connectors

Also Published As

Publication number Publication date
US6627823B1 (en) 2003-09-30
RU2133081C1 (ru) 1999-07-10
AU2646199A (en) 2000-06-26
KR20010089564A (ko) 2001-10-06
WO2000035258A1 (en) 2000-06-15
EA001812B1 (ru) 2001-08-27

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Legal Events

Date Code Title Description
MM4A Lapse of a eurasian patent due to non-payment of renewal fees within the time limit in the following designated state(s)

Designated state(s): AM AZ BY KZ KG MD TJ TM RU