DK159336B - LIMIT VALUE NOTIFICATION FOR EXCHANGE SIGNALS - Google Patents

Description

DK 159336 B

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold signal device for alternating signals with a comparator whose signal input is applied to the alternating signal as unidirectional voltage and whose reference input is applied to a limit value determining reference DC voltage and whose output exceeds the limit value for generating a signal signal. potential to another potential and switches back again at below the limit value.

In known limit value devices of this kind, the alternating signal is converted to a DC voltage which is not only unidirectional but also smoothed so that an accurate comparison with the reference DC voltage can be made. In this way, a very good smoothing must be done, as a residual pulsation would cause a constant exchange of the comparator's starting potential. However, good smoothing leads to a correspondingly large time delay, which in many cases, for example, by monitoring overflows, cannot be accepted.

It is further known (US-PS 3,836,854) to apply single pulses generated by one rectifier of a sinusoidal alternating signal to one input of a bistable comparator and to connect the other input to a reference potential above zero.

On the comparator output is a timing means which in the triggered state overrides the comparator with a reset pulse such that for the duration of the reset pulse the comparator has a constant output signal. The reset pulse is triggered by the back flank of the comparator output signal and additionally applied to the D input of a D flip flop over a delay link. The D flip-flop clock input is also connected to the comparator output. The leading edge of a clock input signal 30 causes the tilting of the D flip flop to the signal state prevailing at the D input. The reset pulse duration is somewhat longer than the time required by a normal alternating signal, however shorter than the time required by a too small alternating signal for the passage of area 2.

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the reference potential - zero - reference potential. The delay time of the delay link is shorter than the reset pulse duration.

Therefore, in the normal case, at a sufficiently large alternating signal, the reset pulse overlaps the normal beginning of the following comparator output pulse so that this beginning is practically moved to the leading edge of the reset pulse. Therefore, the leading edge of the comparator output pulse and the clock signal, respectively, has already disappeared before the reset pulse across the delay link results in the D input of the D flip-flop, so that it normally maintains its tilt state.

On the other hand, when the amplitude of the alternating signal is so small that it exceeds the reference potential, but has not yet exceeded the reset pulse, the comparator output signal immediately disappears with the reset pulse so that it is immediately triggered again and the comparator output signal likewise. The forward flank of this newly triggered comparator output signal now appears, while the first reset pulse, after its delay by the delay link, appears at the D input of the D flip flop. This is therefore tilted to indicate too little alternating signal. However, as soon as the instantaneous value of the alternating signal 25 falls below the reference potential in the next half-wave, the D-flip flop is again reversed. It therefore changes its state with each half-wave of the too small alternating signal. This unstable operation is in many cases undesirable, for example, when the limit value detector should affect a control process. After each half-wave, an error-free state is reported even though the error is still present. This can lead to strong regulatory fluctuations and a destruction of the regulated device. Smoothing the oscillations of the detector would again lead to an undesirable delay of the detector.

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The use of this limit value device also for square alternating signals with long pulse distances or for single-directional sinus signals (in addition to double-directional sinus signals) can lead to a response delay after 5 occurrence of too low voltage with a value corresponding to the reset pulse duration to be is selected according to the distance of the unidirectional single pulses.

Thus, for monitoring a smooth DC voltage, it is known (DE-OS 26 29 894) to connect a differential amplifier 10 in such a way that it works as a bistable comparator. This also causes the difficulties described in the introduction that the use of alternating signals requires a smoothing which delays the reaction time.

The object of the invention is to provide a limit value reporting device of the kind described in the preamble which, in a simple construction, can respond very quickly.

This task is solved according to the invention in that the unidirectional voltage consists of unloaded single pulses and that the comparator output is coupled by a first tipping step which immediately switches from the first to the second tipping state and tipping the switch from the first to the second potential. after switching from the second to the first potential after a first delay time, which is at least approximately equal to the time distance between consecutive single pulses.

When in this device the amplitude of the first single pulse exceeds the reference voltage, not only the comparator but also the first tipping step reacts. However, when the amplitude of the single pulse briefly falls below the reference voltage again, the toggle contact remains until the end of the first delay time in its second toggle state. These are repetitive pulses with too much amplitude, 4

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the delay time is constantly set. This means that the second tilting state is maintained until the amplitude of the single pulses has decreased again. Therefore, not only an immediate reaction is obtained, but also a stable operation. The reporting device is suitable for both square-shaped, single-directional or otherwise-continuous signals as well as for double-rectified sine signals, without the need for a matching to the current waveform to achieve a high reaction rate.

Therefore, it is enough if the first single-time delay time is approximately the period of the alternating signal. Thus, the feedback also takes place with less delay. An even shorter delay time of about half a period is probably double-directional, which, however, requires a significantly higher power consumption.

In order to obtain the first delay time, it is recommended between comparator and kip stage to connect an RC joint whose resistance is shunted by a diode. As the capacitor current flows across the resistor, the desired delay time is obtained. In the opposite direction, the resistor is shorted by the diode so that the capacitor almost immediately assumes the voltage at the comparator output.

Admittedly, it is of interest that the limit value device responds promptly; but often a certainty is desired that a message signal is not already emitted when a single noise pulse occurs. This is achieved by the first tipping step being followed by a second tipping step which follows the tipping of the first tipping step from the first to the second tipping state after a second delay time greater than the first delay time. In this way, noise signals whose duration is less than the difference between the two delay times cannot cause a triggering of the message signal.

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The second delay time should not be large either, but not more than roughly the duration of two periods. In this way, noise pulses over a period of time can be safely neglected. However, since noise pulses are generally 5 shorter, in practice it is enough to choose the second delay time only slightly longer than a period time.

To obtain the second delay time, an RC link may be coupled between the first and second tipping stages. This causes, in one tilt direction, the second delay time and in the other tilt direction a third delay time, which prevents premature interruption of the message signal due to a noise impulse.

Advantageously, the reference input over a first divider resistor is connected to an adjustable voltage and over a second divider resistor and an electronic contact controlled by the last state of the pivotal state is connected to the O-potential. This leads to a hysteresis-like change of the limit value, thereby avoiding a persistent forward and reverse feedback when the amplitude of the alternating signal oscillates negatively around the limit value.

In a preferred embodiment, the comparator in the first tipping state is provided to provide an I signal and in the second tipping condition an O signal that the first tipping step is an NAND link, one input of which is directly connected to 25 the comparator output, and if the second input across the parallel coupling of a resistor and a diode is connected to the comparator output and over a capacitor, is connected to 0-potential, the second bipart is a NAND link whose one input is connected to I-potential, and if a second input over 30 a resistor is connected to the output of the first tipping stage and over a capacitor is connected to O-potential, a third tipping step is provided in the form of a NAND joint, two inputs of which are connected to the output of the second tipping stage. , that on the 6th

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electronic switch is a transistor whose base across a resistor is connected to the output of the third tipping stage and that the message signal may be decreased at the output of the second and / or third tipping stage. The additional third tipping step ensures that the electronic switch is properly switched on and off and that the binary message signal can optionally be decreased in inverting form as well.

The invention will be explained in more detail below with the aid of an exemplary embodiment shown in the drawing which shows in FIG. 1 is a flow chart of the limit value device according to the invention; FIG. 2 shows in a diagram the hysteresis-like change of the limit value; FIG. 3 in several diagrams, the voltage course within the circuit and fig. 4 shows a compressor in a refrigeration system with capacity regulator which can be influenced by the limit value sensing device.

In the limit value device of FIG. 1, a motor torque I 1 is monitored. It flows through the primary winding of a transformer Tr, through whose secondary winding the secondary current Ig flows. One end of the secondary winding is on a line 10 with 0 potential, the other end is connected to the inverting or signal input of a comparator IC1 over a longitudinal resistor R1. In front of the longitudinal resistor there is a cross-resistance R2 with relatively low resistance value, e.g. 5 Ohm, behind it there is a diode D1. The secondary current Ig produces on the transverse resistor R2 an alternating voltage Vj / j, the negative part of which is rendered inactive over D1 and 30 Ri. R1 is thus chosen so that below the negative half- 7

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wave, the input current is still in the safe area. As a result, only the positive half-waves are available as single pulses Vg at the comparator IC1 signal input.

5 The non-inverting or reference input of comparator IC1, on the one hand, faces a resistor R3 in connection with the output of a potentiometer P, at which a limit voltage Vq is adjustable. Furthermore, the reference input is across a resistor R4 and a transistor T collector emitter stretch connected to the 10O potential of the line. As a result, depending on the switching state of the transistor T, two input voltages Vg are obtained, namely VE1 VG, VE2 = -— VG.

R3 + R4 b 15 The comparator IC1 output voltage VG has in the first tipping state, namely when the highest value of the voltage VM is lower than the input voltage Vg, i-potential and in the second tipping state when the highest value exceeds the input voltage VE, O-potential.

The comparator IC1 is connected by a first tipping stage IC2 in the form of a NAND link, the first input of which is directly connected to the comparator output, while its second input over the parallel connection of a resistor R5 and a diode D2 is connected to the comparator output and over a capacitor C1. 25 with line 10. As long as Vc = i, capacitor C1 is charged to I so that the two inputs of the tipping stage IC2 are at the high potential, so that the output voltage V (J1 = 0. becomes Vq * 0, then capacitor C1 is discharged practically ta - 8

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get immediately over D2. Thus Vg ^ = j. if Vq rises again to I, the capacitor C1 is gradually charged over the resistor R5 until the positive threshold voltage of the NAND joint is exceeded. This leads to a first delay time t1. Only 5 then V01 returns to 0.

There is a second tipping stage IC3, again in the form of a NAND link, one of which is connected to a line 11 which carries I potential, and whose second input over a resistor R6 is connected to the output of the first tipping stage IC2 and over a 10 capacitor C2 with the O-potential conducting line 10. Therefore, when Voi = 0, the voltage V02 = 1 is available at the output. If Vg-j increases to 1, then capacitor C2 is gradually charged over resistor R6. After a predetermined second delay time t2, the positive threshold value of the tipping stage IC3 is exceeded, and only then does Vg2 of 0. If V () 1 rises again to 0, then capacitor C2 is discharged over resistor R6. After a predetermined delay time t3, the negative threshold is lowered, and only then does the output signal V02 become I.

There follows a third tipping step IC4 in the form of a NAND link, which serves only as a reverse step. Its output signal V03 is accordingly a mirror signal signal V02. At V02, the 0 signal and at V03 I signal serve as a signal signal for an overcurrent.

The base of the transistor T is connected above a base resistor R7 to the output of the third tipping stage IC4. Each time an overcurrent is detected, the transistor T becomes conductive, thus reducing the input voltage VE of the comparator.

This can be seen in FIG. 2, where the output voltage V03 of the third tipping stage IC4 is shown above the maximum value of the measured voltage Vf / j. The comparator responds when inputs exceed the sword in Vjjji- Shortly thereafter, V03 = X and the transistor T becomes conductive. This leads to a reduction of

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9 the input voltage to VE2. That is, the measured voltage Vt amplitude must fall below this reduced value before Vq3 can again become 0.

The operation of the circuit is shown in fig. 3. In line I, respectively, the measurement voltage Vr0 and the single pulses Vg are shown as a function of time t. At the time a the voltage exceeds the input voltage VE1 which serves as a reference voltage. at this point, the comparator output voltage Vq from I goes to 0. At the same time, the first biphase IC2 output-10 output Vqi goes to I. At time b, V «falls below the value VEi and Vc again becomes I. However, due to R5, The -C1 joint does not immediately return, but only after a delay time t1, if it had remained in the I state for so long. However, this is not the case because already at time c the value VEi is exceeded again and thus Vq = 0. The capacitor C1 is therefore immediately discharged again and the delay time ten starts to run again at time d. A reversal of V01 to zero occurs only after the last reduction of the effective input voltage, here VE2, that is, the time e, namely after the delay time ten, ie at the time f. T.

Although one can already use the output voltage Vg ^ I signal as the overcurrent signal signal, the second tipping stage IC3 with the R6-C2 link is arranged to disable noise pulses, thereby switching the V02 ^ ra 1 to 0 only the delay time t2 later than at time a, that is, at time point g. When one assumes that the comparator's reaction between a and b did not occur due to an overcurrent, but due to a single noise pulse, then Voi would already at time h, t1 later than b, jump back to the 0 value. Since capacitor C2 is no longer charged, can

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Nor does the tipping step IC3 react. Its output voltage Vg2 thus retains its I value. No overcurrent message signal is output. It is clear that in this way all individual noise pulses whose duration is shorter than t2 -5 t1 are suppressed.

However, in the case of recurrent single pulses, the voltage Vgi i value also remains unchanged, and after the delay time t2, V02 goes to zero and V03 to I. The latter causes the reference input Vjji to be reduced 10 to V] j2 * This state is maintained until the output voltage Vgi of the first tipping stage IC2 at time f returns to 0. After the delay time t3, that is, at time i, the voltage Vg2 again assumes the I value and the voltage Vg3 the O value. This also makes the original reference voltage Vgi active again.

Since the noise voltage pulses of the measuring voltage are superimposed, not only can the positive noise pulses exceed a limit value, but the negative noise pulses can also pretend to be below the limit value. These negative noise pulses are similarly rendered inactive by the delay times t1 and t3, as was described for the positive noise pulses associated with the delay time t2.

This noise pulse suppression is especially important when the amplitude of the measurement voltage is in the range between V ^ 2 and 25 VB1, because the overlay of rather small noise pulses would then be enough to exceed the values mentioned downwards and upwards respectively.

FIG. 4 shows a preferred use of the limit value reporting device. An engine 12, which is supplied to power over a main contact 13 and 30 lines 14, drives a screw compressor 15 which sucks refrigerant from an evaporator 16 and transports it over a pressure line 17 to a capacitor, from which the refrigerant is again fed to the evaporator 11 after condensation.

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over a throttle site. Along the screw 18 of the screw compressor 15 is a slider movable which, when displaced to the right, shortens the effective length of the compressor 15 and thus reduces the transport performance. The slide 19 is set by a servo motor 5 20, which can be actuated by opening a valve 21 to the right (downward capacity) and by opening a valve 22 (upward capacity). Both valves are opened by means of a down contact element 23 and an up contact element 24, respectively, which is controlled by a signal generator 25. A temperature sensor 26 adjacent to the evaporator 16 gives the value of the temperature, a setting device 27 gives the desired setpoint of the temperature. Both are compared in a mixing device 28 such that the control deviation is passed to the signal transducer 25 over the signal line 29. As shown schematically in the signal transducer 15, when the control deviation exceeds a predetermined positive value, one contact element is magnetized and when the control deviation falls below a predetermined negative value. , the second contact element is magnetized. Therefore, the capacity of the compressor 15 is adjusted so that the desired temperature is adjusted to the evaporator 16.

Of the limit value device, the transformer Tr, the setting potentiometer P, comparator IC1 and the other coupling components summarized in a block 30 are shown schematically only. The output voltage V03 # which shortly after the occurrence of the "25 overcurrent assumes a high potential, is applied to the down contact element 23, which is independently magnetized by the signal transducer 25, and the valve 21 opens. As a result, the slider 19 is shifted to the right and the compressor's transport performance decreases, thereby reducing the load of the motor 12 and thus the motor current 1¾. Once the overcurrent has been removed in this way, the capacity regulator operates again depending on the signal transducer. 25th

12

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As can be seen from the reference characters of the comparator and the three tipping steps, these parts may be designed as integrated contact circuits.

Claims (8)

A threshold signal device for alternating signals with a comparator (IC1), whose signal input is applied to the alternating signal as unidirectional voltage (Vs), and whose reference input is applied to a limit value determining reference DC voltage and whose output exceeds the limit value to form a message signal switches from a first potential to a second potential and switches back again by below the limit value, characterized in that the unidirectional voltage (Vg) consists of unglazed single pulses and that the comparator output is switched on by a first kip stage (IC2), as at the change from the first to the second potential immediately kicks from the first to the second tipping state and kicks back at the change from the second to the first potential after a first delay time (ti), which is at least approximately equal to the time distance (T ) between consecutive single-hour pulses (VS). Device according to claim 1, characterized in that, in single-directional fashion, the time delay (t1) of the first delay is approximately the period time (t) of the alternating signal. Device according to claim 1 or 2, characterized in that to obtain the first delay time (t1), an RC link (R5, C1) is coupled between comparator (IC1) and first tipping step 25 (IC2), the resistance of which is shunted by a diode (D2). Device according to one of claims 1-3, characterized in that the first tipping step (IC2) is coupled to a second tipping step (IC3), which follows the tipping of the first tipping step from the first to the second state. after a second delay time (t2) greater than the first delay time (t1). Device according to Claim 4, characterized in that the second delay time (t2) does not exceed approximately two periods in time. Device according to claim 4 or 5, characterized in that to obtain the second delay time (t2), an RC link (R6, C2) is coupled between the first and second tipping steps (IC2, IC3). Device according to one of claims 1-6, characterized in that the reference input is connected to an adjustable voltage (VG) and to a second divider resistor (R4) and to one of the last tilting stages (IC4) of the reference state over a first divider resistance (R3). controlled electronic switch (T) is connected to O potential. Device according to one of Claims 1 to 7, characterized in that the comparator (IC1) in the first tipping state gives an I-signal and in the second tipping state an O-signal, that the first tipping step (IC2) is a NAND-20. wires whose one input is directly connected together are similar to the output and the other input over the parallel connection of a resistor (R5) and a diode (D2) is connected to the comparator output and over a capacitor (C1) is connected to the O potential second tipping step 25 (IC3) is a NAND joint whose one input is connected to I potential and whose second input via a resistor (R6) is connected to the output of the first tipping step and via a capacitor (C2) is connected to O potential a third tipping step (IC4) is provided in the form of a 30 NAND link, two inputs of which are connected to the output of the second tipping step, that the electronic switch (T) is a transistor whose base is across a resistor (R7) is junction DK 159336B it is at the output of the third tipping step and the message signal can be decreased at the end of the second and / or third tipping steps.