DK138296A - Method and circuit for generating a system clock signal - Google Patents

Method and circuit for generating a system clock signal

Info

Publication number
DK138296A
DK138296A DK138296A DK138296A DK138296A DK 138296 A DK138296 A DK 138296A DK 138296 A DK138296 A DK 138296A DK 138296 A DK138296 A DK 138296A DK 138296 A DK138296 A DK 138296A
Authority
DK
Denmark
Prior art keywords
generating
circuit
clock signal
system clock
signal
Prior art date
Application number
DK138296A
Other languages
Danish (da)
Inventor
Ole Rassing Andersen
Original Assignee
Dsc Communications As
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsc Communications As filed Critical Dsc Communications As
Priority to DK138296A priority Critical patent/DK138296A/en
Priority to PCT/DK1997/000547 priority patent/WO1998025366A1/en
Priority to AU51172/98A priority patent/AU5117298A/en
Publication of DK138296A publication Critical patent/DK138296A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DK138296A 1996-12-04 1996-12-04 Method and circuit for generating a system clock signal DK138296A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DK138296A DK138296A (en) 1996-12-04 1996-12-04 Method and circuit for generating a system clock signal
PCT/DK1997/000547 WO1998025366A1 (en) 1996-12-04 1997-12-02 A method and a circuit for generating a system clock signal
AU51172/98A AU5117298A (en) 1996-12-04 1997-12-02 A method and a circuit for generating a system clock signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DK138296A DK138296A (en) 1996-12-04 1996-12-04 Method and circuit for generating a system clock signal

Publications (1)

Publication Number Publication Date
DK138296A true DK138296A (en) 1998-06-05

Family

ID=8104257

Family Applications (1)

Application Number Title Priority Date Filing Date
DK138296A DK138296A (en) 1996-12-04 1996-12-04 Method and circuit for generating a system clock signal

Country Status (3)

Country Link
AU (1) AU5117298A (en)
DK (1) DK138296A (en)
WO (1) WO1998025366A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9114841D0 (en) * 1991-07-10 1991-08-28 Gpt Ltd Sdh data transmission timing
EP0718995A1 (en) * 1994-12-20 1996-06-26 International Business Machines Corporation Apparatus and method for synchronizing clock signals for digital links in a packet switching mode

Also Published As

Publication number Publication date
WO1998025366A1 (en) 1998-06-11
AU5117298A (en) 1998-06-29

Similar Documents

Publication Publication Date Title
EP0707381A3 (en) Circuit and method for generating a clock signal
DK13195A (en) Television signal distribution method and system
DE69535087D1 (en) Circuit arrangement for clock recovery
DK0628230T3 (en) System and method for multiplexing data transmissions
DE69737171D1 (en) Circuit for clock recovery
DK0880752T3 (en) Method and system for determining an object's contact point on a screen
DK0625586T3 (en) Structural element and method for making this
DK0913708T3 (en) Electromagnetic signal acquisition apparatus and method for using the same
DE69835190D1 (en) Circuit for clock recovery
FR2764092B1 (en) DEVICE FOR GENERATING A CLOCK SIGNAL AND METHOD FOR IMPLEMENTING IT
DK138196A (en) Method and circuit for generating a system clock signal
DK0749677T3 (en) Method for obtaining data
DE69717401D1 (en) Circuit and method for generating clock signals
DK0515376T3 (en) Method and arrangement for clock recovery
DE69422078D1 (en) Circuit and method for synchronizing clock signals
DK0820384T3 (en) Method and apparatus for making a stencil
DK138296A (en) Method and circuit for generating a system clock signal
DK0612410T3 (en) Method for sensing a jittered signal
DK0941589T3 (en) Method and circuit for generating a system clock signal
DK0943193T3 (en) Method and circuit for generating a central clock signal
NO952599D0 (en) Stopwatch and clock system
KR970004866A (en) Digital Signal Delay Method and Circuit
DK82595A (en) Method and circuit for signal synthesis
DE59702607D1 (en) CLOCK SIGNAL GENERATOR
GB2309841B (en) Circuit and method for generating a clock signal

Legal Events

Date Code Title Description
AHB Application shelved due to non-payment