DK0412575T3 - Filling decision circuit - Google Patents

Filling decision circuit

Info

Publication number
DK0412575T3
DK0412575T3 DK90116389.9T DK90116389T DK0412575T3 DK 0412575 T3 DK0412575 T3 DK 0412575T3 DK 90116389 T DK90116389 T DK 90116389T DK 0412575 T3 DK0412575 T3 DK 0412575T3
Authority
DK
Denmark
Prior art keywords
bit rate
decision circuit
stuffing
decision
stuffing decision
Prior art date
Application number
DK90116389.9T
Other languages
Danish (da)
Inventor
Miguel Dr Ing Robledo
Ralph Dipl-Ing Urbansky
Original Assignee
Philips Patentverwaltung
Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Patentverwaltung, Philips Electronics Nv filed Critical Philips Patentverwaltung
Application granted granted Critical
Publication of DK0412575T3 publication Critical patent/DK0412575T3/en

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/07Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Supplying Of Containers To The Packaging Station (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Manipulation Of Pulses (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
  • Basic Packing Technique (AREA)
  • Circuits Of Receivers In General (AREA)
  • Television Systems (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)

Abstract

A stuffing decision circuit is described which is used in an arrangement for the bit rate adaptation of two signals. It is necessary for the application of the stuffing decision circuit according to the invention that the signal with the higher bit rate is structured in accordance with frames and at least one stuffing decision must be made for each frame. To make the so-called waiting time jitter, which becomes noticeable during the recovery of the signal with the lower bit rate at the receiving end, largely removable, means are provided by means of which the time of the stuffing decision is randomly or pseudorandomly shifted by times which are short compared with one frame length. Due to this modulation of the decision time, the low-frequency jitter otherwise occurring is transformed into higher frequencies and can be easily filtered out by means of a phase-locked loop at the receiving end.
DK90116389.9T 1989-08-09 1990-08-09 Filling decision circuit DK0412575T3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3926251A DE3926251A1 (en) 1989-08-09 1989-08-09 STOP DECISION CIRCUIT

Publications (1)

Publication Number Publication Date
DK0412575T3 true DK0412575T3 (en) 1996-05-13

Family

ID=6386763

Family Applications (1)

Application Number Title Priority Date Filing Date
DK90116389.9T DK0412575T3 (en) 1989-08-09 1990-08-09 Filling decision circuit

Country Status (6)

Country Link
EP (1) EP0412575B1 (en)
AT (1) ATE132677T1 (en)
DE (2) DE3926251A1 (en)
DK (1) DK0412575T3 (en)
ES (1) ES2083987T3 (en)
GR (1) GR3019524T3 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4108429A1 (en) * 1991-03-15 1992-09-17 Philips Patentverwaltung TRANSMISSION SYSTEM FOR THE DIGITAL SYNCHRONOUS HIERARCHY
DE4110933A1 (en) * 1991-04-04 1992-10-08 Philips Patentverwaltung TRANSMISSION SYSTEM FOR THE SYNCHRONOUS DIGITAL HIERACHIE
ITMI20051286A1 (en) * 2005-07-08 2007-01-09 Alcatel Italia DEVICE AND METHOD FOR MAPPING AND DEMAPPING IN TRIBUTE DISTRIBUTION SIGNAL

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3173087D1 (en) * 1980-03-10 1986-01-16 Nec Corp Stuff synchronization device with reduced sampling jitter
JPS57212842A (en) * 1981-06-25 1982-12-27 Nec Corp Pulse stuff synchronizing device
JPS61224740A (en) * 1985-03-29 1986-10-06 Fujitsu Ltd Stuff synchronizing system

Also Published As

Publication number Publication date
GR3019524T3 (en) 1996-07-31
ES2083987T3 (en) 1996-05-01
DE3926251A1 (en) 1991-02-14
EP0412575A3 (en) 1992-03-25
DE59010029D1 (en) 1996-02-15
ATE132677T1 (en) 1996-01-15
EP0412575B1 (en) 1996-01-03
EP0412575A2 (en) 1991-02-13

Similar Documents

Publication Publication Date Title
DE69130046T2 (en) Frequency synthesizer with PLL, which enables a frequency change of the output at high speed
GB1532755A (en) Miller-encoded message decoder
DE69034026T2 (en) Clock jitter correction circuits for regenerating clock signals with jitter
DK0412575T3 (en) Filling decision circuit
US4996444A (en) Clock recovery circuit
DE3854584T2 (en) Error correcting device at the jitter reversal point and method therefor.
IT8320135A0 (en) RESONATOR CIRCUIT FOR AN OSCILLATION DATA STREAM EXTRACTION SYSTEM AT TIMING FREQUENCY.
DE59010111D1 (en) Procedure for switching multiplex signals via cross connectors
SE8802733D0 (en) MODULATION AND DEMODULATION DEVICE
KR100276742B1 (en) Frequency Control System of EFM Signal Frame Period Detection Circuit and Bit Synchronization Clock Signal for EFM Signal Regeneration
US4837782A (en) CMI decoder
NO902663L (en) PROCEDURE AND CLUTCH DEVICE FOR PHASIFICALLY REGENERATING A TASK SIGNAL.
EP0264035A3 (en) Phase comparator, especially for a phase-locked loop
AU5643296A (en) Padding process for plesiochronous data transmission (ii)
SE8501803L (en) SET AND DEVICE FOR PHASING A CONTROLLED OSCILLATOR'S SIGNAL TO A REFERENCE Oscillator SIGNAL
FR2544771B1 (en) DEVICE FOR THE PLACEMENT, REMOVAL OR ESTABLISHMENT OF AT LEAST ONE FLEXIBLE SCREEN
ATE257990T1 (en) SERIAL FREQUENCY CONVERTER WITH TOLERANCE OF JITTER ON THE PAYLOAD
KR900702709A (en) Voice signal demodulation circuit
DE59008700D1 (en) Synchronizer for a digital signal.
FR2559331B1 (en) METHOD AND CIRCUIT FOR THE PRODUCTION OF PULSES FOR A PAL OR SECAM ENCODER OR DECODER
IT8622286A0 (en) PROCEDURE FOR THE REFINING OF COAL BY MEANS OF SELECTIVE AGGLOMERATING.
DE69721183D1 (en) Digital signal reproduction
CA1298357C (en) Clock recovery circuit
DE3679351D1 (en) CIRCUIT ARRANGEMENT FOR RECOVERY OF THE CLOCK OF AN ISOCHRONOUS BINARY SIGNAL.
FR2553606B1 (en) DEVICE FOR IMPROVING THE HIGH FREQUENCY OPERATION OF LOGIC INTEGRATED CIRCUITS, ESPECIALLY OF THE ECL FAMILY