DE7130329U - Electrical conductor arrangement - Google Patents
Electrical conductor arrangementInfo
- Publication number
- DE7130329U DE7130329U DE7130329U DE7130329U DE7130329U DE 7130329 U DE7130329 U DE 7130329U DE 7130329 U DE7130329 U DE 7130329U DE 7130329 U DE7130329 U DE 7130329U DE 7130329 U DE7130329 U DE 7130329U
- Authority
- DE
- Germany
- Prior art keywords
- block
- conductor
- surface side
- arrangement according
- electrical conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 title claims description 45
- 239000011810 insulating material Substances 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/02—Arrangements of circuit components or wiring on supporting structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/0919—Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10439—Position of a single component
- H05K2201/10446—Mounted on an edge
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Led Device Packages (AREA)
- Multi-Conductor Connections (AREA)
- Connections By Means Of Piercing Elements, Nuts, Or Screws (AREA)
Description
DEUTSCHE ITT INDUSTRIES GESELLSCHAFT MIT BESCHRÄNKTER HAFTUNGDEUTSCHE ITT INDUSTRIES GESELLSCHAFT LIMITED LIABILITY
FREIBURG I.B.FREIBURG I.B.
Elektrische LeiteranordnungElectrical conductor arrangement
Die Priorität der Anmeldung vom 13. August 1970 in Großbritannien wird in Anspruch genommen.The priority of the application dated August 13, 1970 in Great Britain is used.
Die Erfindung betrifft eine elektrische Leiteranordnung mit Kontaktierungsflachen für elektrische Bauelemente. Sie ist erfindungsgemäß gekennzeichnet durch eine Mehrzahl von parallel im Abstand zueinander in einem Block aus Isoliermaterial angeordneten Leiterschichten, deren Kontaktierungsflächen an den Enden der Leiterschichten an wenigstens einer ersten Oberflächenseite des Blockes in einer Normalfläche zur Fläche der Leiterschichten freigelegt sind.The invention relates to an electrical conductor arrangement with contacting surfaces for electrical components. It is characterized according to the invention by a plurality of parallel spaced conductor layers in a block of insulating material , the contacting surfaces of which are exposed at the ends of the conductor layers on at least a first surface side of the block in a normal area to the surface of the conductor layers.
Ein bevorzugtes Ausführungsbeispiel der Erfindung wird im folgenden anhand der Zeichnung erläutert, in derA preferred embodiment of the invention is explained below with reference to the drawing, in which
die Fig. 1Fig. 1
eine perspektivische Ansicht einer teilweise verdrahteten elektrischen Schaltungsanordnung mit einer elektrischen Leiteranordnung nach der Erfindung unda perspective view of a partially wired electrical circuit arrangement with an electrical conductor arrangement according to the invention and
-2--2-
713032910.10.74713032910.10.74
R.B.W.Cooke et al 13-3 Fl 679R.B.W. Cooke et al 13-3 Fl 679
die Fig. 2 eine perspektivische Teilansicht einer Leiterschicht mit einer Mehrzahl von Leiusrsügsft veranschaulichen.Fig. 2 is a perspective partial view of a conductor layer with a plurality of Illustrate Leiusrsügsft.
Ein Block 1 aus elektrisch isolierendem Material enthält eine Mehrzahl von parallel im Abstand zueinander angeordneten Leiterschichten 2, bestehend aus je einem profilierten Leiterzug mit einem in Längsrichtung innerhalb des Blockes erstreckenden verbindenden Leiterzug 3 und mit sich senkrecht zum verbindenden Leiterzug 3 im Abstand vor einander erstreckenden Leiterteilen 4, welche an dar Frontfläche 5 des Blockes 1 unter Bildung von in Kolonnen angeordneten Kontaktierungsflachen 6 fluchtend enden.A block 1 of electrically insulating material contains a plurality of parallel spaced conductor layers 2, each consisting of a profiled conductor run with a connecting conductor run 3 extending in the longitudinal direction within the block and with si ch perpendicular to the connecting conductor run 3 at a distance from each other Conductor parts 4 which end in alignment on the front surface 5 of the block 1, forming contacting surfaces 6 arranged in columns.
Jeder der verbindenden Leiterzüge 3 weist einen weiteren einzelnen Laschenleiter 7 auf, der sich senkrecht zu ersteren und entgegengesetzt zu den Leiterteilen 4 erstreckt, um sich über die rückwärtige Oberflächenseite 8 des Blockes zu erheben.Each of the connecting conductor tracks 3 has a further individual tab conductor 7 which is perpendicular to the former and extends opposite to the conductor parts 4 in order to extend over the rear surface side 8 of the block to raise.
Aufeinanderfolgende Leiterschichten 2 haben ihre Laschenleiter 7 in unterschiedlichen Lagen zur Länge des verbindenden Leiterzuges 3 angeordnet, so daß die Laschenleiter 7 an der rückwärtigen Oberflächenseite 8 gestaffelt sind.Successive conductor layers 2 have their tab conductors 7 arranged in different positions to the length of the connecting conductor line 3, so that the tab conductor 7 on the rear surface side 8 are staggered.
Die Anzahl der Leiterschichten im Block sind gegeben durch die Anzahl der für jede Kolonne erforderlichen Kontaktierungsflächen. Beim vorliegenden Ausführungsbeispiel sind 35 derartige Leiterschichten, welche nicht alle gezeigt sind und je eine Dicke von 75 »um bei einer gleichmäßigen Dicke des Isoliermaterials zwischen benachbarten Leiterschichten aufweisen, vorhanden.The number of conductor layers in the block is given by the number of contact surfaces required for each column. In the present embodiment, there are 35 such conductor layers, all of which are not shown and each have a thickness of 75 »µm with a uniform thickness of the insulating material between adjacent conductor layers, available.
Wie die Figur 1 veranschaulicht, erhebt sich die vordere Oberflächenseite 5 des Blockes an jeder Kolonne der Kcntaktierungs-As Figure 1 illustrates, the front surface side rises 5 of the block at each column of the contact
7130329 io.io.74 -3-7130329 io.io.74 -3-
I » t · · · ·
1 · · · · ·
; I · · · · ·
I » · · ·
I ■ · · · ■ · I «I ·· · * · · ·
I »t · · · ·
1 · · · · ·
; I · · · · ·
I »· · ·
I ■ · · · ■ ·
darauf zu befeöuiyenden und zu kor.fcskti er enden Halbleiter-Festkörperschaltungen entspricht.semiconductor solid-state circuits to be fed and corrected is equivalent to.
Beim vorliegenden Ausführungsbeispiel sind die Festkörperschaltungen 10 Matrixen von 5x7 Lichtemissionsdioden, wobei jede Matrix am Rand 35 Anschlußflecken Il aufweist.In the present embodiment, the solid-state circuits are 10 matrices of 5x7 light emitting diodes, where each matrix at the edge 35 has pads II.
Jede Festkörperschaltung 10 ist an einem anderen abgesetzten Teil 9 angeordnet. Die einzelnen Drähte 12 werden irgendwie zwischen dem Anschlußflecken 13 und der passenden der Kontaktierungsflachen 8 befestigt. Eine automatische Verbindung ist erleichtert, da die zwei Sätze der Anschlüsse im wesentlichen in gleicher Ebene liegen.Each solid-state circuit 10 is arranged on a different remote part 9. The individual wires 12 are somehow fastened between the connection pad 13 and the matching one of the contacting surfaces 8. An automatic connection is facilitated because the two sets of connectors are substantially coplanar.
Die äußeren Verbindungen werden ar\ dem aus der rückwärtigen Oberflächenseite des Blockes 1 austretenden L^schenleiter 7 angebracht. Diese Laschenleiter 7 können auch fluchtend an der rückwärtigen Oberflächenseite 8 enden.The external connections are attached ar \ exiting from the rear surface side of the block 1 L ^ rule manager. 7 These tab conductors 7 can also end in alignment on the rear surface side 8.
7130329 ig.io.747130329 ig.io.74
Claims (8)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB38992/70A GB1278380A (en) | 1970-08-13 | 1970-08-13 | Electrical circuit assembly |
Publications (1)
Publication Number | Publication Date |
---|---|
DE7130329U true DE7130329U (en) | 1974-10-10 |
Family
ID=10406955
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE7130329U Expired DE7130329U (en) | 1970-08-13 | 1971-08-07 | Electrical conductor arrangement |
DE19712139613 Pending DE2139613A1 (en) | 1970-08-13 | 1971-08-07 | Electrical conductor arrangement |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19712139613 Pending DE2139613A1 (en) | 1970-08-13 | 1971-08-07 | Electrical conductor arrangement |
Country Status (3)
Country | Link |
---|---|
DE (2) | DE7130329U (en) |
GB (1) | GB1278380A (en) |
ZA (1) | ZA714478B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4237522A (en) * | 1979-06-29 | 1980-12-02 | International Business Machines Corporation | Chip package with high capacitance, stacked vlsi/power sheets extending through slots in substrate |
-
1970
- 1970-08-13 GB GB38992/70A patent/GB1278380A/en not_active Expired
-
1971
- 1971-07-07 ZA ZA714478A patent/ZA714478B/en unknown
- 1971-08-07 DE DE7130329U patent/DE7130329U/en not_active Expired
- 1971-08-07 DE DE19712139613 patent/DE2139613A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2139613A1 (en) | 1972-02-17 |
GB1278380A (en) | 1972-06-21 |
ZA714478B (en) | 1972-03-29 |
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