DE69923539D1 - Ein Mehrport-Speicher - Google Patents
Ein Mehrport-SpeicherInfo
- Publication number
- DE69923539D1 DE69923539D1 DE69923539T DE69923539T DE69923539D1 DE 69923539 D1 DE69923539 D1 DE 69923539D1 DE 69923539 T DE69923539 T DE 69923539T DE 69923539 T DE69923539 T DE 69923539T DE 69923539 D1 DE69923539 D1 DE 69923539D1
- Authority
- DE
- Germany
- Prior art keywords
- port storage
- port
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99410050A EP1050885B1 (de) | 1999-05-03 | 1999-05-03 | Ein Mehrport-Speicher |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69923539D1 true DE69923539D1 (de) | 2005-03-10 |
DE69923539T2 DE69923539T2 (de) | 2006-02-16 |
Family
ID=8242253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69923539T Expired - Fee Related DE69923539T2 (de) | 1999-05-03 | 1999-05-03 | Ein Mehrport-Speicher |
Country Status (3)
Country | Link |
---|---|
US (1) | US6718452B1 (de) |
EP (1) | EP1050885B1 (de) |
DE (1) | DE69923539T2 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040158695A1 (en) | 1999-05-03 | 2004-08-12 | Laurent Ugen | Method and apparatus for handling transfer of guarded instructions in a computer system |
US7139878B2 (en) * | 2003-06-20 | 2006-11-21 | Freescale Semiconductor, Inc. | Method and apparatus for dynamic prefetch buffer configuration and replacement |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4751671A (en) * | 1983-02-14 | 1988-06-14 | Prime Computer, Inc. | Size configurable data storage system |
US4847759A (en) * | 1985-03-18 | 1989-07-11 | International Business Machines Corp. | Register selection mechanism and organization of an instruction prefetch buffer |
US4817051A (en) * | 1987-07-02 | 1989-03-28 | Fairchild Semiconductor Corporation | Expandable multi-port random access memory |
US5134711A (en) * | 1988-05-13 | 1992-07-28 | At&T Bell Laboratories | Computer with intelligent memory system |
WO1992008230A1 (en) * | 1990-10-26 | 1992-05-14 | Micron Technology, Inc. | High-speed, five-port register file having simultaneous read and write capability and high tolerance to clock skew |
US5726584A (en) * | 1996-03-18 | 1998-03-10 | Xilinx, Inc. | Virtual high density programmable integrated circuit having addressable shared memory cells |
US5742557A (en) * | 1996-06-20 | 1998-04-21 | Northern Telecom Limited | Multi-port random access memory |
US6049863A (en) * | 1996-07-24 | 2000-04-11 | Advanced Micro Devices, Inc. | Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor |
JP2888206B2 (ja) * | 1996-08-30 | 1999-05-10 | 日本電気株式会社 | データ処理装置 |
EP0869430B1 (de) * | 1997-04-02 | 2005-11-30 | Matsushita Electric Industrial Co., Ltd. | FIFO-Speicher |
KR100307626B1 (ko) * | 1998-08-31 | 2001-11-30 | 윤종용 | 디램과버퍼메모리를갖는메모리로직복합집적회로장치 |
-
1999
- 1999-05-03 EP EP99410050A patent/EP1050885B1/de not_active Expired - Lifetime
- 1999-05-03 DE DE69923539T patent/DE69923539T2/de not_active Expired - Fee Related
-
2000
- 2000-05-02 US US09/563,610 patent/US6718452B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1050885A1 (de) | 2000-11-08 |
DE69923539T2 (de) | 2006-02-16 |
EP1050885B1 (de) | 2005-02-02 |
US6718452B1 (en) | 2004-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |