DE69901910T2 - Verfahren und gerät zur rechnung von indirekten verzweigungszieladressen - Google Patents

Verfahren und gerät zur rechnung von indirekten verzweigungszieladressen

Info

Publication number
DE69901910T2
DE69901910T2 DE69901910T DE69901910T DE69901910T2 DE 69901910 T2 DE69901910 T2 DE 69901910T2 DE 69901910 T DE69901910 T DE 69901910T DE 69901910 T DE69901910 T DE 69901910T DE 69901910 T2 DE69901910 T2 DE 69901910T2
Authority
DE
Germany
Prior art keywords
branch
instruction
address
fetch
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69901910T
Other languages
German (de)
English (en)
Other versions
DE69901910D1 (de
Inventor
S. Roberts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69901910D1 publication Critical patent/DE69901910D1/de
Publication of DE69901910T2 publication Critical patent/DE69901910T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69901910T 1998-09-21 1999-04-02 Verfahren und gerät zur rechnung von indirekten verzweigungszieladressen Expired - Fee Related DE69901910T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/157,721 US6279106B1 (en) 1998-09-21 1998-09-21 Method for reducing branch target storage by calculating direct branch targets on the fly
PCT/US1999/007266 WO2000017745A1 (en) 1998-09-21 1999-04-02 Method for calculating indirect branch targets

Publications (2)

Publication Number Publication Date
DE69901910D1 DE69901910D1 (de) 2002-07-25
DE69901910T2 true DE69901910T2 (de) 2003-02-13

Family

ID=22564987

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69901910T Expired - Fee Related DE69901910T2 (de) 1998-09-21 1999-04-02 Verfahren und gerät zur rechnung von indirekten verzweigungszieladressen

Country Status (6)

Country Link
US (1) US6279106B1 (enExample)
EP (1) EP1116102B1 (enExample)
JP (1) JP3871883B2 (enExample)
KR (1) KR20010075258A (enExample)
DE (1) DE69901910T2 (enExample)
WO (1) WO2000017745A1 (enExample)

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US6651162B1 (en) * 1999-11-04 2003-11-18 International Business Machines Corporation Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache
US6609194B1 (en) * 1999-11-12 2003-08-19 Ip-First, Llc Apparatus for performing branch target address calculation based on branch type
US6640297B1 (en) * 2000-06-19 2003-10-28 Transmeta Corporation Link pipe system for storage and retrieval of sequences of branch addresses
US7165168B2 (en) * 2003-01-14 2007-01-16 Ip-First, Llc Microprocessor with branch target address cache update queue
US7134005B2 (en) * 2001-05-04 2006-11-07 Ip-First, Llc Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte
US6886093B2 (en) * 2001-05-04 2005-04-26 Ip-First, Llc Speculative hybrid branch direction predictor
US6895498B2 (en) * 2001-05-04 2005-05-17 Ip-First, Llc Apparatus and method for target address replacement in speculative branch target address cache
US7200740B2 (en) * 2001-05-04 2007-04-03 Ip-First, Llc Apparatus and method for speculatively performing a return instruction in a microprocessor
US20020194461A1 (en) * 2001-05-04 2002-12-19 Ip First Llc Speculative branch target address cache
US7707397B2 (en) * 2001-05-04 2010-04-27 Via Technologies, Inc. Variable group associativity branch target address cache delivering multiple target addresses per cache line
US7165169B2 (en) * 2001-05-04 2007-01-16 Ip-First, Llc Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
US7234045B2 (en) * 2001-07-03 2007-06-19 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US7203824B2 (en) * 2001-07-03 2007-04-10 Ip-First, Llc Apparatus and method for handling BTAC branches that wrap across instruction cache lines
US6823444B1 (en) * 2001-07-03 2004-11-23 Ip-First, Llc Apparatus and method for selectively accessing disparate instruction buffer stages based on branch target address cache hit and instruction stage wrap
US7162619B2 (en) * 2001-07-03 2007-01-09 Ip-First, Llc Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer
US20030088758A1 (en) * 2001-11-08 2003-05-08 Matthew Becker Methods and systems for determining valid microprocessor instructions
US6948053B2 (en) * 2002-02-25 2005-09-20 International Business Machines Corporation Efficiently calculating a branch target address
US7159097B2 (en) * 2002-04-26 2007-01-02 Ip-First, Llc Apparatus and method for buffering instructions and late-generated related information using history of previous load/shifts
US7533382B2 (en) * 2002-10-30 2009-05-12 Stmicroelectronics, Inc. Hyperprocessor
US7143269B2 (en) * 2003-01-14 2006-11-28 Ip-First, Llc Apparatus and method for killing an instruction after loading the instruction into an instruction queue in a pipelined microprocessor
US7152154B2 (en) * 2003-01-16 2006-12-19 Ip-First, Llc. Apparatus and method for invalidation of redundant branch target address cache entries
US7185186B2 (en) * 2003-01-14 2007-02-27 Ip-First, Llc Apparatus and method for resolving deadlock fetch conditions involving branch target address cache
US7178010B2 (en) * 2003-01-16 2007-02-13 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that detects from multiple pipeline stages incorrect speculative update of the call/return stack
US7743238B2 (en) * 2003-05-09 2010-06-22 Arm Limited Accessing items of architectural state from a register cache in a data processing apparatus when performing branch prediction operations for an indirect branch instruction
US7237098B2 (en) * 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US7487334B2 (en) * 2005-02-03 2009-02-03 International Business Machines Corporation Branch encoding before instruction cache write
US7409535B2 (en) * 2005-04-20 2008-08-05 International Business Machines Corporation Branch target prediction for multi-target branches by identifying a repeated pattern
US7844807B2 (en) * 2008-02-01 2010-11-30 International Business Machines Corporation Branch target address cache storing direct predictions
US7865705B2 (en) * 2008-02-01 2011-01-04 International Business Machines Corporation Branch target address cache including address type tag bit
US20110078425A1 (en) * 2009-09-25 2011-03-31 Shah Manish K Branch prediction mechanism for predicting indirect branch targets
US20110093658A1 (en) * 2009-10-19 2011-04-21 Zuraski Jr Gerald D Classifying and segregating branch targets
ES2640272T3 (es) 2011-11-23 2017-11-02 Basf Se Aglutinante acuoso para sustratos granulados y/o fibrosos
CN103513958B (zh) * 2012-06-27 2017-01-25 上海芯豪微电子有限公司 高性能指令缓存系统和方法
US9317293B2 (en) 2012-11-28 2016-04-19 Qualcomm Incorporated Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media
US20140250289A1 (en) * 2013-03-01 2014-09-04 Mips Technologies, Inc. Branch Target Buffer With Efficient Return Prediction Capability
US9940262B2 (en) * 2014-09-19 2018-04-10 Apple Inc. Immediate branch recode that handles aliasing
US10936316B2 (en) 2015-09-19 2021-03-02 Microsoft Technology Licensing, Llc Dense read encoding for dataflow ISA
US11977891B2 (en) 2015-09-19 2024-05-07 Microsoft Technology Licensing, Llc Implicit program order
GB2573119A (en) * 2018-04-24 2019-10-30 Advanced Risc Mach Ltd Maintaining state of speculation

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62226232A (ja) 1986-03-28 1987-10-05 Toshiba Corp 分岐先アドレス算出回路
EP0253364A1 (de) 1986-07-16 1988-01-20 Siemens Aktiengesellschaft Verfahren und Schaltungsanordnung zur Bearbeitung von unbedingten Sprungbefehlen in nach dem Fliessbandprinzip arbeitenden Datenverarbeitungsanlagen
JP3494736B2 (ja) 1995-02-27 2004-02-09 株式会社ルネサステクノロジ 分岐先バッファを用いた分岐予測システム
US5995749A (en) * 1996-11-19 1999-11-30 Advanced Micro Devices, Inc. Branch prediction mechanism employing branch selectors to select a branch prediction
US6061786A (en) * 1998-04-23 2000-05-09 Advanced Micro Devices, Inc. Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction

Also Published As

Publication number Publication date
EP1116102A1 (en) 2001-07-18
JP2002525741A (ja) 2002-08-13
KR20010075258A (ko) 2001-08-09
US6279106B1 (en) 2001-08-21
EP1116102B1 (en) 2002-06-19
DE69901910D1 (de) 2002-07-25
WO2000017745A1 (en) 2000-03-30
JP3871883B2 (ja) 2007-01-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee