DE69838835D1 - Verfahren zur Prüfung und zur Darstellung einer Hardware durch Zerlegung und Aufteilung - Google Patents

Verfahren zur Prüfung und zur Darstellung einer Hardware durch Zerlegung und Aufteilung

Info

Publication number
DE69838835D1
DE69838835D1 DE69838835T DE69838835T DE69838835D1 DE 69838835 D1 DE69838835 D1 DE 69838835D1 DE 69838835 T DE69838835 T DE 69838835T DE 69838835 T DE69838835 T DE 69838835T DE 69838835 D1 DE69838835 D1 DE 69838835D1
Authority
DE
Germany
Prior art keywords
partitioning
decomposition
testing
displaying hardware
displaying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69838835T
Other languages
English (en)
Other versions
DE69838835T2 (de
Inventor
Jawahar Jain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69838835D1 publication Critical patent/DE69838835D1/de
Application granted granted Critical
Publication of DE69838835T2 publication Critical patent/DE69838835T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
DE69838835T 1997-11-05 1998-10-28 Verfahren zur Prüfung und zur Darstellung einer Hardware durch Zerlegung und Aufteilung Expired - Lifetime DE69838835T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/964,904 US6212669B1 (en) 1997-11-05 1997-11-05 Method for verifying and representing hardware by decomposition and partitioning
US964904 1997-11-05

Publications (2)

Publication Number Publication Date
DE69838835D1 true DE69838835D1 (de) 2008-01-24
DE69838835T2 DE69838835T2 (de) 2008-11-27

Family

ID=25509142

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69838835T Expired - Lifetime DE69838835T2 (de) 1997-11-05 1998-10-28 Verfahren zur Prüfung und zur Darstellung einer Hardware durch Zerlegung und Aufteilung

Country Status (4)

Country Link
US (4) US6212669B1 (de)
EP (1) EP0917073B1 (de)
JP (1) JP4028107B2 (de)
DE (1) DE69838835T2 (de)

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6212669B1 (en) 1997-11-05 2001-04-03 Fujitsu Limited Method for verifying and representing hardware by decomposition and partitioning
US6389374B1 (en) * 1998-06-03 2002-05-14 Fujitsu Limited OBDD variable ordering using sampling based schemes
US6473885B1 (en) * 1998-07-17 2002-10-29 Mentor Graphics Corporation Digital circuit layout techniques using circuit decomposition and pin swapping
US6360352B2 (en) * 1998-07-17 2002-03-19 David E. Wallace Digital circuit layout techniques
US6532440B1 (en) * 1998-10-16 2003-03-11 Fujitsu Limited Multiple error and fault diagnosis based on Xlists
US6397370B1 (en) * 1998-12-18 2002-05-28 Candence Design Systems, Inc. Method and system for breaking complex Boolean networks
US6408424B1 (en) * 1999-06-04 2002-06-18 Fujitsu Limited Verification of sequential circuits with same state encoding
US6484134B1 (en) * 1999-06-20 2002-11-19 Intel Corporation Property coverage in formal verification
GB2398901A (en) * 1999-06-20 2004-09-01 Intel Corp Coverage measurement of a formal verification property in which covered states cause the property to fail if the value of an observed signal is changed
US6959272B2 (en) * 1999-07-23 2005-10-25 Synopsys, Inc. Method and system for generating an ATPG model of a memory from behavioral descriptions
US6519660B1 (en) * 1999-09-28 2003-02-11 International Business Machines Corporation Method, system and program products for determining I/O configuration entropy
US6986137B1 (en) * 1999-09-28 2006-01-10 International Business Machines Corporation Method, system and program products for managing logical processors of a computing environment
US6745160B1 (en) * 1999-10-08 2004-06-01 Nec Corporation Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
US6536016B1 (en) * 2000-07-27 2003-03-18 Lsi Logic Corporation Method and apparatus for locating constants in combinational circuits
US6643827B1 (en) * 2000-09-30 2003-11-04 Intel Corporation Symbolic model checking with dynamic model pruning
US6587990B1 (en) * 2000-10-01 2003-07-01 Lsi Logic Corporation Method and apparatus for formula area and delay minimization
US6820244B2 (en) * 2001-02-09 2004-11-16 Sri International Methods for testing and programming nanoscale electronic devices
US6938223B2 (en) * 2001-02-15 2005-08-30 Zenasis Technologies, Inc. Logic circuit having a functionally redundant transistor network
US6567959B2 (en) * 2001-03-30 2003-05-20 Intel Corporation Method and device for verification of VLSI designs
US6912700B1 (en) * 2001-06-06 2005-06-28 The United States Of America As Represented By The National Security Agency Method and system for non-linear state based satisfiability
US7110525B1 (en) 2001-06-25 2006-09-19 Toby Heller Agent training sensitive call routing system
US6609234B2 (en) * 2001-06-29 2003-08-19 Intel Corporation Ordering binary decision diagrams used in the formal equivalence verification of digital designs
US7076407B2 (en) * 2001-08-24 2006-07-11 Wayne Biao Liu Space reduction in compositional state systems
US6698003B2 (en) * 2001-12-06 2004-02-24 International Business Machines Corporation Framework for multiple-engine based verification tools for integrated circuits
US20030115559A1 (en) * 2001-12-13 2003-06-19 International Business Machines Corporation Hardware validation through binary decision diagrams including functions and equalities
US6668362B1 (en) * 2002-01-09 2003-12-23 Synopsys, Inc. Hierarchical verification for equivalence checking of designs
US6701499B2 (en) * 2002-06-13 2004-03-02 Lsi Logic Corporation Effective approximated calculation of smooth functions
US8214421B2 (en) * 2002-06-17 2012-07-03 Ibm International Group Bv Conformance testing without reference implementation of an XML standard
US7058910B2 (en) * 2002-06-27 2006-06-06 The United States Of America As Represented By The Secretary Of The Navy Invariant checking method and apparatus using binary decision diagrams in combination with constraint solvers
US6792581B2 (en) * 2002-11-07 2004-09-14 Intel Corporation Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification
US6904578B2 (en) * 2002-11-13 2005-06-07 Fujitsu Limited System and method for verifying a plurality of states associated with a target circuit
US9818136B1 (en) 2003-02-05 2017-11-14 Steven M. Hoffberg System and method for determining contingent relevance
US7111270B2 (en) * 2003-02-26 2006-09-19 Intel Corporation Method and apparatus to adaptively validate a physical net routing topology of a substrate design
US6877141B2 (en) * 2003-04-01 2005-04-05 Fujitsu Limited Evaluating a validation vector for validating a network design
US7139929B2 (en) * 2003-04-01 2006-11-21 Fujitsu Limited Generating a test environment for validating a network design
US7168014B2 (en) * 2003-04-01 2007-01-23 Fujitsu Limited Propagating an error through a network
US7047510B1 (en) * 2003-04-23 2006-05-16 Cadence Design Systems, Inc. Method and system for partitioning an integrated circuit design
US7444274B1 (en) 2003-04-23 2008-10-28 Cadence Design Systems, Inc. Method and system for verifying circuit designs through propagation of assertions
US7571403B2 (en) * 2003-05-23 2009-08-04 Fujitsu Limited Circuit verification
US20050060790A1 (en) * 2003-09-24 2005-03-24 Chang Cho Three position headpiece
US7844924B2 (en) * 2003-11-19 2010-11-30 Kitakyushu Foundation For The Advancement Of Industry, Science And Technology Device for reducing the width of graph and a method to reduce the width of graph, and a device for logic synthesis and a method for logic synthesis
US7281225B2 (en) * 2003-11-20 2007-10-09 Fujitsu Limited Circuit verification using multiple engines
US7231615B2 (en) * 2003-12-08 2007-06-12 Cadence Design Systems, Inc. Methods and apparatus for transforming sequential logic designs into equivalent combinational logic
US7093218B2 (en) * 2004-02-19 2006-08-15 International Business Machines Corporation Incremental, assertion-based design verification
US7231619B1 (en) * 2004-03-03 2007-06-12 Marvell Semiconductor Israel Ltd. Extended model checking hardware verification
US7275224B2 (en) * 2004-04-02 2007-09-25 International Business Machines Corporation Method for providing an area optimized binary orthogonality checker
US7146589B1 (en) * 2004-08-23 2006-12-05 Synplicity, Inc. Reducing equivalence checking complexity using inverse function
US20060058989A1 (en) * 2004-09-13 2006-03-16 International Business Machines Corporation Symbolic model checking of generally asynchronous hardware
US7322016B2 (en) * 2005-01-11 2008-01-22 International Business Machines Corporation Impact checking technique
US7143374B1 (en) * 2005-03-01 2006-11-28 Hewlett-Packard Development Company, L.P. System and method for achieving analysis capacity for circuit analysis tools
US7506278B1 (en) 2005-03-08 2009-03-17 Xilinx, Inc. Method and apparatus for improving multiplexer implementation on integrated circuits
US7818793B2 (en) * 2005-03-23 2010-10-19 The Board Of Regents, University Of Texas System System and method of firewall design utilizing decision diagrams
US7350169B2 (en) * 2005-06-02 2008-03-25 International Business Machines Corporation Method and system for enhanced verification through structural target decomposition
US7343573B2 (en) * 2005-06-02 2008-03-11 International Business Machines Corporation Method and system for enhanced verification through binary decision diagram-based target decomposition
US7454738B2 (en) * 2005-06-10 2008-11-18 Purdue Research Foundation Synthesis approach for active leakage power reduction using dynamic supply gating
US7302655B2 (en) * 2005-06-14 2007-11-27 National Tsing Hua University Method for verifying a circuit design by assigning numerical values to inputs of the circuit design
US7340704B2 (en) * 2005-06-23 2008-03-04 International Business Machines Corporation Method and system for optimized automated case-splitting via constraints in a symbolic simulation framework
US7509597B1 (en) * 2005-06-30 2009-03-24 Altera Corporation Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams
US7693690B2 (en) * 2005-08-09 2010-04-06 Nec Laboratories America, Inc. Disjunctive image computation for sequential systems
US7555733B1 (en) * 2005-09-18 2009-06-30 Infinisim, Inc. Hierarchical partitioning
US7890896B2 (en) * 2005-11-18 2011-02-15 Synopsys, Inc. Method and apparatus for distinguishing combinational designs
US7877711B2 (en) * 2006-03-01 2011-01-25 Nangate A/S Methods of deriving switch networks
US7650579B2 (en) * 2006-05-25 2010-01-19 Freescale Semiconductor, Inc. Model correspondence method and device
US8171438B2 (en) * 2006-08-25 2012-05-01 International Business Machines Corporation Verification of a program partitioned according to the control flow information of the program
US7448008B2 (en) * 2006-08-29 2008-11-04 International Business Machines Corporation Method, system, and program product for automated verification of gating logic using formal verification
JP4241802B2 (ja) * 2006-10-27 2009-03-18 株式会社東芝 部品配置支援装置、方法およびプログラム
US20080109201A1 (en) * 2006-10-31 2008-05-08 Fujitsu Limited Disjunctive transition relation decomposition based verification
US7882473B2 (en) 2007-11-27 2011-02-01 International Business Machines Corporation Sequential equivalence checking for asynchronous verification
US8214780B2 (en) * 2008-08-27 2012-07-03 Intel Corporation Optimization of verification of chip design
US8195439B1 (en) 2008-09-02 2012-06-05 Infinisim, Inc. Real-time adaptive circuit simulation
US8862439B1 (en) * 2009-06-25 2014-10-14 Cadence Design Systems, Inc. General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software
US8812943B2 (en) * 2011-09-23 2014-08-19 Fujitsu Limited Detecting data corruption in medical binary decision diagrams using hashing techniques
US9075908B2 (en) * 2011-09-23 2015-07-07 Fujitsu Limited Partitioning medical binary decision diagrams for size optimization
US9177247B2 (en) * 2011-09-23 2015-11-03 Fujitsu Limited Partitioning medical binary decision diagrams for analysis optimization
US20130290919A1 (en) * 2012-04-27 2013-10-31 Synopsys, Inc. Selective execution for partitioned parallel simulations
US9275012B2 (en) 2013-06-11 2016-03-01 International Business Machines Corporation Multi-way number partitioning using weakest link optimality
CN107809235B (zh) * 2017-10-18 2021-03-26 浙江万里学院 用于转换规范rm逻辑电路的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5243538B1 (en) 1989-08-09 1995-11-07 Hitachi Ltd Comparison and verification system for logic circuits and method thereof
US5128871A (en) * 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5598344A (en) * 1990-04-06 1997-01-28 Lsi Logic Corporation Method and system for creating, validating, and scaling structural description of electronic device
US5555201A (en) * 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5377201A (en) 1991-06-18 1994-12-27 Nec Research Institute, Inc. Transitive closure based process for generating test vectors for VLSI circuit
US5349659A (en) 1992-01-23 1994-09-20 Cadence Design Systems, Inc. Hierarchical ordering of logical elements in the canonical mapping of net lists
US5528508A (en) 1993-02-19 1996-06-18 International Business Machines Corporation System and method for verifying a hierarchical circuit design
US5481473A (en) 1993-02-19 1996-01-02 International Business Machines Corporation System and method for building interconnections in a hierarchical circuit design
US5497334A (en) 1993-02-19 1996-03-05 International Business Machines Corporation Application generator for use in verifying a hierarchical circuit design
US5522063A (en) 1993-09-27 1996-05-28 Nec Usa, Inc. Method of finding minimum-cost feedback-vertex sets for a graph for partial scan testing without exhaustive cycle enumeration
US5485471A (en) 1993-10-15 1996-01-16 Mitsubishi Electric Research Laboratories, Inc. System for testing of digital integrated circuits
US5469367A (en) * 1994-06-06 1995-11-21 University Technologies International Inc. Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits
US5526514A (en) 1994-06-21 1996-06-11 Pradhan; Dhiraj Method for circuit verification and multi-level circuit optimization based on structural implications
DE4423367A1 (de) 1994-07-04 1996-07-25 Siemens Ag Verfahren zur hierarchischen Logik-Verifikation hochintegrierter Schaltungen
US5649165A (en) * 1995-01-31 1997-07-15 Fujitsu Limited Topology-based computer-aided design system for digital circuits and method thereof
JPH096821A (ja) 1995-04-21 1997-01-10 Hitachi Ltd 論理回路の合成方法、半導体装置の製造方法および二分決定グラフの最適化方法
US5805462A (en) * 1995-08-18 1998-09-08 Vlsi Technology, Inc. Automatic synthesis of integrated circuits employing boolean decomposition
US5680332A (en) * 1995-10-30 1997-10-21 Motorola, Inc. Measurement of digital circuit simulation test coverage utilizing BDDs and state bins
US5787006A (en) 1996-04-30 1998-07-28 Micron Technology, Inc. Apparatus and method for management of integrated circuit layout verification processes
US6086626A (en) * 1997-05-16 2000-07-11 Fijutsu Limited Method for verification of combinational circuits using a filtering oriented approach
US6212669B1 (en) 1997-11-05 2001-04-03 Fujitsu Limited Method for verifying and representing hardware by decomposition and partitioning
US6026222A (en) * 1997-12-23 2000-02-15 Nec Usa, Inc. System for combinational equivalence checking

Also Published As

Publication number Publication date
JPH11219378A (ja) 1999-08-10
US7673263B2 (en) 2010-03-02
EP0917073B1 (de) 2007-12-12
US20040015799A1 (en) 2004-01-22
US7028278B2 (en) 2006-04-11
US6212669B1 (en) 2001-04-03
DE69838835T2 (de) 2008-11-27
US6560758B1 (en) 2003-05-06
US20060129953A1 (en) 2006-06-15
JP4028107B2 (ja) 2007-12-26
EP0917073A3 (de) 2003-06-04
EP0917073A2 (de) 1999-05-19

Similar Documents

Publication Publication Date Title
DE69838835D1 (de) Verfahren zur Prüfung und zur Darstellung einer Hardware durch Zerlegung und Aufteilung
DE69501651D1 (de) System und Verfahren zur Darstellung von Bildern
DE69717965D1 (de) Verfahren und vorrichtung zur darstellung von objekten mittels fenstern
DE69420547T2 (de) Wellenform-mischungsverfahren für system zur text-zu-sprache umsetzung
DE69817634D1 (de) Vorrichtung und Verfahren zur Anzeige von Fenstern
DE69521575D1 (de) Verfahren und Anordnung zur Darstellung elektronischer Dokumente
DE69917978T2 (de) Vorrichtung und Verfahren zur Komplettierung einer unterirdischen Bohrung
DE69508381T2 (de) Verfahren zur bedrohungsvermeidungs für flugzeuge
DE69624590T2 (de) Klebhilfsmittel und verfahren zur darstellung von klebhilfsmittel
DE69327501D1 (de) Schallumgebungsimulator und Verfahren zur Schallfeldanalyse
DE69523530D1 (de) Vorrichtung und Verfahren zur graphischen Darstellung mathematischer Formeln
DE69535165D1 (de) Verfahren und Vorrichtung zur Bohrlochuntersuchung
DE69622961D1 (de) Verfahren und Vorrichtung zur Darstellung von Zeichen
DE69942434D1 (de) Verfahren und Vorrichtung für eine dreidimensionale Darstellung
DE59711373D1 (de) Verfahren und einrichtung zur darstellung von flugführungsinformation
DE59700716D1 (de) Verfahren zur Analyse und Darstellung von transienten Prozessvorgängen
DE69329316T2 (de) Gerät und Verfahren zur graphischer Darstellung von Flächen
DE69633736D1 (de) Verfahren und vorrichtung zur darstellung von aufzugsfunktionen
DE69427809D1 (de) Vorrichtung und Verfahren zur graphischen Darstellung
DE59801882D1 (de) Verfahren zur synchronisierten darstellung von netz-inhalten
DE69531777D1 (de) Verfahren zur darstellung von lithiumalkylamiden
DE69709871D1 (de) Verfahren zur darstellung von hydrocarbyl-bis(hydrocarbylphosphat)
DE59906702D1 (de) Automatisierungssystem und verfahren zum zugriff auf die funktionalität von hardwarekomponenten
DE69630763D1 (de) Multiplexbetriebene Vorrichtung zur Anzeige von Zeichen und Verfahren zur Darstellung hochdynamischer Ereignisse
DE69808961T2 (de) Verfahren zur darstellung von dicyclopentadien-polyetherestern

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE