DE69828900D1 - Verbindungslochkonfigurationzurunterstützung einer gleichmässigen übertragungsleitungsstruktur - Google Patents

Verbindungslochkonfigurationzurunterstützung einer gleichmässigen übertragungsleitungsstruktur

Info

Publication number
DE69828900D1
DE69828900D1 DE69828900T DE69828900T DE69828900D1 DE 69828900 D1 DE69828900 D1 DE 69828900D1 DE 69828900 T DE69828900 T DE 69828900T DE 69828900 T DE69828900 T DE 69828900T DE 69828900 D1 DE69828900 D1 DE 69828900D1
Authority
DE
Germany
Prior art keywords
support
transmission line
connecting hole
line structure
hole configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69828900T
Other languages
English (en)
Other versions
DE69828900T2 (de
Inventor
Michael Leddige
John Sprietsma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE69828900D1 publication Critical patent/DE69828900D1/de
Application granted granted Critical
Publication of DE69828900T2 publication Critical patent/DE69828900T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/044—Details of backplane or midplane for mounting orthogonal PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Structure Of Printed Boards (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
DE69828900T 1997-10-28 1998-08-20 Verbindungslochkonfigurationzurunterstützung einer gleichmässigen übertragungsleitungsstruktur Expired - Fee Related DE69828900T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US959244 1997-10-28
US08/959,244 US6111205A (en) 1997-10-28 1997-10-28 Via pad geometry supporting uniform transmission line structures
PCT/US1998/017397 WO1999022552A1 (en) 1997-10-28 1998-08-20 Via pad geometry supporting uniform transmission line structures

Publications (2)

Publication Number Publication Date
DE69828900D1 true DE69828900D1 (de) 2005-03-10
DE69828900T2 DE69828900T2 (de) 2006-01-12

Family

ID=25501830

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69828900T Expired - Fee Related DE69828900T2 (de) 1997-10-28 1998-08-20 Verbindungslochkonfigurationzurunterstützung einer gleichmässigen übertragungsleitungsstruktur

Country Status (7)

Country Link
US (1) US6111205A (de)
EP (1) EP1029431B1 (de)
AU (1) AU9113498A (de)
DE (1) DE69828900T2 (de)
HK (1) HK1028158A1 (de)
TW (1) TW389008B (de)
WO (1) WO1999022552A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429528B1 (en) * 1998-02-27 2002-08-06 Micron Technology, Inc. Multichip semiconductor package
US6950891B1 (en) * 1999-12-14 2005-09-27 Intel Corporation Signal routing between a memory control unit and a memory device
US20030011390A1 (en) * 2001-07-09 2003-01-16 Smith Douglas W. Interface apparatus for integrated circuit testing
US6870276B1 (en) * 2001-12-26 2005-03-22 Micron Technology, Inc. Apparatus for supporting microelectronic substrates
TW550991B (en) * 2002-02-06 2003-09-01 Via Tech Inc Multi-layered substrate having voltage reference signal circuit layout
US6875930B2 (en) * 2002-04-18 2005-04-05 Hewlett-Packard Development Company, L.P. Optimized conductor routing for multiple components on a printed circuit board
US7084354B2 (en) * 2002-06-14 2006-08-01 Intel Corporation PCB method and apparatus for producing landless interconnects
US7034544B2 (en) * 2003-06-30 2006-04-25 Intel Corporation Methods for minimizing the impedance discontinuity between a conductive trace and a component and structures formed thereby
US20060220167A1 (en) * 2005-03-31 2006-10-05 Intel Corporation IC package with prefabricated film capacitor
EP2235750A1 (de) * 2007-11-27 2010-10-06 Nxp B.V. Kontaktstruktur für ein elektronisches schaltungssubstrat und elektronische schaltung mit der kontaktstruktur
US9553040B2 (en) 2012-03-27 2017-01-24 Mediatek Inc. Semiconductor package
US10398025B2 (en) * 2017-11-09 2019-08-27 International Business Machines Corporation Peripheral end face attachment of exposed copper layers of a first printed circuit board to the surface of a second printed circuit board by surface mount assembly
US10321564B2 (en) 2017-11-09 2019-06-11 International Business Machines Corporation Solder assembly of pins to the peripheral end face of a printed circuit board
CN113079634B (zh) * 2020-05-29 2022-11-18 新华三技术有限公司合肥分公司 一种电路板及其制备工艺

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3033914A (en) * 1960-04-20 1962-05-08 Gen Electric Printed circuit boards
US3398232A (en) * 1965-10-19 1968-08-20 Amp Inc Circuit board with interconnected signal conductors and interconnected shielding conductors
GB1589519A (en) * 1976-11-19 1981-05-13 Solartron Electronic Group Printed circuits
IT211826Z2 (it) * 1987-09-15 1989-05-25 Microset Srl Scheda madre a circuito stampato per bus di microprocessori.
US5272600A (en) * 1992-09-02 1993-12-21 Microelectronics And Computer Technology Corporation Electrical interconnect device with interwoven power and ground lines and capacitive vias
US5764489A (en) * 1996-07-18 1998-06-09 Compaq Computer Corporation Apparatus for controlling the impedance of high speed signals on a printed circuit board

Also Published As

Publication number Publication date
US6111205A (en) 2000-08-29
HK1028158A1 (en) 2001-02-02
EP1029431B1 (de) 2005-02-02
TW389008B (en) 2000-05-01
EP1029431A4 (de) 2002-07-24
AU9113498A (en) 1999-05-17
WO1999022552A1 (en) 1999-05-06
EP1029431A1 (de) 2000-08-23
DE69828900T2 (de) 2006-01-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee