DE69813788D1 - Vidiografischer regler mit ver- und entriegelungsbetriebsmodus - Google Patents

Vidiografischer regler mit ver- und entriegelungsbetriebsmodus

Info

Publication number
DE69813788D1
DE69813788D1 DE69813788T DE69813788T DE69813788D1 DE 69813788 D1 DE69813788 D1 DE 69813788D1 DE 69813788 T DE69813788 T DE 69813788T DE 69813788 T DE69813788 T DE 69813788T DE 69813788 D1 DE69813788 D1 DE 69813788D1
Authority
DE
Germany
Prior art keywords
vidiographic
locking
controller
operating mode
unlocking operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69813788T
Other languages
English (en)
Other versions
DE69813788T2 (de
Inventor
Christopher Walsh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69813788D1 publication Critical patent/DE69813788D1/de
Publication of DE69813788T2 publication Critical patent/DE69813788T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
DE69813788T 1997-11-14 1998-10-12 Vidiografischer regler mit ver- und entriegelungsbetriebsmodus Expired - Lifetime DE69813788T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US970886 1997-11-14
US08/970,886 US5982397A (en) 1997-11-14 1997-11-14 Video graphics controller having locked and unlocked modes of operation
PCT/IB1998/001605 WO1999026145A2 (en) 1997-11-14 1998-10-12 Video graphics controller having locked and unlocked modes of operation

Publications (2)

Publication Number Publication Date
DE69813788D1 true DE69813788D1 (de) 2003-05-28
DE69813788T2 DE69813788T2 (de) 2004-02-12

Family

ID=25517661

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69813788T Expired - Lifetime DE69813788T2 (de) 1997-11-14 1998-10-12 Vidiografischer regler mit ver- und entriegelungsbetriebsmodus

Country Status (6)

Country Link
US (1) US5982397A (de)
EP (1) EP0974099B1 (de)
JP (1) JP2001508199A (de)
KR (1) KR20000070090A (de)
DE (1) DE69813788T2 (de)
WO (1) WO1999026145A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271866B1 (en) * 1998-12-23 2001-08-07 Honeywell International Inc. Dual port memory system for buffering asynchronous input to a raster scanned display
US6831647B1 (en) * 2000-09-28 2004-12-14 Rockwell Automation Technologies, Inc. Raster engine with bounded video signature analyzer
US7215339B1 (en) 2000-09-28 2007-05-08 Rockwell Automation Technologies, Inc. Method and apparatus for video underflow detection in a raster engine
US6817531B2 (en) * 2001-03-07 2004-11-16 Hewlett-Packard Development Company, L.P. Apparatus and methods for marking content of memory storage devices
US7650466B2 (en) * 2005-09-21 2010-01-19 Qualcomm Incorporated Method and apparatus for managing cache partitioning using a dynamic boundary
DE112010005418B4 (de) * 2010-03-25 2019-07-11 Nokia Technologies Oy Vorrichtung, Anzeigemodul und Verfahren zum anpassbaren Einfügen eines Leerrahmens
TW201237831A (en) * 2011-03-11 2012-09-16 Raydium Semiconductor Corp Liquid crystal display driver and display device having the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4454507A (en) * 1982-01-04 1984-06-12 General Electric Company Real-time cursor generator
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
US5097442A (en) * 1985-06-20 1992-03-17 Texas Instruments Incorporated Programmable depth first-in, first-out memory
US4706074A (en) * 1986-01-17 1987-11-10 International Business Machines Corporation Cursor circuit for a dual port memory
US5325487A (en) * 1990-08-14 1994-06-28 Integrated Device Technology, Inc. Shadow pipeline architecture in FIFO buffer
DE69124606T2 (de) * 1991-10-17 1997-08-21 Ibm Adaptive FIFO-Speichersteuerung
US5473756A (en) * 1992-12-30 1995-12-05 Intel Corporation FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers
US5682554A (en) * 1993-01-15 1997-10-28 Silicon Graphics, Inc. Apparatus and method for handling data transfer between a general purpose computer and a cooperating processor
US5717954A (en) * 1995-10-13 1998-02-10 Compaq Computer Corporation Locked exchange FIFO

Also Published As

Publication number Publication date
DE69813788T2 (de) 2004-02-12
EP0974099A2 (de) 2000-01-26
KR20000070090A (ko) 2000-11-25
WO1999026145A2 (en) 1999-05-27
WO1999026145A3 (en) 1999-07-29
JP2001508199A (ja) 2001-06-19
EP0974099B1 (de) 2003-04-23
US5982397A (en) 1999-11-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: EISENFUEHR, SPEISER & PARTNER, 10178 BERLIN

8327 Change in the person/name/address of the patent owner

Owner name: NXP B.V., EINDHOVEN, NL