DE69734945D1 - Speichersystem und Datenkommunikationssystem - Google Patents

Speichersystem und Datenkommunikationssystem

Info

Publication number
DE69734945D1
DE69734945D1 DE69734945T DE69734945T DE69734945D1 DE 69734945 D1 DE69734945 D1 DE 69734945D1 DE 69734945 T DE69734945 T DE 69734945T DE 69734945 T DE69734945 T DE 69734945T DE 69734945 D1 DE69734945 D1 DE 69734945D1
Authority
DE
Germany
Prior art keywords
data communication
communication system
storage system
storage
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69734945T
Other languages
English (en)
Other versions
DE69734945T2 (de
Inventor
Benjamin Rosen
Yaron Ben-Arie
Avi Ginsberg
Itzhak Barak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE69734945D1 publication Critical patent/DE69734945D1/de
Application granted granted Critical
Publication of DE69734945T2 publication Critical patent/DE69734945T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
DE69734945T 1996-02-09 1997-02-05 Speichersystem und Datenkommunikationssystem Expired - Fee Related DE69734945T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US599016 1996-02-09
US08/599,016 US5710944A (en) 1996-02-09 1996-02-09 Memory system and data communications system

Publications (2)

Publication Number Publication Date
DE69734945D1 true DE69734945D1 (de) 2006-02-02
DE69734945T2 DE69734945T2 (de) 2006-07-13

Family

ID=24397860

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69734945T Expired - Fee Related DE69734945T2 (de) 1996-02-09 1997-02-05 Speichersystem und Datenkommunikationssystem

Country Status (3)

Country Link
US (1) US5710944A (de)
EP (1) EP0789363B1 (de)
DE (1) DE69734945T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177322B2 (en) 2002-05-28 2007-02-13 International Business Machines Corporation Technique for controlling selection of a peek adapter or a read adapter from multiple adapters connected to a high speed switch
US7161954B2 (en) * 2002-05-28 2007-01-09 International Business Machines Corporation Technique for controlling selection of a write adapter from multiple adapters connected to a high speed switch

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3824551A (en) * 1972-05-18 1974-07-16 Little Inc A Releasable buffer memory for data processor
US4380798A (en) * 1980-09-15 1983-04-19 Motorola, Inc. Semaphore register including ownership bits
GB2140177B (en) * 1983-05-19 1986-09-17 Elwyn Rees Data entry interface assembly
JPH01191243A (ja) * 1988-01-26 1989-08-01 Mitsubishi Electric Corp マルチプロセツサシステムにおける共有メモリアクセス方式
FR2642214B1 (fr) * 1988-12-30 1992-11-20 Cit Alcatel Systeme de detection d'ecrasement de donnees dans une memoire tampon, notamment pour un commutateur de donnees
US5251310A (en) * 1990-06-29 1993-10-05 Digital Equipment Corporation Method and apparatus for exchanging blocks of information between a cache memory and a main memory
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
JP3293635B2 (ja) * 1990-12-27 2002-06-17 日本電気株式会社 チャネル装置
US5471602A (en) * 1992-07-31 1995-11-28 Hewlett-Packard Company System and method of scoreboarding individual cache line segments
US5586294A (en) * 1993-03-26 1996-12-17 Digital Equipment Corporation Method for increased performance from a memory stream buffer by eliminating read-modify-write streams from history buffer
US5510934A (en) * 1993-12-15 1996-04-23 Silicon Graphics, Inc. Memory system including local and global caches for storing floating point and integer data
US5553265A (en) * 1994-10-21 1996-09-03 International Business Machines Corporation Methods and system for merging data during cache checking and write-back cycles for memory reads and writes
US5544344A (en) * 1994-12-06 1996-08-06 Digital Equipment Corporation Apparatus for caching smram in an intel processor based computer system employing system management mode

Also Published As

Publication number Publication date
EP0789363A2 (de) 1997-08-13
EP0789363A3 (de) 2003-01-29
DE69734945T2 (de) 2006-07-13
EP0789363B1 (de) 2005-12-28
US5710944A (en) 1998-01-20

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee