DE69724353D1 - Mehrrechnersystem mit einem Drei-Sprung-Kommunikationsprotokoll - Google Patents

Mehrrechnersystem mit einem Drei-Sprung-Kommunikationsprotokoll

Info

Publication number
DE69724353D1
DE69724353D1 DE69724353T DE69724353T DE69724353D1 DE 69724353 D1 DE69724353 D1 DE 69724353D1 DE 69724353 T DE69724353 T DE 69724353T DE 69724353 T DE69724353 T DE 69724353T DE 69724353 D1 DE69724353 D1 DE 69724353D1
Authority
DE
Germany
Prior art keywords
computer system
communication protocol
hop communication
hop
protocol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69724353T
Other languages
English (en)
Other versions
DE69724353T2 (de
Inventor
Erik E Hagersten
Paul N Loewenstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69724353D1 publication Critical patent/DE69724353D1/de
Application granted granted Critical
Publication of DE69724353T2 publication Critical patent/DE69724353T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE69724353T 1996-07-01 1997-06-27 Mehrrechnersystem mit einem Drei-Sprung-Kommunikationsprotokoll Expired - Fee Related DE69724353T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/674,270 US5950226A (en) 1996-07-01 1996-07-01 Multiprocessing system employing a three-hop communication protocol
US674270 1996-07-01

Publications (2)

Publication Number Publication Date
DE69724353D1 true DE69724353D1 (de) 2003-10-02
DE69724353T2 DE69724353T2 (de) 2004-06-24

Family

ID=24705974

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69724353T Expired - Fee Related DE69724353T2 (de) 1996-07-01 1997-06-27 Mehrrechnersystem mit einem Drei-Sprung-Kommunikationsprotokoll

Country Status (4)

Country Link
US (1) US5950226A (de)
EP (1) EP0817074B1 (de)
JP (1) JPH10134014A (de)
DE (1) DE69724353T2 (de)

Families Citing this family (36)

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Publication number Priority date Publication date Assignee Title
US6341337B1 (en) * 1998-01-30 2002-01-22 Sun Microsystems, Inc. Apparatus and method for implementing a snoop bus protocol without snoop-in and snoop-out logic
EP1008940A3 (de) * 1998-12-07 2001-09-12 Network Virtual Systems Inc. Intelligenter und adaptiver Speicher und Verfahren und Vorrichtungen zur Verwaltung von verteilten Speichersystemen mit hardware-erzwungener Kohärenz
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US8635410B1 (en) 2000-07-20 2014-01-21 Silicon Graphics International, Corp. System and method for removing data from processor caches in a distributed multi-processor computer system
US6829683B1 (en) * 2000-07-20 2004-12-07 Silicon Graphics, Inc. System and method for transferring ownership of data in a distributed shared memory system
US6938128B1 (en) 2000-07-20 2005-08-30 Silicon Graphics, Inc. System and method for reducing memory latency during read requests
US6915387B1 (en) 2000-07-20 2005-07-05 Silicon Graphics, Inc. System and method for handling updates to memory in a distributed shared memory system
US6826619B1 (en) 2000-08-21 2004-11-30 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6810467B1 (en) * 2000-08-21 2004-10-26 Intel Corporation Method and apparatus for centralized snoop filtering
US7185196B1 (en) * 2000-09-15 2007-02-27 Atheros Communications, Inc. Key caching system
US6487643B1 (en) 2000-09-29 2002-11-26 Intel Corporation Method and apparatus for preventing starvation in a multi-node architecture
US6772298B2 (en) 2000-12-20 2004-08-03 Intel Corporation Method and apparatus for invalidating a cache line without data return in a multi-node architecture
US6791412B2 (en) 2000-12-28 2004-09-14 Intel Corporation Differential amplifier output stage
US7234029B2 (en) * 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US6721918B2 (en) 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US6971098B2 (en) 2001-06-27 2005-11-29 Intel Corporation Method and apparatus for managing transaction requests in a multi-node architecture
US20030131167A1 (en) * 2001-12-20 2003-07-10 Rankin Linda J. Node ID discovery
US6889295B2 (en) * 2002-03-05 2005-05-03 Hewlett-Packard Development Company, L.P. Re-ordering requests for shared resources
US6959364B2 (en) 2002-06-28 2005-10-25 Intel Corporation Partially inclusive snoop filter
US7000080B2 (en) 2002-10-03 2006-02-14 Hewlett-Packard Development Company, L.P. Channel-based late race resolution mechanism for a computer system
US6892290B2 (en) 2002-10-03 2005-05-10 Hewlett-Packard Development Company, L.P. Linked-list early race resolution mechanism
US6990559B2 (en) 2002-10-03 2006-01-24 Hewlett-Packard Development Company, L.P. Mechanism for resolving ambiguous invalidates in a computer system
US6895476B2 (en) 2002-10-03 2005-05-17 Hewlett-Packard Development Company, L.P. Retry-based late race resolution mechanism for a computer system
US6898676B2 (en) 2002-10-03 2005-05-24 Hewlett-Packard Development Company, L.P. Computer system supporting both dirty-shared and non-dirty-shared data processing entities
US7024520B2 (en) 2002-10-03 2006-04-04 Hewlett-Packard Development Company, L.P. System and method enabling efficient cache line reuse in a computer system
US7003635B2 (en) 2002-10-03 2006-02-21 Hewlett-Packard Development Company, L.P. Generalized active inheritance consistency mechanism having linked writes
US7051163B2 (en) 2002-10-03 2006-05-23 Hewlett-Packard Development Company, L.P. Directory structure permitting efficient write-backs in a shared memory computer system
US7346744B1 (en) * 2002-11-04 2008-03-18 Newisys, Inc. Methods and apparatus for maintaining remote cluster state information
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US20050010615A1 (en) * 2003-04-11 2005-01-13 Sun Microsystems, Inc. Multi-node computer system implementing memory-correctable speculative proxy transactions
GB0317372D0 (en) * 2003-07-25 2003-08-27 Royal Holloway University Of L Routing protocol for ad hoc networks
US7596654B1 (en) 2006-01-26 2009-09-29 Symantec Operating Corporation Virtual machine spanning multiple computers
US7702743B1 (en) 2006-01-26 2010-04-20 Symantec Operating Corporation Supporting a weak ordering memory model for a virtual physical address space that spans multiple nodes
US7756943B1 (en) 2006-01-26 2010-07-13 Symantec Operating Corporation Efficient data transfer between computers in a virtual NUMA system using RDMA
US8635411B2 (en) 2011-07-18 2014-01-21 Arm Limited Data processing apparatus and method for managing coherency of cached data
US10540316B2 (en) 2017-12-28 2020-01-21 Advanced Micro Devices, Inc. Cancel and replay protocol scheme to improve ordered bandwidth

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5265232A (en) * 1991-04-03 1993-11-23 International Business Machines Corporation Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data
CA2078310A1 (en) * 1991-09-20 1993-03-21 Mark A. Kaufman Digital processor with distributed memory system
US5504874A (en) * 1993-09-29 1996-04-02 Silicon Graphics, Inc. System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
US5778437A (en) * 1995-09-25 1998-07-07 International Business Machines Corporation Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory
US5893160A (en) * 1996-04-08 1999-04-06 Sun Microsystems, Inc. Deterministic distributed multi-cache coherence method and system
US5822763A (en) * 1996-04-19 1998-10-13 Ibm Corporation Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors

Also Published As

Publication number Publication date
EP0817074A1 (de) 1998-01-07
JPH10134014A (ja) 1998-05-22
US5950226A (en) 1999-09-07
EP0817074B1 (de) 2003-08-27
DE69724353T2 (de) 2004-06-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee