DE69712818T2 - A semiconductor memory device - Google Patents

A semiconductor memory device

Info

Publication number
DE69712818T2
DE69712818T2 DE69712818T DE69712818T DE69712818T2 DE 69712818 T2 DE69712818 T2 DE 69712818T2 DE 69712818 T DE69712818 T DE 69712818T DE 69712818 T DE69712818 T DE 69712818T DE 69712818 T2 DE69712818 T2 DE 69712818T2
Authority
DE
Germany
Prior art keywords
test
writing
voltage
writing test
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69712818T
Other languages
German (de)
Other versions
DE69712818D1 (en
Inventor
Naotoshi Nakadai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69712818D1 publication Critical patent/DE69712818D1/en
Application granted granted Critical
Publication of DE69712818T2 publication Critical patent/DE69712818T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G11C16/225—Preventing erasure, programming or reading when power supply voltages are outside the required ranges
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

In a semiconductor memory device, a memory cell array 14 includes a test memory region 142 for a writing test, and there are provided a writing test circuit for generating a writing test signal WTEST, a write voltage-detecting circuit 18 for generating a voltage-detecting signal WREN when a writing voltage supplied to the region 142 is less than a reference value at the time of writing test, and an output buffer circuit 15 which switches it to a test output mode in response to the supply of the writing test signal WTEST and outputs a write inhibit information in response to the supply of voltage-detecting signal WREN. <IMAGE>
DE69712818T 1996-02-21 1997-02-19 A semiconductor memory device Expired - Fee Related DE69712818T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3387996A JP2818571B2 (en) 1996-02-21 1996-02-21 Semiconductor storage device

Publications (2)

Publication Number Publication Date
DE69712818D1 DE69712818D1 (en) 2002-07-04
DE69712818T2 true DE69712818T2 (en) 2003-01-16

Family

ID=12398813

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69712818T Expired - Fee Related DE69712818T2 (en) 1996-02-21 1997-02-19 A semiconductor memory device

Country Status (5)

Country Link
US (1) US5923674A (en)
EP (1) EP0791934B1 (en)
JP (1) JP2818571B2 (en)
KR (1) KR100245313B1 (en)
DE (1) DE69712818T2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69631284D1 (en) * 1996-03-29 2004-02-12 St Microelectronics Srl Programming and reading management architecture for memory devices, in particular for testing purposes
JP5044868B2 (en) * 2000-11-17 2012-10-10 富士通セミコンダクター株式会社 Semiconductor device and multichip module
US7298656B2 (en) * 2004-04-30 2007-11-20 Infineon Technologies Ag Process monitoring by comparing delays proportional to test voltages and reference voltages
US7620792B2 (en) * 2006-08-21 2009-11-17 Sigmatel, Inc. Processing system, memory and methods for use therewith
JP4982883B2 (en) 2006-09-14 2012-07-25 株式会社メガチップス Storage device and data output circuit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4967394A (en) * 1987-09-09 1990-10-30 Kabushiki Kaisha Toshiba Semiconductor memory device having a test cell array
US5428574A (en) * 1988-12-05 1995-06-27 Motorola, Inc. Static RAM with test features
JP2519585B2 (en) * 1990-07-03 1996-07-31 三菱電機株式会社 Nonvolatile semiconductor memory device
JP2977385B2 (en) * 1992-08-31 1999-11-15 株式会社東芝 Dynamic memory device
JP3236105B2 (en) * 1993-03-17 2001-12-10 富士通株式会社 Nonvolatile semiconductor memory device and operation test method thereof
TW243531B (en) * 1993-09-03 1995-03-21 Motorola Inc

Also Published As

Publication number Publication date
EP0791934A2 (en) 1997-08-27
DE69712818D1 (en) 2002-07-04
EP0791934B1 (en) 2002-05-29
JP2818571B2 (en) 1998-10-30
JPH09231800A (en) 1997-09-05
US5923674A (en) 1999-07-13
KR970063277A (en) 1997-09-12
KR100245313B1 (en) 2000-03-02
EP0791934A3 (en) 1999-04-28

Similar Documents

Publication Publication Date Title
KR920010617A (en) Semiconductor memory
KR950006850A (en) Selector circuit
EP1158532A3 (en) Semiconductor memory device
DE69223461D1 (en) Configurable self-test for integrated RAMs
KR970023372A (en) Semiconductor memory
TW374169B (en) Semiconductor memory device
KR910007272A (en) Programmable Logic Devices and Memory Circuits Used in the Devices
KR970076846A (en) Delay circuit
KR860002100A (en) Semiconductor memory
EP0600655A3 (en) Integrated circuit test arrangement and method.
KR860008559A (en) Semiconductor memory
HK1025837A1 (en) Nonvolatile memory device and inspection method thereof
DE69220256D1 (en) Semiconductor memory device
KR910019050A (en) Semiconductor memory
KR910015999A (en) Semiconductor memory device
DE69712818D1 (en) A semiconductor memory device
KR930003139A (en) Semiconductor memory
DE59706533D1 (en) Single-electron memory cell array
KR920017115A (en) Semiconductor memory device
KR920006974A (en) Dynamic Semiconductor Memory Device
KR920010656A (en) Semiconductor memory device
TW329012B (en) Semiconductor Memory Device
WO2004027779A3 (en) Improved memory architecture
EP0304591A3 (en) Semiconductor memory with signal change detector circuit
DE69434596D1 (en) Interrupt-controlled sound data processing device

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

Owner name: NEC CORP., TOKIO/TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee