DE69702350D1 - Verzweigungsvorhersageschema für cachespeicherzeile, das von sätzen eines set-assoziativen cachespeichers gemeinsam verwendet wird - Google Patents

Verzweigungsvorhersageschema für cachespeicherzeile, das von sätzen eines set-assoziativen cachespeichers gemeinsam verwendet wird

Info

Publication number
DE69702350D1
DE69702350D1 DE69702350T DE69702350T DE69702350D1 DE 69702350 D1 DE69702350 D1 DE 69702350D1 DE 69702350 T DE69702350 T DE 69702350T DE 69702350 T DE69702350 T DE 69702350T DE 69702350 D1 DE69702350 D1 DE 69702350D1
Authority
DE
Germany
Prior art keywords
cache storage
sets
line together
presentation schedule
forwarding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69702350T
Other languages
English (en)
Other versions
DE69702350T2 (de
Inventor
Shine Chung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69702350D1 publication Critical patent/DE69702350D1/de
Application granted granted Critical
Publication of DE69702350T2 publication Critical patent/DE69702350T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69702350T 1996-09-19 1997-09-19 Verzweigungsvorhersageschema für cachespeicherzeile, das von sätzen eines set-assoziativen cachespeichers gemeinsam verwendet wird Expired - Lifetime DE69702350T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/710,560 US5774710A (en) 1996-09-19 1996-09-19 Cache line branch prediction scheme that shares among sets of a set associative cache
PCT/US1997/016797 WO1998012631A1 (en) 1996-09-19 1997-09-19 A cache line branch prediction scheme that shares among sets of a set associative cache

Publications (2)

Publication Number Publication Date
DE69702350D1 true DE69702350D1 (de) 2000-07-27
DE69702350T2 DE69702350T2 (de) 2001-02-15

Family

ID=24854536

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69702350T Expired - Lifetime DE69702350T2 (de) 1996-09-19 1997-09-19 Verzweigungsvorhersageschema für cachespeicherzeile, das von sätzen eines set-assoziativen cachespeichers gemeinsam verwendet wird

Country Status (4)

Country Link
US (1) US5774710A (de)
EP (1) EP0927394B1 (de)
DE (1) DE69702350T2 (de)
WO (1) WO1998012631A1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574871A (en) * 1994-01-04 1996-11-12 Intel Corporation Method and apparatus for implementing a set-associative branch target buffer
JPH10214188A (ja) * 1997-01-30 1998-08-11 Toshiba Corp プロセッサの命令供給方法及び装置
JPH10333908A (ja) * 1997-05-30 1998-12-18 Mitsubishi Electric Corp 分岐予測方法
US5941985A (en) * 1997-06-24 1999-08-24 Sun Microsystems, Inc. Branch instruction prediction method
US5857098A (en) * 1997-06-24 1999-01-05 Samsung Electronics Co., Ltd. Branch instruction prediction apparatus
US6067601A (en) * 1997-11-03 2000-05-23 Brecis Communications Cache memory based instruction execution
US6216218B1 (en) 1997-11-03 2001-04-10 Donald L. Sollars Processor having a datapath and control logic constituted with basis execution blocks
US6016545A (en) * 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor
US6275927B2 (en) 1998-09-21 2001-08-14 Advanced Micro Devices. Compressing variable-length instruction prefix bytes
US6460116B1 (en) 1998-09-21 2002-10-01 Advanced Micro Devices, Inc. Using separate caches for variable and generated fixed-length instructions
US6253309B1 (en) 1998-09-21 2001-06-26 Advanced Micro Devices, Inc. Forcing regularity into a CISC instruction set by padding instructions
US6240506B1 (en) 1998-10-02 2001-05-29 Advanced Micro Devices, Inc. Expanding instructions with variable-length operands to a fixed length
US6339822B1 (en) * 1998-10-02 2002-01-15 Advanced Micro Devices, Inc. Using padded instructions in a block-oriented cache
EP1236095B1 (de) * 2000-02-28 2010-04-14 Nxp B.V. Datenprozessor mit meherern befehlen umfassende befehlswörtern
US7107437B1 (en) * 2000-06-30 2006-09-12 Intel Corporation Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB)
US20020166042A1 (en) * 2001-05-01 2002-11-07 Yoav Almog Speculative branch target allocation
US6978361B2 (en) * 2002-09-20 2005-12-20 International Business Machines Corporation Effectively infinite branch prediction table mechanism
US7437543B2 (en) * 2005-04-19 2008-10-14 International Business Machines Corporation Reducing the fetch time of target instructions of a predicted taken branch instruction
US7827392B2 (en) * 2006-06-05 2010-11-02 Qualcomm Incorporated Sliding-window, block-based branch target address cache
US7640422B2 (en) * 2006-08-16 2009-12-29 Qualcomm Incorporated System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache
US20090249048A1 (en) * 2008-03-28 2009-10-01 Sergio Schuler Branch target buffer addressing in a data processor
US9354885B1 (en) * 2016-01-08 2016-05-31 International Business Machines Corporation Selective suppression of instruction cache-related directory access
US9898296B2 (en) 2016-01-08 2018-02-20 International Business Machines Corporation Selective suppression of instruction translation lookaside buffer (ITLB) access
US10481912B2 (en) 2016-06-24 2019-11-19 International Business Machines Corporation Variable branch target buffer (BTB) line size for compression
US10929535B2 (en) * 2018-06-29 2021-02-23 Intel Corporation Controlled introduction of uncertainty in system operating parameters

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4679141A (en) * 1985-04-29 1987-07-07 International Business Machines Corporation Pageable branch history table
US5265213A (en) * 1990-12-10 1993-11-23 Intel Corporation Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction
DE69327927T2 (de) * 1992-08-31 2000-10-12 Sun Microsystems Inc Schnelles Vorausholen und Zuteilung von Befehlen mittels vorausschauender Anmerkungen von früher vorausgeholten
US5367703A (en) * 1993-01-08 1994-11-22 International Business Machines Corporation Method and system for enhanced branch history prediction accuracy in a superscalar processor system
US5530825A (en) * 1994-04-15 1996-06-25 Motorola, Inc. Data processor with branch target address cache and method of operation
US5663965A (en) * 1995-10-06 1997-09-02 International Business Machines Corp. Apparatus and method for testing a memory array

Also Published As

Publication number Publication date
EP0927394B1 (de) 2000-06-21
US5774710A (en) 1998-06-30
EP0927394A1 (de) 1999-07-07
WO1998012631A1 (en) 1998-03-26
DE69702350T2 (de) 2001-02-15

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Legal Events

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8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY