DE69628481T2 - Device for reducing signal interference for a liquid crystal display - Google Patents

Description

The present invention relates to general driver circuits for Playback devices and in particular a system for supplying brightness signals to pixels of a display unit arranged in a matrix such as for example a liquid crystal display (LCD = liquid crystal display).

Display units such as liquid crystal displays consist of a matrix of pixels arranged horizontally in rows and are arranged vertically in columns. The video information to be played back data lines are supplied as brightness (gray scale) signals are individually assigned to each column of pixels. The series of Pixels are sampled sequentially by signals that are in row select lines be formed. The capacity of the pixel for the activated row selection line is via the corresponding data lines corresponding to the value of the brightness signal supplied to the individual columns loaded to different brightness values.

Amorphous silicon was the preferred Technology for the production of liquid crystal displays, because this material is made at low temperatures can. A low manufacturing temperature is important because of it the application of usual, readily available and inexpensive substrate materials allows. However, the use of thin film transistors made of amorphous silicon (a-Si TFTs) in peripheral integrated pixel drivers because of the lower mobility, the drift of the threshold voltage and the availability of improved metal oxide semiconductors Only make N-type (N-MOS) transistors difficult to manufacture.

In an active matrix display, each pixel element contains a switching unit that supplies the video signal to the pixel. In general, the switching unit is a TFT that receives the brightness information from the solid state circuit. Since both the TFTs and the circuit consist of solid state units, it is preferable to fabricate the TFTs and the driver circuit at the same time using amorphous silicon or polysilicon technology. The US 5 170 155 in the name of Plus et al., entitled "System for Applying Brightness Signals To A Display Device And Comparator Therefore" describes an example of a data line or column drivers of an LCD.

Because of the parasitic coupling between the column data lines and the row select lines is that formed in the data lines Data ramp voltage capacitive with each of the row select lines coupled and generates a parasitic interference signal. It is desirable to prevent such a parasitic signal in the row select lines is created to prevent wrong selection of a row. A was possible solution in EP-A-0 570 001.

A row select driver circuit is desirably fabricated directly on the same substrate and simultaneously with the manufacture of the liquid crystal cells. An example of a known scan or shift register that controls the row select lines is described in US Pat US 5 222 082 , which can be integrated with a liquid crystal display unit. An output area of the register is designed as a push-pull amplifier, which can be formed by TFTs. When a particular row is preselected, a so-called pull-down TFT of the push-pull amplifier is turned on to apply an appropriate impedance to a terminal of a row row conductor of the row not selected. This short-circuits the parasitic signal mentioned above or prevents it from developing a significant size on the row row conductor.

Each row row conductor is for the most part an update cycle or a frame time is not selected. Therefore are the pulldown TFT's while most of the time conductive and subject to overuse.

Around the threshold voltage drift in the pulldown TFT, it is desirable to have a significant drive avoid the pulldown TFT. Therefore, it is desirable the size of the stream the pulldown TFT needs to conduct. In is advantageous by reducing the interference signal the current that the pulldown TFT needs to conduct is reduced. Hence the Pulldown TFT in the circuit less critical.

A video player with one aspect of the invention provides a video signal to the pixels, those in multiple rows and multiple columns in an array a playback unit are arranged. The device contains several row selection row drivers for the successive feeding the row select signals to multiple row select lines. Several Data line drivers deliver the video signal to multiple data lines, assigned to the multiple columns. An amplifier becomes by interference signals controlled, which arise in the corresponding lines of the arrangement and an input of the amplifier via a first additional, So-called dummy (blind) line are supplied, at least is partially connected to the corresponding lines for generation one reinforced Output signal. The output signal is an indication of the interference signals and is in negative feedback about the additional Dummy line of the arrangement of the lines forming the interference signal supplied around the interference signals to reduce significantly, so that each of the additional lines oblique or transverse and capacitive with one of the interfering signal supply lines is coupled.

Advantageously, similar interference removal arrangements can be used for display units other than LCD display units, the matrices for the addressing of the pixels use, such as a plasma discharge display.

1 1 shows a block diagram of a shift register with a plurality of stages arranged in a cascade,

2 FIG. 3 shows a circuit diagram of a shift register stage with an aspect of the invention contained in the shift register of FIG 1 can be applied.

3a - 3d are graphs showing the relative timing of the output signals and the corresponding clock signals at the respective points of the shift register of 1 using the in 2 illustrated levels,

4 FIG. 10 is a circuit diagram of a compensation arrangement for changing the threshold voltage with an aspect of the invention for the switching of FIG 2 .

5 shows a curve for explaining the operation of the circuit of FIG 4 .

6 shows a liquid crystal display with a noise suppression arrangement for reducing a current in an output stage of the shift register of 2 , and

7 shows an amplifier of the circuit of 6 in detail.

DETAILED DESCRIPTION

2 shows an exemplary level n of a shift register 100 of 1 , The shift register 100 of 1 controls row selection lines 118 a liquid crystal display matrix, which in 1 is not shown. In the shift register 100 stages n - 1, n, n + 1 and n + 2 are connected in a cascade arrangement. An output signal of a certain stage is fed to an input of the stage immediately following in the chain. For example, an output pulse OUTn - 1 of the previous stage n - 1 in the chain of the register 100 an input terminal 12 level n of 2 fed. As an example, only four stages n-1, n, n + 1 and n + 2 are shown. However, the total number of levels is n in the chain of the register 100 much larger. The shift register 100 can be called a "walking one" shift register. This is because a so-called TRUE status moves through the register during a video frame time 100 common.

A clock generator 101 of 1 generates a three-phase clock signal (clock signals C1, C2 and C3) with waveforms that are in the 3d . 3c respectively. 3b are shown. The pulse of the signal OUTn - 1 from 3a is generated when the pulse of the clock signal C3 of level n - 1 of 1 is fed. Same symbols and reference symbols in the 1 . 2 and 3a - 3d designate the same parts or functions.

The signal OUTn - 1 from 1 arises at the input terminal 12 level n of 2 , The signal OUTn - 1 with the value HIGH or "1" is via a transistor 18 of 2 that works as a switch, a clamp 18a fed to form a control signal P1. Immediately before the occurrence of the clock signal C1, the signal P1 is on the terminal 18a boosted to a higher voltage by a clock signal C3 using a so-called bootstrap process, via a capacitor 31 the clamp 18a is fed. The signal OUTn - 1 of level n - 1, that of the input terminal 12 the stage n is also applied to the gate electrode of a transistor 21 fed. A drain electrode of the transistor 21 is over a clamp 21a with the gate electrode of a transistor 19 and the gate electrode of a so-called pulldown transistor 17 fed. This will make both transistors 19 and 17 made non-conductive.

The value HIGH or "1" of the signal P1 is temporarily in a capacitance, not shown, between the electrodes and in a capacitor 30 saved. The signal P1, which is at the gate of an output transistor 16 arises, causes the output transistor 16 becomes a leader. The clock signal C1 from 3d is about the transistor 16 the output terminal 13 fed when the clamp 18a is "1". Parasitic capacitances CP between the electrodes tend to "bootstrap" the voltage at the terminal 18a which is an additional control for the transistor 16 forms. This will result in an output pulse signal OUTn at the output terminal 13 of the register n is formed. During this interval the pulldown transistor 17 through the action of the transistor 21 made non-conductive and then has no effect on the signal OUTn.

The signal OUTn of stage n becomes an input terminal of the subsequent stage n + 1 of 1 fed. Stage n + 1 works similarly to stage n, with the exception of using clock signal C2 instead of clock signal C1 in stage n to turn on the corresponding transistor. If the clock signal C1 assumes the inactive value LOW or "0", the transistor remains 16 switched on until the signal P1 goes to "0". The stage n OUTn goes through the transistor due to the discharge 16 to "0" when the clock signal C1 is "0".

A transistor 25 lies with its drain / source route between the terminal 18a and a reference voltage VSS1 sufficient, the pull-up transistor 16 turn off when the transistor 25 is leading. The gate of the transistor 25 level n becomes an output terminal of the subsequent level n + 2 in the chain of 1 guided and controlled by an output signal OUTn + 2.

The pulse of the signal OUTn + 2 appears simultaneously with the clock signal C3 from 3b , The pulse of the signal OUTn + 2 causes the transistor 25 of 2 the aforementioned capacitance CP between the electrodes on the terminal 18a discharges. The transistor 25 the signal is stuck at the terminal 18a to a value that prevents the transistor 16 generates an additional pulse of the signal OUTn when the immediately following pulse of the clock signal C1 occurs.

The pulse of the OUTn + 2 signal also turns on a transistor 20 the gate of the transistor 20 fed. The transistor 20 supplies a voltage VDD to the terminal with a further feature according to the invention 21a to turn on the transistors 17 and 19 , After the pulse of the signal OUTn + 2, the transistor 20 switched off. However, a capacitor stores 32 to the gate of the transistors 17 and 19 is connected by the operation of the transistor 20 a load. The stored charge in the capacitor 32 holds the transistors 17 and 19 conductive until the next sampling cycle if the signal at the terminal 12 causes the transistor 21 is turned on and thereby the transistors 17 and 19 turned off. The condenser 32 also causes interference filtering for the signal at the terminal 12 ,

As long as the transistor 17 is conductive, it works as a pulldown transistor to form a suitable impedance at the terminal 13 , So the transistor takes 17 a current i17. The drain / source impedance of the transistor is advantageous 17 sufficiently low to discharge the high value "1" on the row select line, and in addition, it should be sufficiently low to accommodate any parasitic currents supplied from the column lines of the LCD matrix to the row select line. If parasitic currents are not through the transistor 17 derived, they can generate voltages that increase to a large value that is sufficiently large to cause an incorrect selection in the subsequent register stage. Thus, an incorrect selection can be prevented, provided that the threshold voltage of the transistor 17 does not increase significantly over the service life. If the transistor 19 is conductive, it advantageously prevents the clock signals C1 and C3 from the transistor 16 turn on.

One pulse at each register output terminal 100 of 1 , for example the pulse of the signal OUTn + 2, appears only once during a vertical interval of approximately 16.6 milliseconds. Therefore, advantageously none of the switched transistors 18 . 16 . 20 and 25 level n of 2 biased for more than one clock period for a line during each vertical interval. On the other hand, the transistors 17 and 19 biased for permanent conduction during most of the vertical interval. It may be desirable to use the transistors 17 and 19 reduce supplied voltages that can cause the threshold voltages of the transistors 17 and 19 increase and their abilities to draw or dissipate electricity decrease.

To the load on the transistors 17 and 19 to decrease the signal P2 at the gate of the transistor 17 formed at a voltage value that is not more than, for example, 2 volts greater than the threshold voltage of the transistor at the beginning of the service life 17 , Since the threshold voltage VTH of the transistor 17 due to an overuse, it is desirable to compensate for such an increase in the threshold voltage VTH in a manner that improves the ability to conduct the transistors 17 and 19 keeps essentially constant over the service life.

Advantageously, the variable voltage VDD, which is the conductivity of the transistors 17 and 19 controls, increased in a way to the deviation of the threshold voltage in the transistors 17 and 19 to adapt during the lifespan. The change in voltage VDD prevents, for example, a decrease in the conductivity of the transistor 17 resulting from a drift in the threshold voltage of the voltage VTH of the transistor 17 could result.

4 shows a circuit 40 to compensate for the drift of the threshold voltage, which is the voltage VDD 2 and 4 generated. With the exception of the TFT 199 become the circuit components of the circuit 40 separate from the shift register 100 of 1 formed so that all the other transistors of the circuit 40 can be single crystal transistors and not TFT's. The TFT 199 is together with the shift register 100 of 1 formed on the glass of the LCD and is used to determine any threshold drifts in the TFTs.

In the circuit 40 there is a MOS transistor 41 P-type in series with a resistor 42 for generating a predetermined constant control current in the transistor 41 , A transistor 43 is with the transistor 41 connected in the form of a so-called current mirror. Thus the current i43 is in the transistor 43 through the transistor 41 current mirror controlled. Current i43 becomes a series connection of a transistor 44 , a transistor 45 and a TFT 199 supplied by the N type. As a result of the current i43 becomes a threshold voltage compensation voltage 46 above the series connection at the terminal 46 educated.

The gate electrode of the TFT 199 is connected to its drain electrode. Therefore, the source / drain voltage is V199 across the TFT 199 equal to the source / gate voltage of the TFT 199 , The gate / source voltage V199 across the TFT 199 forms a first part of the tension 46a , Voltage V199 is an indication of the threshold voltage of the transistor 199 , Since the TFT 199 similar threshold voltage change characteristics as the transistor 17 of 2 voltage V199 is also an indication of the threshold voltage VTH of the transistor 17 , The TFT is for easier dimensioning 199 a larger transistor. Therefore, a relatively larger value of current i43 than that in the transistor serves 17 flows to form voltage V199. If due to an overuse an increase in the threshold voltage VTH in the transistor 17 of 2 occurs, because of the similarity of the properties and the stress, there is a corresponding increase in the voltage V199 from 4 ,

Each of the transistors 44 and 45 that are in series with the TFT 199 lie, is connected with its gate to its drain and contains a substrate clamp, which is connected via a capacitor 48 is connected to a reference value G. Part of the tension 46a that are in the transistors 44 and 45 arises, is used to generate the tension 46a added to voltage V199. This way the tension 46a approximately 2 V greater than voltage V199. The voltage V199 is substantially equal to the threshold voltage VTH of the transistor 17 of 2 and increases as the voltage VTH increases.

The voltage 46a is fed to a non-inverting amplifier with gain one to generate the voltage VDD which is equal to the voltage 46a is. The voltage VDD is across the transistor 20 of 2 to change the voltage value of the signal P2 of the transistor 17 fed.

The above voltage difference of, for example, 2 V through the transistors 44 and 45 of 4 is generated, the LCD is reached at the start of service operation. The threshold voltage of the transistor increases during the operating hours 199 on. It may be desirable that the tension 46a increases by more than voltage V199, by the same conductivity in the transistor 17 of 2 maintain.

Advantageously, the substrate is biased at a value that is less than the source voltage of each of the transistors 44 and 45 as explained above. A rise in voltage V199 creates channel modulation in each of the transistors 44 and 45 , The channel modulation arises from the increase in the source / substrate voltage. Therefore, the resistance of each of the transistors increases 44 and 45 with the increase in voltage V199. In this way, the voltage is advantageously 46a increased in a non-linear manner. The increase in tension 46a is proportionately larger than if the transistors 44 and 45 would work as linear resistors or as simple level shifters. In this way, the conductivity of the transistor can be advantageously 17 can be kept relatively constant even if the threshold voltage VTH of the transistor 17 increases.

5 shows an example of the magnitude of the current i17 that the transistor 17 can absorb so that the source / drain voltage is kept at not more than 50 mV. How 5 shows, for a corresponding change in the threshold voltage VTH of approximately 10 V, the current i17 changes by less than 5%.

To the load on the transistor 17 to decrease, it is desirable to keep current i17 low, such as within the in 5 shown current range. A conductive current i17 with a higher value than the range of 5 could have a higher gate / source voltage in the transistor 17 require. Such a higher gate / source voltage could result in a higher load on the transistor 17 and thereby disadvantageously result in a shorter lifespan.

6 shows a noise suppression circuit 200 with an aspect of the invention for liquid crystal display 16 ' , Same symbols and reference symbols in the 1 . 2 3a - 3d and 4 - 6 designate the same parts or functions. The circuit 200 of 6 keeps the current i17 from 2 at a relatively small value. The order 16 ' of 6 contains column data lines 177 and row selection lines 118 , The row selection lines 118 are through the shift register 100 of 1 for a successive selection of the row lines 118 controlled. Column data lines 117 can be controlled in a similar way as in the US 5 170 155 in the name of Plus et al., entitled "System for Applying Brightness Signals To A Display Device And Comparator Therefore". The data line drivers from Plus et al. work as clocked ramp amplifiers. Any data line 177 of 6 is through an appropriate transistor 126 controlled. A certain transistor 126 a corresponding data line driver supplies one in a data ramp generator 234 generated ramp voltage 128 to a corresponding data line 177 the matrix for forming a ramp signal in the pixels 16a the selected row. The transistor switch 126 is controlled by a comparator, not shown. The transistor switch 126 is used for supplying the data ramp voltage 128 to the data line 177 switched on and switched off at a controllable point in time, which is determined by the size of the image information contained in the video signal, not shown.

When executing a feature according to the invention, the arrangement contains 16 ' in addition to the conventional data lines 177 a pair of column lines 177a and 177b that do not provide any image information and here as so-called blind or dummy column lines 177a and 177b be designated. The column lines 177a and 177b are parallel to the data lines 177 at both ends of the arrangement 16 ' , The data lines are thus located 177 between the dummy column lines 177a and 177b , A significant number of transmission gates provide for the reproduction of a typical image content 126 corresponding parts of the data ramp voltage 128 to the corresponding data lines 177 , around in a particular data line 177 to form a data ramp voltage VDATALINE.

A parasitic coupling capacitance CRC is every intersection or intersection of each row select line 118 and every data line 177 assigned. A ROW-NOISE signal is generated on the respective select lines as a result of the parasitic capacitances that connect the clocked ramp signals supplied to the data lines to the row select lines.

The dummy column line 177a with similar capacities CRD, but much larger than the capacities CRC, is used to form a signal NOISE-SENSE (noise scan), which is the one in the row selection lines 118 formed signals ROW-NOISE. The ROW-NOISE signals are transmitted via the capacities CRD of a line 177a fed. The capacities CRD are intermediate line capacities between the lines 118 and the line 177a , An assumption is made that the signal ROW-NOISE in the respective row selection lines 118 that have not been chosen have similar amplitude and curve shape.

The NOISE-SENSE signal becomes an input terminal 201 a noise suppression amplifier 202 fed. The amplifier 202 is an inverting amplifier with a relatively large gain, which inverts the instantaneous value of the NOISE-SENSE signal and generates a NOISE-CANCEL signal. The NOISE-CANCEL signal is an alternating voltage signal that that of the dummy column line 177b is fed. The signal NOISE-CANCEL is capacitive from the line 177b about capacities CRD the row selection lines 118 fed. Since the NOISE-CANCEL signal is in phase opposition to the NOISE-SENSE signal, the NOISE-CANCEL signal tends to have the ROW-NOISE signals in each row select line 118 to reduce significantly.

It may be desirable to have parasitic capacitive coupling between the row select lines 118 and the dummy column lines 177a and 177b to enlarge, as shown schematically by the capacitors CRD, in order to achieve sufficient sensitivity and stability. Therefore, the width dimension W of each line 177a and 177b chosen much larger than that of the data line 177 , For example, the total capacity between the lines 177a and the row selection lines 118 are in the range from 2000 pF to 3000 pF.

7 shows the amplifier 202 of 6 in detail. Same symbols and reference symbols in the 1 . 2 . 3a - 3d and 4 - 7 designate the same parts or functions. The amplifier 202 of 7 contains a non-inverting amplifier 202a with reinforcement one. The signal NOISE-SENSE is connected via a resistor R2 and a level shift arrangement with a capacitor C2 to a non-inverting input terminal IN + of the amplifier 202a fed. A P-type metal oxide semiconductor (MOS) transistor and an N-type MOS transistor MN supply a reference voltage REF of 10 V across the capacitor C2 when a pulse signal PRECHG and a complementary pulse signal PRECHAG-INV at the gates the transistors MP and MN arise. In this way, a voltage of, for example, 10 V at the IN + terminal is added to the instantaneous voltage of the NOISE-SIGNAL signal. The transistors MP and MN are turned on and off to the capacitor C2 in the vicinity of a time T1 of the curve of the ramp voltage VDATALINE of 6 in front of a ramp part 66 the voltage VDATALINE.

The voltage REF of 7 also becomes a non-inverting input terminal of an inverting amplifier 202b supplied with high gain via an RC filter from a resistor Rx and a capacitor C4. An output signal OUT of the amplifier 202a is a resistor R3 an inverting input terminal of the amplifier 202b fed. A feedback resistor R4 is located between an output terminal of the amplifier 202b , where the signal NOISE-CANCEL originates, and the inverting input terminal of the amplifier 202b , The amplifier's AC gain 202b with the feedback is approximately equal to 2000.

As long as the voltage at the terminal 201 is zero, as at time T1 when there is no signal interference, the shift in the DC voltage value caused by the voltage across capacitor C2 produces an output signal 202c from the amplifier 202a of 10 V. Due to the voltage of 10 V at the non-inverting input terminal of the amplifier 202b is the voltage at the output terminal of the amplifier 202b , where the signal NOISE-CANCEL originates, is equal to 10 V. Thus, a voltage range of the signal NOISE-CANCEL of 7 an upper range limit in the vicinity of an operating voltage VS of +22 V and a lower range limit in the vicinity of 0 V. Advantageously, the signal NOISE-CANCEL is normally biased approximately in the middle between +22 V and 0 V, so that the Voltage swings of the NOISE-CANCEL signal can occur in opposite directions.

As explained above, the NOISE-CANCEL signal significantly reduces the size of the NOISE-SENSE signal when the input voltage is at the terminal 201 of 6 changes. If the signal at the terminal 201 changes such that the signal NOISE-SENSE of a certain amplitude arises, the signal NOISE-CANCEL of the amplifier tends 202b to significantly reduce the amplitude of the NOISE-SENSE signal. Because of the high gain of the amplifier 202b the interference reduction is noteworthy.

When performing a fiction The characteristic feature is the capacitive coupling between the line 177b and the selection lines 118 that the signal ROW-NOISE in each row selection line 118 is significantly reduced in an advantageous manner. The current i17 in the transistor 17 of 2 is also advantageously reduced. Therefore, the transistor 17 cannot be controlled by a large gate / source voltage. The transistor 17 is therefore not significantly claimed. The result is that the transistor 17 has a longer lifespan than if it were used.

Claims (7)

A video display apparatus for supplying a video signal to pixels arranged in a plurality of rows and in a plurality of columns of an arrangement of a reproduction unit, comprising: a plurality of row selection line drivers ( 100 ) for the sequential supply of row selection signals to several row selection lines ( 118 ), several data line drivers for feeding the video signal to several data lines ( 177 ), which are assigned to the several columns, characterized by an amplifier controlled by interference signals ( 200 ) in the row selection lines ( 118 ) of the arrangement, which are created via a first additional dummy line ( 177a ) are connected to an input of the amplifier for generating an output signal which is amplified and which indicates the interference signals, the output being in negative feedback via a second additional dummy line ( 177b ) the arrangement is connected to the lines forming the interference signal, in order to significantly reduce the interference signals, such that each of the additional lines is transversely and capacitively connected to a specific line ( 118 ) the lines forming the interference signal are connected. Apparatus according to claim 1, wherein if the Video signal is supplied to the multiple data lines, the interference signals arise in a certain row selection line, and the Amplifier output capacitive about the second additional Line is fed to the multiple row selection lines. The apparatus of claim 1, wherein the second additional Capacitive line connected to the multiple row selection lines is the amplifier output signal to the row selection lines. The apparatus of claim 3, wherein the second additional Line overlaps the corresponding parts of the multiple row selection lines. The apparatus of claim 1, wherein the first additional Line is arranged so that it detects the interference signals, wherein the first additional Line extends transversely to the row select lines and the first additional Line has a width dimension that is significantly larger than the width dimension of a specific data line of the data lines, such that a larger capacity between the first additional Line and the row selection lines is formed. The apparatus of claim 1, wherein the second additional Line with the amplifier output signal connected and capacitive to the multiple row select lines is coupled, for capacitive coupling of the amplifier output signal with the multiple row selection lines. The apparatus of claim 6, wherein the second additional Lines extend transversely to the row select lines and have a width dimension that is appreciably larger than the width dimension of a particular data line among the plurality Data lines, such that a capacity between the second additional Line and the row selection lines is increased.