DE69624952T2 - Einstellbarer Frequenzteiler - Google Patents

Einstellbarer Frequenzteiler

Info

Publication number
DE69624952T2
DE69624952T2 DE1996624952 DE69624952T DE69624952T2 DE 69624952 T2 DE69624952 T2 DE 69624952T2 DE 1996624952 DE1996624952 DE 1996624952 DE 69624952 T DE69624952 T DE 69624952T DE 69624952 T2 DE69624952 T2 DE 69624952T2
Authority
DE
Germany
Prior art keywords
frequency divider
adjustable frequency
adjustable
divider
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1996624952
Other languages
English (en)
Other versions
DE69624952D1 (de
Inventor
Yasuaki Sumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Consumer Electronics Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Tottori Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Tottori Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Publication of DE69624952D1 publication Critical patent/DE69624952D1/de
Application granted granted Critical
Publication of DE69624952T2 publication Critical patent/DE69624952T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
DE1996624952 1996-01-09 1996-09-25 Einstellbarer Frequenzteiler Expired - Lifetime DE69624952T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP164496 1996-01-09

Publications (2)

Publication Number Publication Date
DE69624952D1 DE69624952D1 (de) 2003-01-02
DE69624952T2 true DE69624952T2 (de) 2003-08-28

Family

ID=11507237

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1996624952 Expired - Lifetime DE69624952T2 (de) 1996-01-09 1996-09-25 Einstellbarer Frequenzteiler

Country Status (2)

Country Link
EP (1) EP1005164B1 (de)
DE (1) DE69624952T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008009924A1 (de) * 2008-02-15 2009-08-27 Altenbrunn, Jürgen Verfahren zum Generieren von Frequenzen

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4198303B2 (ja) * 2000-06-15 2008-12-17 富士通マイクロエレクトロニクス株式会社 Ｆｒａｃｔｉｏｎａｌ−ＮＰＬＬ周波数シンセサイザの位相誤差除去方法及びＦｒａｃｔｉｏｎａｌ−ＮＰＬＬ周波数シンセサイザ
CN104901684B (zh) * 2015-04-25 2017-10-20 福州大学 一种分频电路及其控制方法
RU2765273C1 (ru) * 2021-07-01 2022-01-27 Акционерное общество "Концерн "Созвездие" Цифровой формирователь частотно-модулированных сигналов с низким уровнем искажений
CN117081582B (zh) * 2023-05-12 2024-04-23 南京筠芯科技有限公司 一种实现占空比50%的分频方法及分频器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1022043B (it) * 1974-06-06 1978-03-20 Sits Soc It Telecom Siemens Divisore simmetrico di frequenza per un numero k dispari
US4573176A (en) * 1983-11-18 1986-02-25 Rca Corporation Fractional frequency divider
US4975931A (en) * 1988-12-19 1990-12-04 Hughes Aircraft Company High speed programmable divider
US4935944A (en) * 1989-03-20 1990-06-19 Motorola, Inc. Frequency divider circuit with integer and non-integer divisors
US5063579A (en) * 1990-05-11 1991-11-05 Northern Telecom Limited Scaler for synchronous digital clock
JPH05291950A (ja) * 1992-04-15 1993-11-05 Mitsubishi Electric Corp フェーズロックドループ周波数シンセサイザ

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008009924A1 (de) * 2008-02-15 2009-08-27 Altenbrunn, Jürgen Verfahren zum Generieren von Frequenzen
DE102008009924B4 (de) * 2008-02-15 2014-10-30 Jürgen Altenbrunn Verfahren zum Generieren von Frequenzen

Also Published As

Publication number Publication date
EP1005164B1 (de) 2002-11-20
DE69624952D1 (de) 2003-01-02
EP1005164A1 (de) 2000-05-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition