DE69617919D1 - Speichergerät mit getakteter Spaltenredundanz - Google Patents
Speichergerät mit getakteter SpaltenredundanzInfo
- Publication number
- DE69617919D1 DE69617919D1 DE69617919T DE69617919T DE69617919D1 DE 69617919 D1 DE69617919 D1 DE 69617919D1 DE 69617919 T DE69617919 T DE 69617919T DE 69617919 T DE69617919 T DE 69617919T DE 69617919 D1 DE69617919 D1 DE 69617919D1
- Authority
- DE
- Germany
- Prior art keywords
- clocked
- storage device
- column redundancy
- redundancy
- column
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96830325A EP0811919B1 (de) | 1996-06-06 | 1996-06-06 | Speichergerät mit getakteter Spaltenredundanz |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69617919D1 true DE69617919D1 (de) | 2002-01-24 |
DE69617919T2 DE69617919T2 (de) | 2002-08-08 |
Family
ID=8225931
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69617919T Expired - Fee Related DE69617919T2 (de) | 1996-06-06 | 1996-06-06 | Speichergerät mit getakteter Spaltenredundanz |
Country Status (3)
Country | Link |
---|---|
US (1) | US5831915A (de) |
EP (1) | EP0811919B1 (de) |
DE (1) | DE69617919T2 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6240525B1 (en) * | 1998-11-17 | 2001-05-29 | Oak Technology, Inc. | Method and apparatus for re-addressing defective memory cells |
EP1178491A1 (de) * | 2000-08-02 | 2002-02-06 | STMicroelectronics S.r.l. | Halbleiterspeicher |
US6928377B2 (en) * | 2003-09-09 | 2005-08-09 | International Business Machines Corporation | Self-test architecture to implement data column redundancy in a RAM |
US9953725B2 (en) * | 2012-02-29 | 2018-04-24 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods of operating the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0257120B1 (de) * | 1986-08-22 | 1992-06-10 | International Business Machines Corporation | Dekodierverfahren und -Schaltungsanordnung für einen redundanten CMOS-Halbleiterspeicher |
US5708601A (en) * | 1993-12-09 | 1998-01-13 | Sgs-Thomson Microelectronics S.R.L. | Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device |
DE69412230T2 (de) * | 1994-02-17 | 1999-04-08 | Sgs Thomson Microelectronics | Verfahren zur Programmierung von Redundanzregistern in einer Spaltenredundanzschaltung für einen Halbleiterspeicherbaustein |
-
1996
- 1996-06-06 DE DE69617919T patent/DE69617919T2/de not_active Expired - Fee Related
- 1996-06-06 EP EP96830325A patent/EP0811919B1/de not_active Expired - Lifetime
-
1997
- 1997-06-03 US US08/868,213 patent/US5831915A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0811919A1 (de) | 1997-12-10 |
US5831915A (en) | 1998-11-03 |
DE69617919T2 (de) | 2002-08-08 |
EP0811919B1 (de) | 2001-12-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |