DE69534555D1 - Füllen von Löchern und Ähnlichem in Substraten - Google Patents

Füllen von Löchern und Ähnlichem in Substraten

Info

Publication number
DE69534555D1
DE69534555D1 DE69534555T DE69534555T DE69534555D1 DE 69534555 D1 DE69534555 D1 DE 69534555D1 DE 69534555 T DE69534555 T DE 69534555T DE 69534555 T DE69534555 T DE 69534555T DE 69534555 D1 DE69534555 D1 DE 69534555D1
Authority
DE
Germany
Prior art keywords
substrates
filling holes
filling
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69534555T
Other languages
English (en)
Other versions
DE69534555T2 (de
Inventor
Christopher David Dobson
Arthur John Mcgeown
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aviza Europe Ltd
Original Assignee
Aviza Europe Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aviza Europe Ltd filed Critical Aviza Europe Ltd
Publication of DE69534555D1 publication Critical patent/DE69534555D1/de
Application granted granted Critical
Publication of DE69534555T2 publication Critical patent/DE69534555T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Laminated Bodies (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
DE69534555T 1994-07-13 1995-07-04 Füllen von Löchern und Ähnlichem in Substraten Expired - Lifetime DE69534555T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9414145 1994-07-13
GB9414145A GB9414145D0 (en) 1994-07-13 1994-07-13 Forming a layer

Publications (2)

Publication Number Publication Date
DE69534555D1 true DE69534555D1 (de) 2005-12-01
DE69534555T2 DE69534555T2 (de) 2006-07-20

Family

ID=10758272

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69528571T Expired - Lifetime DE69528571T2 (de) 1994-07-13 1995-07-04 Füllen von löchern und dergleichen in substraten
DE69534555T Expired - Lifetime DE69534555T2 (de) 1994-07-13 1995-07-04 Füllen von Löchern und Ähnlichem in Substraten

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69528571T Expired - Lifetime DE69528571T2 (de) 1994-07-13 1995-07-04 Füllen von löchern und dergleichen in substraten

Country Status (7)

Country Link
EP (2) EP1162656B1 (de)
JP (1) JPH09503104A (de)
KR (1) KR100357508B1 (de)
CA (1) CA2171092A1 (de)
DE (2) DE69528571T2 (de)
GB (1) GB9414145D0 (de)
WO (2) WO1996002938A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3277098B2 (ja) * 1994-07-26 2002-04-22 株式会社東芝 半導体装置の製造方法
KR960042974A (de) * 1995-05-23 1996-12-21
GB9619461D0 (en) 1996-09-18 1996-10-30 Electrotech Ltd Method of processing a workpiece
GB2319533B (en) 1996-11-22 2001-06-06 Trikon Equip Ltd Methods of forming a barrier layer
GB2319532B (en) 1996-11-22 2001-01-31 Trikon Equip Ltd Method and apparatus for treating a semiconductor wafer
US20020146896A1 (en) * 2001-04-06 2002-10-10 Yoo Woo Sik Metallizaton methods using foils
JP2002368082A (ja) * 2001-06-08 2002-12-20 Fujikura Ltd 微細空間への金属充填方法および装置
CN113543522A (zh) * 2021-07-09 2021-10-22 广东工业大学 一种基于金属压印的载板填孔工艺
CN113517224A (zh) * 2021-07-09 2021-10-19 广东工业大学 一种通孔、盲孔互连结构成型工艺
CN113543527B (zh) * 2021-07-09 2022-12-30 广东工业大学 载板填孔工艺的填充基材选型方法及载板填孔工艺

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH654793A5 (fr) * 1983-10-03 1986-03-14 Battelle Memorial Institute Siege, notamment pour voiture automobile.
JPS63304636A (ja) * 1987-06-05 1988-12-12 Hitachi Ltd はんだキヤリア及びその製法並びにこれを用いた半導体装置の実装方法
DE69023382T2 (de) * 1989-04-17 1996-06-20 Ibm Laminierungsverfahren zum Überdecken der Seitenwände einer Höhlung in einem Substrat sowie zur Füllung dieser Höhlung.
DE3930743A1 (de) * 1989-09-14 1991-03-28 Roehm Gmbh Waessrige polyacrylat-dispersion als heisssiegelkleber
EP0430040A3 (en) * 1989-11-27 1992-05-20 Micron Technology, Inc. Method of forming a conductive via plug or an interconnect line of ductile metal within an integrated circuit using mechanical smearing
US5011793A (en) * 1990-06-19 1991-04-30 Nihon Shinku Gijutsu Kabushiki Kaisha Vacuum deposition using pressurized reflow process
ATE251342T1 (de) * 1991-05-28 2003-10-15 Trikon Technologies Ltd Verfahren zum füllen eines hohraumes in einem substrat
JPH0529254A (ja) * 1991-07-24 1993-02-05 Sony Corp 配線形成方法
GB9224260D0 (en) * 1992-11-19 1993-01-06 Electrotech Ltd Forming a layer

Also Published As

Publication number Publication date
JPH09503104A (ja) 1997-03-25
WO1996002938A1 (en) 1996-02-01
EP1162656A2 (de) 2001-12-12
EP0719451B1 (de) 2002-10-16
WO1996002939A1 (en) 1996-02-01
EP1162656B1 (de) 2005-10-26
EP1162656A3 (de) 2004-01-28
CA2171092A1 (en) 1996-02-01
KR960705350A (ko) 1996-10-09
KR100357508B1 (ko) 2003-01-24
GB9414145D0 (en) 1994-08-31
EP0719451A1 (de) 1996-07-03
DE69528571D1 (de) 2002-11-21
DE69534555T2 (de) 2006-07-20
DE69528571T2 (de) 2003-07-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition