DE69533857D1 - Sram-cache-speicherverbindunganordnung - Google Patents
Sram-cache-speicherverbindunganordnungInfo
- Publication number
- DE69533857D1 DE69533857D1 DE69533857T DE69533857T DE69533857D1 DE 69533857 D1 DE69533857 D1 DE 69533857D1 DE 69533857 T DE69533857 T DE 69533857T DE 69533857 T DE69533857 T DE 69533857T DE 69533857 D1 DE69533857 D1 DE 69533857D1
- Authority
- DE
- Germany
- Prior art keywords
- cache memory
- connector assembly
- sram cache
- memory connector
- sram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US358798 | 1994-12-19 | ||
US08/358,798 US5604875A (en) | 1994-12-19 | 1994-12-19 | Method and apparatus for removably connecting either asynchronous or burst cache SRAM to a computer system |
PCT/US1995/016487 WO1996019818A1 (en) | 1994-12-19 | 1995-12-18 | A cache sram connector assembly |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69533857D1 true DE69533857D1 (de) | 2005-01-20 |
DE69533857T2 DE69533857T2 (de) | 2005-12-29 |
Family
ID=23411095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69533857T Expired - Lifetime DE69533857T2 (de) | 1994-12-19 | 1995-12-18 | Sram-cache-speicherverbindunganordnung |
Country Status (6)
Country | Link |
---|---|
US (1) | US5604875A (de) |
EP (1) | EP0799490B1 (de) |
AU (1) | AU4601496A (de) |
DE (1) | DE69533857T2 (de) |
HK (1) | HK1003683A1 (de) |
WO (1) | WO1996019818A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5963721A (en) * | 1995-12-29 | 1999-10-05 | Texas Instruments Incorporated | Microprocessor system with capability for asynchronous bus transactions |
US5813029A (en) * | 1996-07-09 | 1998-09-22 | Micron Electronics, Inc. | Upgradeable cache circuit using high speed multiplexer |
US5968139A (en) * | 1996-11-25 | 1999-10-19 | Micron Electronics, Inc. | Method of redirecting I/O operations to memory |
US6119197A (en) * | 1997-10-31 | 2000-09-12 | Micron Technology, Inc. | Method for providing and operating upgradeable cache circuitry |
US6493798B2 (en) | 1998-09-21 | 2002-12-10 | Micron Technology, Inc. | Upgradeable cache circuit using high speed multiplexer |
US7120788B2 (en) * | 2002-06-20 | 2006-10-10 | Intel Corporation | Method and system for shutting down and restarting a computer system |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AT361726B (de) * | 1979-02-19 | 1981-03-25 | Philips Nv | Datenverarbeitungsanlage mit mindestens zwei mikrocomputern |
US4281392A (en) * | 1979-05-01 | 1981-07-28 | Allen-Bradley Company | Memory circuit for programmable machines |
US4500933A (en) * | 1982-04-02 | 1985-02-19 | Ampex Corporation | Universal interface unit |
US5027315A (en) * | 1984-09-28 | 1991-06-25 | Advanced Micro Devices, Inc. | Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions |
JPS63113624A (ja) * | 1986-10-30 | 1988-05-18 | Tokyo Electric Co Ltd | 電子秤のプリンタインタ−フエ−ス |
US5237672A (en) * | 1989-07-28 | 1993-08-17 | Texas Instruments Incorporated | Dynamically adaptable memory controller for various size memories |
US5301343A (en) * | 1990-12-31 | 1994-04-05 | International Business Machines Corp. | System having microprocessor local memory expansion capability through removable coupling of local memory expansion boards directly to the high speed microprocessor local bus |
US5253357A (en) * | 1991-06-13 | 1993-10-12 | Hewlett-Packard Company | System for determining pluggable memory characteristics employing a status register to provide information in response to a preset field of an address |
US5357624A (en) * | 1991-10-23 | 1994-10-18 | Ast Research, Inc. | Single inline memory module support system |
-
1994
- 1994-12-19 US US08/358,798 patent/US5604875A/en not_active Expired - Lifetime
-
1995
- 1995-12-18 WO PCT/US1995/016487 patent/WO1996019818A1/en active IP Right Grant
- 1995-12-18 AU AU46014/96A patent/AU4601496A/en not_active Abandoned
- 1995-12-18 EP EP95944137A patent/EP0799490B1/de not_active Expired - Lifetime
- 1995-12-18 DE DE69533857T patent/DE69533857T2/de not_active Expired - Lifetime
-
1998
- 1998-04-08 HK HK98102961A patent/HK1003683A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE69533857T2 (de) | 2005-12-29 |
HK1003683A1 (en) | 1998-11-06 |
EP0799490B1 (de) | 2004-12-15 |
EP0799490A1 (de) | 1997-10-08 |
EP0799490A4 (de) | 1999-12-29 |
US5604875A (en) | 1997-02-18 |
AU4601496A (en) | 1996-07-10 |
WO1996019818A1 (en) | 1996-06-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |