DE69531933D1 - Busarchitektur in hochgradiger pipeline-ausführung - Google Patents

Busarchitektur in hochgradiger pipeline-ausführung

Info

Publication number
DE69531933D1
DE69531933D1 DE69531933T DE69531933T DE69531933D1 DE 69531933 D1 DE69531933 D1 DE 69531933D1 DE 69531933 T DE69531933 T DE 69531933T DE 69531933 T DE69531933 T DE 69531933T DE 69531933 D1 DE69531933 D1 DE 69531933D1
Authority
DE
Germany
Prior art keywords
high grade
bus architecture
grade pipeline
pipeline version
version
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69531933T
Other languages
English (en)
Other versions
DE69531933T2 (de
Inventor
V Sarangdhar
Gurbir Singh
Konrad Lai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69531933D1 publication Critical patent/DE69531933D1/de
Publication of DE69531933T2 publication Critical patent/DE69531933T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
DE69531933T 1994-03-01 1995-03-01 Busarchitektur in hochgradiger pipeline-ausführung Expired - Lifetime DE69531933T2 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US20638294A 1994-03-01 1994-03-01
US206382 1994-03-01
US39096995A 1995-02-21 1995-02-21
US390969 1995-02-21
PCT/US1995/002505 WO1995024678A2 (en) 1994-03-01 1995-03-01 Highly pipelined bus architecture

Publications (2)

Publication Number Publication Date
DE69531933D1 true DE69531933D1 (de) 2003-11-20
DE69531933T2 DE69531933T2 (de) 2004-08-12

Family

ID=26901290

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69531933T Expired - Lifetime DE69531933T2 (de) 1994-03-01 1995-03-01 Busarchitektur in hochgradiger pipeline-ausführung

Country Status (8)

Country Link
US (1) US5796977A (de)
EP (2) EP0748481B1 (de)
JP (1) JP3660679B2 (de)
KR (1) KR100360064B1 (de)
AU (1) AU1973595A (de)
BR (1) BR9506997A (de)
DE (1) DE69531933T2 (de)
WO (1) WO1995024678A2 (de)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5615343A (en) 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US5673413A (en) * 1995-12-15 1997-09-30 International Business Machines Corporation Method and apparatus for coherency reporting in a multiprocessing system
JPH11501141A (ja) * 1996-03-15 1999-01-26 サン・マイクロシステムズ・インコーポレーテッド 分割トランザクション・スヌーピング・バスおよび調停方法
US5983326A (en) * 1996-07-01 1999-11-09 Sun Microsystems, Inc. Multiprocessing system including an enhanced blocking mechanism for read-to-share-transactions in a NUMA mode
KR100454652B1 (ko) * 1997-04-11 2005-01-13 엘지전자 주식회사 하이파이버스시스템의주기억장치
US6260117B1 (en) * 1997-09-18 2001-07-10 International Business Machines Corporation Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
US6070231A (en) * 1997-12-02 2000-05-30 Intel Corporation Method and apparatus for processing memory requests that require coherency transactions
US6029225A (en) * 1997-12-16 2000-02-22 Hewlett-Packard Company Cache bank conflict avoidance and cache collision avoidance
US6292906B1 (en) * 1997-12-17 2001-09-18 Intel Corporation Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memories
US6460119B1 (en) * 1997-12-29 2002-10-01 Intel Corporation Snoop blocking for cache coherency
US6138218A (en) * 1998-02-17 2000-10-24 International Business Machines Corporation Forward progress on retried snoop hits by altering the coherency state of a local cache
US6330591B1 (en) * 1998-03-09 2001-12-11 Lsi Logic Corporation High speed serial line transceivers integrated into a cache controller to support coherent memory transactions in a loosely coupled network
US6269360B1 (en) * 1998-04-24 2001-07-31 International Business Machines Corporation Optimization of ordered stores on a pipelined bus via self-initiated retry
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6216190B1 (en) * 1998-09-30 2001-04-10 Compaq Computer Corporation System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus
US7555603B1 (en) * 1998-12-16 2009-06-30 Intel Corporation Transaction manager and cache for processing agent
US6732208B1 (en) 1999-02-25 2004-05-04 Mips Technologies, Inc. Low latency system bus interface for multi-master processing environments
US6397304B1 (en) * 1999-06-16 2002-05-28 Intel Corporation Method and apparatus for improving system performance in multiprocessor systems
US6393500B1 (en) 1999-08-12 2002-05-21 Mips Technologies, Inc. Burst-configurable data bus
US6493776B1 (en) 1999-08-12 2002-12-10 Mips Technologies, Inc. Scalable on-chip system bus
US6490642B1 (en) 1999-08-12 2002-12-03 Mips Technologies, Inc. Locked read/write on separate address/data bus using write barrier
US6604159B1 (en) 1999-08-12 2003-08-05 Mips Technologies, Inc. Data release to reduce latency in on-chip system bus
US6681283B1 (en) 1999-08-12 2004-01-20 Mips Technologies, Inc. Coherent data apparatus for an on-chip split transaction system bus
US6519685B1 (en) 1999-12-22 2003-02-11 Intel Corporation Cache states for multiprocessor cache coherency protocols
US6609171B1 (en) * 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
US6681320B1 (en) * 1999-12-29 2004-01-20 Intel Corporation Causality-based memory ordering in a multiprocessing environment
US6438737B1 (en) 2000-02-15 2002-08-20 Intel Corporation Reconfigurable logic for a computer
US6745297B2 (en) * 2000-10-06 2004-06-01 Broadcom Corporation Cache coherent protocol in which exclusive and modified data is transferred to requesting agent from snooping agent
US6546468B2 (en) * 2000-12-27 2003-04-08 International Business Machines Corporation Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update
US6601145B2 (en) 2000-12-27 2003-07-29 International Business Machines Corporation Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls
US6742160B2 (en) 2001-02-14 2004-05-25 Intel Corporation Checkerboard parity techniques for a multi-pumped bus
US6546470B1 (en) 2001-03-12 2003-04-08 International Business Machines Corporation Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers with banked directory implementation
US6546469B2 (en) 2001-03-12 2003-04-08 International Business Machines Corporation Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers
US7076627B2 (en) * 2001-06-29 2006-07-11 Intel Corporation Memory control for multiple read requests
US7114038B2 (en) * 2001-12-28 2006-09-26 Intel Corporation Method and apparatus for communicating between integrated circuits in a low power mode
US7085889B2 (en) 2002-03-22 2006-08-01 Intel Corporation Use of a context identifier in a cache memory
US7343395B2 (en) * 2002-03-29 2008-03-11 Intel Corporation Facilitating resource access using prioritized multicast responses to a discovery request
DE60211874T2 (de) * 2002-06-20 2007-05-24 Infineon Technologies Ag Anordnung von zwei Geräten, verbunden durch einen Kreuzvermittlungsschalter
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US6986010B2 (en) * 2002-12-13 2006-01-10 Intel Corporation Cache lock mechanism with speculative allocation
US7043656B2 (en) * 2003-01-28 2006-05-09 Hewlett-Packard Development Company, L.P. Methods and apparatus for extending a phase on an interconnect
US20040226011A1 (en) * 2003-05-08 2004-11-11 International Business Machines Corporation Multi-threaded microprocessor with queue flushing
US7747733B2 (en) 2004-10-25 2010-06-29 Electro Industries/Gauge Tech Power meter having multiple ethernet ports
US20060143384A1 (en) * 2004-12-27 2006-06-29 Hughes Christopher J System and method for non-uniform cache in a multi-core processor
US7788240B2 (en) * 2004-12-29 2010-08-31 Sap Ag Hash mapping with secondary table having linear probing
US7360008B2 (en) * 2004-12-30 2008-04-15 Intel Corporation Enforcing global ordering through a caching bridge in a multicore multiprocessor system
US7886086B2 (en) * 2005-02-03 2011-02-08 International Business Machines Corporation Method and apparatus for restricting input/output device peer-to-peer operations in a data processing system to improve reliability, availability, and serviceability
US8490107B2 (en) 2011-08-08 2013-07-16 Arm Limited Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels
US10862784B2 (en) 2011-10-04 2020-12-08 Electro Industries/Gauge Tech Systems and methods for processing meter information in a network of intelligent electronic devices
US20170063566A1 (en) * 2011-10-04 2017-03-02 Electro Industries/Gauge Tech Internet of things (iot) intelligent electronic devices, systems and methods
US10771532B2 (en) 2011-10-04 2020-09-08 Electro Industries/Gauge Tech Intelligent electronic devices, systems and methods for communicating messages over a network
US11816465B2 (en) 2013-03-15 2023-11-14 Ei Electronics Llc Devices, systems and methods for tracking and upgrading firmware in intelligent electronic devices
US11734396B2 (en) 2014-06-17 2023-08-22 El Electronics Llc Security through layers in an intelligent electronic device
US10958435B2 (en) 2015-12-21 2021-03-23 Electro Industries/ Gauge Tech Providing security in an intelligent electronic device
US11754997B2 (en) 2018-02-17 2023-09-12 Ei Electronics Llc Devices, systems and methods for predicting future consumption values of load(s) in power distribution systems
US11734704B2 (en) 2018-02-17 2023-08-22 Ei Electronics Llc Devices, systems and methods for the collection of meter data in a common, globally accessible, group of servers, to provide simpler configuration, collection, viewing, and analysis of the meter data
US11686594B2 (en) 2018-02-17 2023-06-27 Ei Electronics Llc Devices, systems and methods for a cloud-based meter management system
US11863589B2 (en) 2019-06-07 2024-01-02 Ei Electronics Llc Enterprise security in meters
US11941428B2 (en) 2021-04-16 2024-03-26 Apple Inc. Ensuring transactional ordering in I/O agent

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353416A (en) * 1989-10-25 1994-10-04 Zenith Data Systems Corporation CPU lock logic for corrected operation with a posted write array
JPH04119445A (ja) * 1990-09-11 1992-04-20 Canon Inc 計算機システム
US5339399A (en) * 1991-04-12 1994-08-16 Intel Corporation Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
US5218564A (en) * 1991-06-07 1993-06-08 National Semiconductor Corporation Layout efficient 32-bit shifter/register with 16-bit interface
US5327570A (en) * 1991-07-22 1994-07-05 International Business Machines Corporation Multiprocessor system having local write cache within each data processor node
US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
GB2260628A (en) * 1991-10-11 1993-04-21 Intel Corp Line buffer for cache memory
US5353415A (en) * 1992-10-02 1994-10-04 Compaq Computer Corporation Method and apparatus for concurrency of bus operations
US5420991A (en) * 1994-01-04 1995-05-30 Intel Corporation Apparatus and method for maintaining processing consistency in a computer system having multiple processors

Also Published As

Publication number Publication date
DE69531933T2 (de) 2004-08-12
EP1215584A3 (de) 2004-04-21
WO1995024678A3 (en) 1995-10-12
EP0748481A1 (de) 1996-12-18
WO1995024678A2 (en) 1995-09-14
JP3660679B2 (ja) 2005-06-15
AU1973595A (en) 1995-09-25
EP0748481A4 (de) 2000-07-05
KR100360064B1 (ko) 2003-03-10
EP0748481B1 (de) 2003-10-15
BR9506997A (pt) 1997-11-18
US5796977A (en) 1998-08-18
EP1215584A2 (de) 2002-06-19
JPH09510308A (ja) 1997-10-14

Similar Documents

Publication Publication Date Title
DE69531933D1 (de) Busarchitektur in hochgradiger pipeline-ausführung
DE69510458T2 (de) Rohrverlegung
BR9509031A (pt) Microestruturas em disposiçao cruzada
DE69426355T2 (de) Umfangreiche Datenbusarchitektur
DE59606218D1 (de) Rohrleitung
DE69516473T2 (de) Inspektionssystem
DE29613522U1 (de) Rohrleitungsmolch
DE29614187U1 (de) Busankoppler
DE29609722U1 (de) Systemverrohrung
DE9403326U1 (de) Rohrleitung
DE69601273T2 (de) Verbesserungen an oder bezüglich Rohrverbindungen
DE9409499U1 (de) Rohrleitungsmolch
DE9409092U1 (de) Rohrleitungsmolch
KR950033779U (ko) 배관연결구
KR960008281U (ko) 버스 승차대
DE9411102U1 (de) Rohrleitung
UA973S (uk) Автобус великий міський
BR7402351U (pt) Disposição introduzida em soroban
BR9604268A (pt) Disposição introduzida em conexão
KR960014984U (ko) 배관구조
SE9503618L (sv) Musplatta
BR7501598U (pt) Disposição introduzida em aragador
BR7500321U (pt) Disposiçao introduzida em bilboque
FI1691U1 (fi) Hopsaettningsmaskin foer lastpallsben
BR7400199U (pt) Disposição construtiva introduzida em apontador

Legal Events

Date Code Title Description
8364 No opposition during term of opposition