DE69510272T2 - Kohärente Transaktionsordnung in einem vielschichtigen Bussystem - Google Patents

Kohärente Transaktionsordnung in einem vielschichtigen Bussystem

Info

Publication number
DE69510272T2
DE69510272T2 DE69510272T DE69510272T DE69510272T2 DE 69510272 T2 DE69510272 T2 DE 69510272T2 DE 69510272 T DE69510272 T DE 69510272T DE 69510272 T DE69510272 T DE 69510272T DE 69510272 T2 DE69510272 T2 DE 69510272T2
Authority
DE
Germany
Prior art keywords
bus system
transaction order
coherent transaction
layered bus
layered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69510272T
Other languages
English (en)
Other versions
DE69510272D1 (de
Inventor
Thomas B Alexander
Kenneth K Chan
Julie W Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Application granted granted Critical
Publication of DE69510272D1 publication Critical patent/DE69510272D1/de
Publication of DE69510272T2 publication Critical patent/DE69510272T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69510272T 1994-05-13 1995-03-28 Kohärente Transaktionsordnung in einem vielschichtigen Bussystem Expired - Lifetime DE69510272T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/242,748 US5524216A (en) 1994-05-13 1994-05-13 Coherent transaction ordering in multi-tiered bus system

Publications (2)

Publication Number Publication Date
DE69510272D1 DE69510272D1 (de) 1999-07-22
DE69510272T2 true DE69510272T2 (de) 2000-01-20

Family

ID=22916029

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69510272T Expired - Lifetime DE69510272T2 (de) 1994-05-13 1995-03-28 Kohärente Transaktionsordnung in einem vielschichtigen Bussystem

Country Status (4)

Country Link
US (1) US5524216A (de)
EP (1) EP0683459B1 (de)
JP (1) JP3698458B2 (de)
DE (1) DE69510272T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761444A (en) * 1995-09-05 1998-06-02 Intel Corporation Method and apparatus for dynamically deferring transactions
US6108735A (en) * 1995-09-29 2000-08-22 Intel Corporation Method and apparatus for responding to unclaimed bus transactions
JP3288261B2 (ja) 1997-06-19 2002-06-04 甲府日本電気株式会社 キャッシュシステム
US5944805A (en) * 1997-08-21 1999-08-31 Advanced Micro Devices, Inc. System and method for transmitting data upon an address portion of a computer system bus during periods of maximum utilization of a data portion of the bus
US6931510B1 (en) * 2000-07-31 2005-08-16 Sun Microsystems, Inc. Method and system for translation lookaside buffer coherence in multiprocessor systems
US7336700B2 (en) * 2001-09-20 2008-02-26 Lockheed Martin Corporation System bus transceiver interface
US7191271B2 (en) * 2001-09-20 2007-03-13 Lockheed Martin Corporation Two level multi-tier system bus
US9622069B2 (en) * 2014-05-21 2017-04-11 Qualcomm Incorporated Systems and methods for multiple network access by mobile computing devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4466060A (en) * 1982-02-11 1984-08-14 At&T Bell Telephone Laboratories, Incorporated Message routing in a computer network
US4719621A (en) * 1985-07-15 1988-01-12 Raytheon Company Packet fastbus
US4853846A (en) * 1986-07-29 1989-08-01 Intel Corporation Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
US4901226A (en) * 1987-12-07 1990-02-13 Bull Hn Information Systems Inc. Inter and intra priority resolution network for an asynchronous bus system
US5142672A (en) * 1987-12-15 1992-08-25 Advanced Micro Devices, Inc. Data transfer controller incorporating direct memory access channels and address mapped input/output windows
US5050066A (en) * 1988-10-14 1991-09-17 Intel Corporation Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus
US5353416A (en) * 1989-10-25 1994-10-04 Zenith Data Systems Corporation CPU lock logic for corrected operation with a posted write array
US5408644A (en) * 1992-06-05 1995-04-18 Compaq Computer Corporation Method and apparatus for improving the performance of partial stripe operations in a disk array subsystem
US5363485A (en) * 1992-10-01 1994-11-08 Xerox Corporation Bus interface having single and multiple channel FIFO devices using pending channel information stored in a circular queue for transfer of information therein
US5367689A (en) * 1992-10-02 1994-11-22 Compaq Computer Corporation Apparatus for strictly ordered input/output operations for interrupt system integrity

Also Published As

Publication number Publication date
US5524216A (en) 1996-06-04
EP0683459A1 (de) 1995-11-22
EP0683459B1 (de) 1999-06-16
DE69510272D1 (de) 1999-07-22
JPH07311714A (ja) 1995-11-28
JP3698458B2 (ja) 2005-09-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE