DE69428428D1 - METHOD AND DEVICE FOR ACCURATE ON / OUT OF THE OUTPUT OF A STORAGE MATRIX - Google Patents
METHOD AND DEVICE FOR ACCURATE ON / OUT OF THE OUTPUT OF A STORAGE MATRIXInfo
- Publication number
- DE69428428D1 DE69428428D1 DE69428428T DE69428428T DE69428428D1 DE 69428428 D1 DE69428428 D1 DE 69428428D1 DE 69428428 T DE69428428 T DE 69428428T DE 69428428 T DE69428428 T DE 69428428T DE 69428428 D1 DE69428428 D1 DE 69428428D1
- Authority
- DE
- Germany
- Prior art keywords
- accurate
- output
- storage matrix
- matrix
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/145,373 US5500818A (en) | 1993-10-29 | 1993-10-29 | Method and apparatus for providing accurate T(on) and T(off) times for the output of a memory array |
| PCT/US1994/012356 WO1995012202A1 (en) | 1993-10-29 | 1994-10-27 | METHOD AND APPARATUS FOR PROVIDING ACCURATE T(on) AND T(off) TIMES FOR THE OUTPUT OF A MEMORY ARRAY |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE69428428D1 true DE69428428D1 (en) | 2001-10-31 |
| DE69428428T2 DE69428428T2 (en) | 2002-06-20 |
Family
ID=22512811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE69428428T Expired - Fee Related DE69428428T2 (en) | 1993-10-29 | 1994-10-27 | METHOD AND DEVICE FOR ACCURATE ON / OUT OF THE OUTPUT OF A STORAGE MATRIX |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5500818A (en) |
| EP (1) | EP0677204B1 (en) |
| JP (1) | JP3421347B2 (en) |
| KR (1) | KR100342731B1 (en) |
| DE (1) | DE69428428T2 (en) |
| WO (1) | WO1995012202A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6088774A (en) | 1996-09-20 | 2000-07-11 | Advanced Memory International, Inc. | Read/write timing for maximum utilization of bidirectional read/write bus |
| US6040998A (en) * | 1998-08-11 | 2000-03-21 | Siemens Aktiengesellschaft | Memory activation devices and methods |
| KR100401509B1 (en) * | 2001-05-31 | 2003-10-17 | 주식회사 하이닉스반도체 | Sense amp circuit of semiconductor memory device |
| US20050102476A1 (en) * | 2003-11-12 | 2005-05-12 | Infineon Technologies North America Corp. | Random access memory with optional column address strobe latency of one |
| CN112422116A (en) * | 2019-08-23 | 2021-02-26 | 长鑫存储技术有限公司 | Multi-stage driving data transmission circuit and data transmission method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60115092A (en) * | 1983-11-28 | 1985-06-21 | Nec Corp | Semiconductor storing circuit |
| EP0194939B1 (en) * | 1985-03-14 | 1992-02-05 | Fujitsu Limited | Semiconductor memory device |
| JPS62103893A (en) * | 1985-10-30 | 1987-05-14 | Toshiba Corp | Semiconductor memory |
| JP2735268B2 (en) * | 1989-02-22 | 1998-04-02 | 日本電気株式会社 | LSI output buffer |
| KR930006228B1 (en) * | 1990-07-20 | 1993-07-09 | 삼성전자 주식회사 | Signal delay circuit |
| JPH04172711A (en) * | 1990-11-06 | 1992-06-19 | Mitsubishi Electric Corp | Semiconductor delay circuit |
| US5313422A (en) * | 1991-05-29 | 1994-05-17 | Texas Instruments Incorporated | Digitally controlled delay applied to address decoder for write vs. read |
-
1993
- 1993-10-29 US US08/145,373 patent/US5500818A/en not_active Expired - Fee Related
-
1994
- 1994-10-27 KR KR1019950702480A patent/KR100342731B1/en not_active IP Right Cessation
- 1994-10-27 WO PCT/US1994/012356 patent/WO1995012202A1/en active IP Right Grant
- 1994-10-27 JP JP51283495A patent/JP3421347B2/en not_active Expired - Fee Related
- 1994-10-27 DE DE69428428T patent/DE69428428T2/en not_active Expired - Fee Related
- 1994-10-27 EP EP95900454A patent/EP0677204B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69428428T2 (en) | 2002-06-20 |
| US5500818A (en) | 1996-03-19 |
| JPH09506458A (en) | 1997-06-24 |
| EP0677204A4 (en) | 1996-11-13 |
| KR950704787A (en) | 1995-11-20 |
| KR100342731B1 (en) | 2002-11-29 |
| EP0677204B1 (en) | 2001-09-26 |
| JP3421347B2 (en) | 2003-06-30 |
| EP0677204A1 (en) | 1995-10-18 |
| WO1995012202A1 (en) | 1995-05-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |