DE69422018D1 - Schnittstellenvorrichtung - Google Patents

Schnittstellenvorrichtung

Info

Publication number
DE69422018D1
DE69422018D1 DE69422018T DE69422018T DE69422018D1 DE 69422018 D1 DE69422018 D1 DE 69422018D1 DE 69422018 T DE69422018 T DE 69422018T DE 69422018 T DE69422018 T DE 69422018T DE 69422018 D1 DE69422018 D1 DE 69422018D1
Authority
DE
Germany
Prior art keywords
interface device
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69422018T
Other languages
English (en)
Other versions
DE69422018T2 (de
Inventor
Trevor Edward Willis
Adrian Suggett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Madge Networks Ltd
Original Assignee
Madge Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Madge Networks Ltd filed Critical Madge Networks Ltd
Application granted granted Critical
Publication of DE69422018D1 publication Critical patent/DE69422018D1/de
Publication of DE69422018T2 publication Critical patent/DE69422018T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Communication Control (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
DE69422018T 1993-01-19 1994-01-18 Schnittstellenvorrichtung Expired - Fee Related DE69422018T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB939300913A GB9300913D0 (en) 1993-01-19 1993-01-19 Interface apparatus
PCT/GB1994/000094 WO1994017476A1 (en) 1993-01-19 1994-01-18 Interface apparatus

Publications (2)

Publication Number Publication Date
DE69422018D1 true DE69422018D1 (de) 2000-01-13
DE69422018T2 DE69422018T2 (de) 2000-04-27

Family

ID=10728891

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69422018T Expired - Fee Related DE69422018T2 (de) 1993-01-19 1994-01-18 Schnittstellenvorrichtung

Country Status (7)

Country Link
US (1) US6351725B1 (de)
EP (1) EP0680636B1 (de)
JP (1) JPH08505726A (de)
CA (1) CA2152474C (de)
DE (1) DE69422018T2 (de)
GB (1) GB9300913D0 (de)
WO (1) WO1994017476A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3635169B2 (ja) * 1996-11-20 2005-04-06 松下電器産業株式会社 データ伝送装置
US7382736B2 (en) * 1999-01-12 2008-06-03 Mcdata Corporation Method for scoring queued frames for selective transmission through a switch
JP5220974B2 (ja) 1999-10-14 2013-06-26 ブルアーク ユーケー リミテッド ハードウェア実行又はオペレーティングシステム機能の加速のための装置及び方法
JP2003067321A (ja) * 2001-08-28 2003-03-07 Hitachi Ltd データ転送装置及び該データ転送装置内に具備されるアライナ
US7457822B1 (en) * 2002-11-01 2008-11-25 Bluearc Uk Limited Apparatus and method for hardware-based file system
US8041735B1 (en) 2002-11-01 2011-10-18 Bluearc Uk Limited Distributed file system and method
CN1300686C (zh) * 2004-07-20 2007-02-14 华为技术有限公司 一种sdh类逻辑仿真激励数据缓存方法
US7917671B2 (en) * 2007-12-18 2011-03-29 Nvidia Corporation Scalable port controller architecture supporting data streams of different speeds
US9003369B2 (en) 2011-08-31 2015-04-07 Nvidia Corporation HDMI-muxed debug port methods and apparatuses

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4841435A (en) 1986-10-29 1989-06-20 Saxpy Computer Corporation Data alignment system for random and block transfers of embedded subarrays of an array onto a system bus
EP0290172A3 (de) * 1987-04-30 1991-01-16 Advanced Micro Devices, Inc. Zweirichtungsfifo mit variabler Byte-Begrenzung und Datenpfadbreitenänderung
US5168561A (en) * 1990-02-16 1992-12-01 Ncr Corporation Pipe-line method and apparatus for byte alignment of data words during direct memory access transfers
GB2264845B (en) * 1992-02-28 1995-09-20 Texas Instruments Ltd Local area network adaptive circuit for multiple network types
US5299313A (en) * 1992-07-28 1994-03-29 3Com Corporation Network interface with host independent buffer management

Also Published As

Publication number Publication date
DE69422018T2 (de) 2000-04-27
WO1994017476A1 (en) 1994-08-04
EP0680636A1 (de) 1995-11-08
JPH08505726A (ja) 1996-06-18
US6351725B1 (en) 2002-02-26
EP0680636B1 (de) 1999-12-08
CA2152474C (en) 1999-12-21
CA2152474A1 (en) 1994-08-04
GB9300913D0 (en) 1993-03-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MADGE NETWORKS LTD., WEXHAM, SLOUGH, GB

8339 Ceased/non-payment of the annual fee