DE69333798T2 - METHOD AND DEVICE FOR ARBITRATING ON AN AZYCLICAL-TARGETED GRAPH - Google Patents

Description

BACKGROUND OF THE INVENTION

Related registrations

These Application is related to U.S. Patent No. 5,394,556 "A method and a facility for a unique address assignment, a node self-identification and a topology image for a directed acyclic graph ".

Territory of invention

The The present invention relates to computer systems. Especially The present invention relates to a method of forming and Use of a communication scheme between a plurality of arbitrarily assembled elements of a computer system.

background

components in a given computer system need the ability to communicate with each other to convey. In very simple systems it is possible to use every element of the system to wire directly to all other parts of the system. To computer expandable and to record an unknown number of system parts, however Computer architects actually developed the concept of a communication bus a long time ago.

One Bus is a communication path, such as one through the computer system running wire or wires. Each component of the system only needs to be connected to the bus to theoretically associated with every other component in the system be. Naturally not every component can communicate with other components at the same time, because there is only one communication channel between the components can give. When using a communication bus, the education is any type of access arrangement required so that each component the bus to communicate with other components in an efficient Can use the way in which crucial information not blocked by a component that is on a bus access waiting. The procedure whereby components on the bus die Bus sharing is commonly referred to as a bus arbitration scheme.

A execution of an arbitration scheme is on Distributed in the 11th International Conference Computing Systems, Arlington, Texas, USA, May 1991, entitled "A Dag-Based Algorithm for Distributed Mutual Exclusion "by M. L. Nelson and M. Mizumo. The scheme described is based on a token [allocation marker] -based Distributed mutual algorithm, which is a fully connected Network and a structured as a directed acyclic graph logical network requires.

In addition to the crucial need to optimize the bus arbitration scheme for one Maximizing the flow of important information can and should the physical (and logical / electrical) configuration of the bus itself for one Minimization of system delays be optimized while remaining as flexible as possible.

Around to communicate with other components connected to a bus, Each component must be equipped with hardware, such as with one with the for the bus implemented communication protocol compatible transmit and receiving circuit. Such a communication standard is in IEEE Standard Document P1394 entitled "High Performance Serial Bus" This document is attached as Annex A to this document. Of the standard described in P1394 is for a provision of a inexpensive connection between cards on the same bus circuit board, Cards on other bus boards and external peripherals certainly.

buses and prior art networks required the knowledge what was connected where. The back of many computers points for example, fixed ports for certain peripherals. Some computers have multiple buses such as the Macintosh, one called ADB Bus for Components like a mouse and a keyboard and a SCSI bus for others Peripheral equipment used. These types of buses provide one Chaining elements ready. However, the compounds have a limited topology. Other known buses / networks require that the nodes of the network are arranged in a ring, one Loop that must be closed to effectiveness. At long last require star or spoke [hub-and-spoke] arrangements that every node directly with a central main facility [master] is connected. Each of the prior art systems is missing a desired one Measure Flexibility.

It would be desirable to be able to and therefore is an object of the present Invention, elements of a computer system on a bus arbitrary through which system any topology can be separated into a working system, without one Require predetermined arrangement of components.

SUMMARY THE INVENTION

In an embodiment will be a procedure for a fair bus access arbitration according to claim 1 described. In a further embodiment will be a procedure for a fair bus arbitration according to claim 11 described. In a further embodiment, a method a token forwarding bus access arbitration according to claim 13 described. In a further embodiment, a method the preemptive Businitialisierung according to claim 14 described.

It It is an object of the present invention to provide a fair bus access arbitration scheme for one To provide a computer system bus or a network in which the Connect the nodes to an acyclic directed graph disbanded were.

It Another object of the present invention is a method a token passing bus arbitration for a Computer system bus or provide a network in which the connections the node has been resolved into an acyclic directed graph.

It Yet another object of the present invention is a mechanism to provide a preemptive bus initialization by each Nodes in a network of nodes are triggered can be resolved into an acyclic directed graph, if errors are detected or nodes added during operation or be removed.

These and other objects of the present invention are in one system executed in which an arbitrary arrangement of nodes on a system bus in an acyclic directed graph was resolved. The hierarchical Arrangement of nodes has a node called root on, while all other node parent / child relationships are formed with the nodes have with whom they are connected. Each node may have a plurality Connected child ports with a predefined confirmation priority scheme have formed. A fair bus access arbitration is considered a bus grant in a sequence corresponding to the predetermined port priorities, which allows all nodes a turn on the bus. The root node can always his priority access status claim for the bus access. This is useful, to accommodate a root node, which is an isochronous data transfer needed. Alternatively, a token forwarding arbitration scheme accomplished where the token is for the bus access around the nodes according to the above, before fixed priority scheme the ports forwarded. A preemptive bus initialization can be required by any node in capturing this making mistakes or adding or removing one Connection to an existing node will be triggered.

BRIEF DESCRIPTION OF THE DRAWINGS

The Objects, features and advantages of the present invention from the following detailed description, in the:

1 FIG. 12 illustrates a block diagram of the hardware layer implementation used in accordance with the present invention. FIG.

2 (a) - 2 B) illustrate an arbitrarily assembled collection of nodes. One is acyclic and the other includes several cycles.

3 (a) shows the arbitrarily arranged collection of nodes from 2 (a) which is subjected to the graph transformation method according to the present invention.

3 (b) - 3 (d) illustrate alternative communication capabilities between the nodes in the practice of the present invention.

3 (e) graphically illustrates the directed graph resulting from the arbitrarily assembled network of nodes of 2 (a) results.

4 illustrates a symmetric graph arrangement that requires resolution of a root contention.

5 illustrates a directed acyclic graph, indicating a possible unique address assignment order.

6 (a) - 6 (e) illustrate the process flow for performing the graph transformation method according to the preferred embodiment of the present invention.

DETAILED DESCRIPTION THE INVENTION

A method and apparatus for using a bus having any topology is described. In the following description, many specific details are set forth, such as various computer components, to provide a thorough understanding of the present invention. It will ever however, it will be apparent to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known control structures and coding techniques have not been described in detail so as not to unnecessarily obscure the present invention.

Everywhere in These detailed descriptions are numerous descriptive Terms introduced to to provide a metaphorical overview of the description. For example, they are common covers on parent-child relationships between the nodes in a given Topology made. The purpose of this is to provide the concept the "direction" to the end resolved Graph. As will be described, it will, as soon as any Topology has been reduced to an acyclic directed graph, one referred to as the "root" node Give knots. The root node will not have a parent node. All nodes immediately adjacent to the root node are the child nodes of the root node. The "tree" metaphor is incorporated by inclusion of nodes called "branches" and "leaves" completed.

Even though the bus architecture described herein with respect to components for one Single computer is described, it generally has an extended Scope. The present invention for defining the bus topology may on any collection of interconnected collections Nodes are applied, such as in a network of Institutions. One point to note is the need for differentiation a node of a physical computer component. each on-the-bus component becomes at least one node controller assigned to the physical layer. Under certain circumstances For example, a given component may suitably have multiple nodes be assigned. Normally, however, it will be a one-to-one correspondence between the facilities or components on the bus and the Give knots.

It will be up now 1 Reference is made to a block diagram of a node 10 is illustrated. The physical execution of a node is quite arbitrary. In the embodiment of the preferred embodiment of the invention, the nodes are designed to comply with the IEEE P1394 High Performance Serial Bus communication protocol, which is attached as Appendix A. The knot 10 includes an arbitration machine logic 11 , This arbitration engine logic contains the entire logic circuitry for carrying out the methods and algorithms to be described herein. The circuit may include a programmable logic device (PLA) or may be specifically designed to perform the functions described herein. Once the functions to be performed by the node logic are described, those skilled in the art will, without undue experimentation, be able to practice the present invention. The node, through its logic, is to execute the minimum arbitration protocol, which includes bus initialization, tree identification, self-identification, and bus arbitration functions. All are described in detail below.

The in 1 shown knots 10 also includes transmission multiplexer 12 and 13 and a data transmitter, receiver and resynchronizer 14 , The in 1 illustrated node is with the local host 15 coupled. The local host 15 may be any device that one wishes to connect to the bus, such as a disk drive, a CPU, a keyboard, or any other component that needs to communicate with other components in the system. The knot 10 communicates via communication links with other nodes. A connection is a coupling between two ports and in practical terms a cable segment. In general, however, it can be implemented as any physical communication channel. A connection should at least be able to provide a half-duplex communication channel between the two ports connecting it. A port is the interface between a node and a connection. According to the present invention, a port must have the ability to send and receive data and arbitration signaling. A port must be able to determine if it is connected to another port or not. One method that allows this is to apply a bias voltage across the connection to the connected ports that is detectable by the port at the other end of the connection. Thus, if a port has a connected connection that is not connected to a port on the other end, an open connection, the port will determine that it is not a connected port. In 1 has the illustrated node 10 three external ports 21 . 22 and 23 with the connections 17 . 18 respectively 19 on.

One of the execution rules for nodes for practicing the present invention is that a node may have one or more ports. A node should be able to send and receive data on each of its ports. A node should be able to receive data on exactly one of its shared ports and be able to retransmit that data on all remaining shared ports. A node is intended for simultaneous and independent reception and transmission of signals be able to transmit messages over all its ports. Each port of a node requires separate signaling transceiver devices, encoders and decoders. A minimum execution node does not require a local host facility. Such a node may, for example, function as a cable extension. From there, facilities and local hosts are ignored, and all references to a bus topology will refer to nodes and node connections through different ports.

graph transformation

2 (a) and 2 B) illustrate arbitrarily assembled collections of nodes. From here, nodes are shown as circles only. However, it is assumed that each contains elements related to those 1 correspond described. Note, however, that each node may have more or less than the three external ports shown in this figure. The illustrated lines connecting each of the nodes are the method by which connections are shown. Ports are not illustrated but are implied, the interface through which a connection and a node connect.

The bus arbitration method described here requires that the arbitrary topology be resolved into an acyclic directed graph. In a graph of arbitrary topology, a collection of nodes and links can be one cycle. A cycle exists when it is possible to return to the same node by traversing links and nodes after starting from a particular node in the graph, without traversing any link twice. 2 (a) illustrates an acyclic graph because none of the illustrated nodes are connected within a loop. 2 B) however, is not an acyclic graph, as the range in the character box 25 a collection of nodes 40 - 47 contains, which form several cycles. The bus arbitration method to be described requires that there are no cycles. Therefore, a method of user intervention for resolution of cycles will be described below.

In addition to the requirement that a graph be acyclic, it must also be directed. A directed graph is a graph in which a hierarchical arrangement has been formed between adjacent nodes. First, there are no parent-child relationships between the nodes. That is, knots 31 For example, the "parent node" may be for nodes 34 or the "child node" for nodes 34 be. In this way, it is necessary to take a given graph of arbitrary topology and transform it into an acyclic and directed graph. The method described here will function to perform this transformation for any given topology, regardless of the number of nodes or their physical connection, and regardless of the signaling propagation time along the links.

Node communication

First, the transformation process of an acyclic graph of arbitrary topology into a directed graph will be described. It will be followed by the case where the resolution of a cycle is required. 3 (a) shows the arbitrary graph of 2 (a) in which the nodes and the links have status labels and the communicated signals are given to the graph transformation process to align a graph. It is instructive at this point to describe the signal communication between the nodes. 3 (b) illustrates two through the connection 52 coupled knots 50 and 51 (hereinafter node A or node B). As described, the connection is the communication channel comprising the transmitter-receiver ports of the respective nodes as described above with reference to FIG 1 described coupled. During the graph transformation process, the nodes will require the formation of parent-child relationships with neighboring nodes. Two nodes are considered adjacent nodes if there is at least one connection formed between a port of the first node and a port of the second node. In the 3 (b) - 3 (d) It will be assumed that the relationship to be resolved is that node B is the parent of node A and that the formation of this relationship is appropriate for the nodes.

If it is appropriate for node A to establish node B as its parent node prior to the establishment of a direction, node A will become disconnected from it 52 The content of this message may take some form as long as node A knows that it is signaling YAMP and node B is able to understand that the message being received is YAMP If the YAMP signal 53 from node B, node B becomes node A by sending "you are my child node" (YAMC) over the connection 52 answer to node A. The arbitration machine logic 11 from node A, the time delay between the transmission of the YAMP signal 53 and receiving the YAMC signal 54 observe. The measured time indicates twice the propagation delay between nodes A and B. Upon receipt of the YAMC signal, node A becomes a "you are my acknowledged child node" (YAMCA) signal 55 reply. This also gives node B the ability to determine the off time delay between the nodes equal to the time delay between the transmission of YAMC and the reception of YAMCA. For half duplex communication links, the YAMCA message also has the effect of correctly orienting the communication channel.

For full-duplex communication channels, the three logical messages YAMP, YAMC and YAMCA can alternatively be forwarded by only two signal transmissions. In 3 (c) This situation is illustrated in which node A is the YAMP signal 56 continuously applies until it receives the return signal YAMC 57 receives. The YAMCA signal is logically transmitted to node B when it is detected that the YAMP signal is no longer arriving.

The Use of this described triple asynchronous message exchange provides a mechanism through which both in the message exchange embedded nodes determine the propagation time delay through the connection can. This delay value will at the resolution from contention events to be further described hereinafter, as well as during normal bus arbitration to optimize bus performance used. The dynamic decoupling of this parameter is not absolutely necessary. As an alternative, at the expense of optimal performance of the bus a maximum propagation time delay a priori be defined.

Once nodes A and B have exchanged tags for identification that node B is the parent node of node A, the connection may be considered addressed. Within its logic, node A denotes its port, with which the connection 52 is coupled as a parent port (he speaks to a parent node) and node B identifies his port to which the connection 52 coupled as a child port (he speaks to a child node). Maintaining the names obtained from the ports is important because the methods to be described below are illustrated by the designations assigned to the nodes and ports at a set time. A shorthand of a graphical notation is in 3 (d) illustrated in which the directional arrow 58 indicates that node B is formed as the parent node of node A and the connection is directed.

direction determination

It will be up again 3 (a) and the processing 6 (a) - 6 (e) Referenced. Now the process of aligning the entire arbitrary topology is described. To help explain the topology transformation process, it is necessary to introduce a few more descriptive definitions. First, a "leaf" node is defined as a node with only one connected port A node recognizes its status as a leaf node as soon as it is initialized after power-up or other bus initialization has at least two connected ports. Over all but one of the connected ports, a branch node will have received the YAMP signal and confirmed it. Over its remaining port, a branch node sent the YAMP signal. This establishes that it has a parent node. A node does not reach a branch state until it has established that it has a parent node (a node can only have one parent node) and all its other ports are connected to child nodes. Prior to reaching the branch status, a node is considered to be a "cycle" node because, until it is designated as a branch, there is the possibility that the node is part of a cycle that makes the formation of a direction impossible.

The graph transformation process begins in step 60 at bus initialization (at power up or on cause), at what time the leaf nodes in any topology in step 61 recognize yourself and by a determination in the decision symbol 66 that they only have one connected port, themselves in step 68 mark as leaf node. In the in 3 (a) Graphically represented graphs are the nodes 33 . 35 . 36 and 37 Leaf nodes, once initialized, each in step 69 transmit the YAMP signal to its neighboring node via its single connected port. The nodes receiving these signals will then be in step 70 distribute the YAMC signals back to the leaf nodes. In this way, a direction is established for the given connection between the corresponding parent-child pairs when the YAMCA communication is finished. In step 71 Each leaf node designates its single connected port as a parent port and each receive port on the parent node is referred to as a child port.

The nodes on the graph that are not initially leaf nodes are initially considered "cycle nodes" for the reason described above and run according to the cycle node method 63 from. Each cycle node that has named all but one of its connected ports as child ports then propagates in step 85 YAMP signal from its remaining, unsigned port. When this direction is established for the connection, the cycle node is referred to as a branch node. After the leaf node 37 node 34 has formed as its parent node, thus knots 34 only an unspecified port (it has the connection to nodes 37 than about one Child port running). Therefore, the node sends 34 the YAMP signal to node 31 , This causes nodes 34 becomes a branch node. As soon as knot 31 has identified that the nodes 33 and 34 his children are sending knots 31 as well as the YAMP signal to node 30 , If a node in the decision icon 75 Through all its ports the YAMP signal has been received, the node becomes the root node. After knots 30 in 3 (a) the YAMP signals from the nodes 31 and 32 its name changes from that of a cycle node to that of a root node. In the graph of 3 (a) It is not necessarily the case that node 30 would become the root node. If some of the connections in the tree had provided large propagation delays, then node could 30 received a YAMP signal on one port and then sent a YAMP signal over its other port. Each of the nodes can become the root node, even a leaf. The role property has priority. 3 (e) shows the resulting directional graph in response to the in 3 (a) shown, communicated signals. Each node is labeled and the directions are marked by dark arrows.

Root competition

Under certain circumstances, a root contention situation may occur. This may occur, for example, in the case where the arbitrary topology has a symmetric arrangement, such as those in FIG 4 . shown In the in 4 Any graphs illustrated have the nodes 160 and 161 each set up as parents for the two leaf nodes to which they are coupled. Then everyone spread the YAMP signal to the other at about the same time. The root contention situation is affected by both involved nodes in the decision symbol 86 recognized. Each node receives a signal that designates it as a parent node while sending the same signal over the same port. Each of the competing nodes responds in step 91 the other with the YAMC signal. This allows each to determine the "decision time period" equal to twice the propagation time between the nodes.

The root contention situation is resolved by the use of a random decision mechanism, which in each arbitration automaton logic unit 11 every node is included. For each expiring "decision time period", each node in step 92 randomly decide (with a 50% chance) whether to retransmit the YAMP signal to the other one. Almost certainly, within a finite number of cycles, a node will choose to commit the other as its parent node without responding. The node set as the parent node will be in step 95 the root node. Alternatively, nodes can be assigned predefined values for the selection criteria. The larger or smaller one determines which dominates in a contention event. Although dynamic determination of the "decision time period" provides optimum performance, it is not required in the practice of the present invention. "As an alternative, an a priori defined" decision time period "may be used as long as it is greater than the worst case bus used in any algorithm is encountered connection propagation. The same method used to resolve root contention situations is also used to resolve other contention events described below.

Root Assignment

As described above is the result of the graph transformation process the assignment of the root attribute to exactly one node in the graph. The root node will be described in the bus arbitration scheme the final Have a decision. He can therefore without a use of special Priority time gaps with maximum priority access the bus. It is often desirable to be able to be to a given node to optimize a given system either in its manufacture or dynamically (during the Runtime) to assign the Roots property. A given bus can comprise a node requiring isochronous data transmission. isochronous Data is data that is transmitted at a specified time have to be around to be of value. For example, music from a CD in the too hearing Order and without significant delays being transmitted and output. In contrast, you can Transfer data files piecemeal and not have to necessarily be transmitted in the order.

Nodes can be classified into three categories in terms of root names. These designations may be provided during manufacture by hard-wiring the designation in the device, by programming the arbitration automation logic, or by higher level software that makes the decision and then initiates a restart while maintaining that decision. The three names that can be assigned to a node in terms of its root designation are: nodes that do not want to be root nodes, nodes that can (should) be a root node, and nodes that have a root node Should be knots. These terms will be in the steps 81 and 83 ge reviewed. A node designated in the first category will begin the graph transformation process as soon as instructed to do so. This will usually be done immediately after completing the bus initialization procedure. A node of the second category will delay the start of the graph transform process by a predetermined amount of time after it starts to process in step 84 was instructed. This delay increases the node's chance of becoming root nodes. (Due to the delay, the propagation of the YAMP signals to it is more likely.) Despite the added delay, it is still possible that a "can not be root" node will end up with its root name, as determined by the given topology The amount of delay may be defined during the design to be greater than a reasonable worst propagation delay over a fairly complex graph.

A node of the third category of root naming capabilities can only recognize the fact that it must be the root node after the graph has already been transformed and all nodes have identified themselves. This determination may be made by the arbitration engine logic or software running on the host system. When this occurs, the node, which must be the root node, agrees with all other nodes on the bus that it will be the sole root node and restarts the graph transformation process by signaling a preemptive bus initialization signal, further described herein. The node then waits in step 82 to become root node and does not participate in the graph transformation until it has received the YAMP signal on all its ports. In this way, he enforces his name as root.

As soon as the root node has been determined, the graph may be considered directional. There is a defined relationship between all neighboring nodes exists on the graph.

cycle resolution

The graphene alignment methods described above will only work for an acyclic graph. If there are cycles in any topology, they must go through that in step 80 beginning procedures are interrupted. The existence of a cycle is in step 79 detected when, after the lapse of a predetermined timeout period, a node is still referred to as a cycle node rather than a leaf, branch or root. The "cycle detect" timing begins immediately after the bus initialization function ends, and the timeout period need not be longer than the worst duration of the graph transform process (adding the delay time for a "can be root" node and a possible root contention event).

The "cycle detection timeout event" does not have to be synchronous for all Nodes of a graph occur because all message exchanges are asynchronous events. Therefore, for a node that is not yet has reached its "cycle detection timeout event", the Reception of a message possible, the one running cycle resolution displays. Such a node becomes its cycle detection timeout interval and start the appropriate cycle resolution process.

The method of cycle resolution according to the present invention requires intervention of the user of the compiled node collection. When a node encounters a "cycle capture" timeout, the system user may, in step 100 from 6 (a) be notified via an output device that a cycle exists and which nodes are involved. The user is then instructed to disconnect to eliminate any existing cycles. The user will then return control to the graph transformation process.

As soon as each of the loops is interrupted and no cycles remain, can be the method of transformation of the graph, as in the previous sections, continue until the whole Graph is both acyclic and directed.

Unique physical address assignment

Once a directed acyclic graph is formed from the original, arbitrary topology, the assignment of unique physical addresses to each node on the graph is possible. This process begins with all leaf nodes requesting the bus through the transmission of the Bus Request (BR) signal over their single connected port. The parent node receiving the signal will wait for all of its child ports to receive the BR signal and then propagate the BR signal to its parent node. The BR signals will propagate through the graph until the root node has received the BR signal from all its children. Once the root node has received a bus request across all of its child ports, it will make a decision to grant the bus over a port and propagate a bus denial (BD) signal over its remaining child ports. The procedure to choose which bus request to grant may be an a priori decision, such as that described above, in which, for example, ports are selected from left to right or based on port numbering, etc. The bus grant (BG) signal is transmitted from the root node to its requesting child. If this requesting child is itself a parent node that has propagated the bus request of one of his children, he will send the bus refusal signal over all but one of his child ports in the same predetermined manner described above. Finally, a leaf node will receive the bus grant signal, to which it will respond with a bus grant acknowledged (BGA) signal which is propagated back to the root node. The propagation of the BD and BGA signals serves to orient the communication links, which may be necessary in the case of half-duplex communication channels. All denied nodes will then wait for an activity of the node which will eventually receive the BG signal.

The node that has finally been granted access to the bus is sent an address assignment packet. The node will transmit this packet onto the bus and it will be received by all other nodes, each of which will count the number of address packets they receive. The transmitted address packet may have any arbitrary information. The unique physical address of a node will be based on the number of address packets a node has counted before transmitting an address packet. As a result, no two nodes will receive the same physical address even though no address information has been assigned in advance. The actual composition of the address packet is arbitrary and can be any bitstream that can be efficiently used by the system. After transmission of the physical address assignment packet, a node will transmit a "child ID complete" (CIC) signal, and the parent node receiving this on its child port will then transmit the "child ID full acknowledgment" (CICA) signal and designate the port as an identified child port. In response to the next BR signal propagation, the parent node of the node that has just identified itself will select its next child node to transmit the physical address packet. Once all child nodes of a parent node have identified, the parent node will request the bus. If granted the bus, he will propagate his physical address allocation packet. This procedure continues following the predetermined selection criterion until all nodes determine a unique physical address assignment by counting. 5 illustrates the graph of 3 (e) in which a predefined left-to-right selection criterion is executed. The nodes are uniquely assigned addresses, where the node 33 receives the first address and the root node 30 as described the eighth and last address receives.

If This process is completed, every node in the graph have a unique physical address that is not in advance must be determined and the for the system management or other purposes can be used.

Node self-ID

The Method of self-identification of the nodes essentially follows the same routine as the above-described method of Assignment of the physical address. Because every node has its assignment packet the physical address transmits, can this package will include more information, such as the Identification of the physical device that identifies of the node belonging to local host has how much energy he requires and for example if he is a "soft power-on "[controlled Power on] attribute supports etc. In fact you can the self-identification information of the nodes as the assignment packet of physical address serve as the method of sending any Information at all base for the counting to provide unique physical addresses.

In Regarding the self - identification package of the nodes, the certain information concerning the node only from those Nodes are "listened" through the nature of the announcing node are concerned. As in the preceding, this procedure continues until all nodes transmit their information to the node self-identification to have.

topology mapping

The Topology imaging follows the same way as the physical address assignment and node self-identification. Consequently, in this method transmits every node, if by the method of address assignment or the node self-identification goes, more, all its ports relevant information, such as the number of its child ports and whether or not it has any disabled ports. With regard to the deactivated ports, the execution of a communication protocol between deactivating ports be desirable, so they can identify from whom they were deactivated. Consequently, a port, if he identifies a disabled port, provide an identifier that shows both its own ID and the ID of the port from which he was deactivated.

By the compilation of all during the Topology imaging method received topology information about all Ports can the bus server, the host, or any software layer application the resolved ones Logically reconstruct bus topology. This is useful for many purposes the execution of redundancy, in case of unexpected collapse a compound previously disabled compounds for prevention the loss of communication channels to any nodes can serve.

Fair bus access arbitration

As soon as the routines of topology mapping, node self-identification or assignment of the Physical addresses are completed, the bus may be ready and be considered in operation. One according to the present invention executed Arbitration scheme is that of a fair bus access. If a node wants access to the bus, he sends over its parent port (if it is not the root node) a Bus Request (BR) signal. The parent node sends on receipt of the BR signal from a child node a bus denied signal (BD) via all his other childports. The parent node then spreads that BR signal up over his Parent node until the signal reaches the root node. The root node gives in response to the first received BR signal, asserts and transmits a bus grant signal (BG) the BD signal over all his other, down sprawling child sports. This will orient the connections. The BG signal spreads downhill through the graph until reaching the requesting node, which then followed the bus acknowledged (BR) signal sends from the information packet whose transmission the node needed the bus. When the package is complete, all nodes go into hibernation back or enter him.

If the root node receives bus requests almost simultaneously the predefined selection criteria for the root node to grant the Bus access for one of the nodes used. This can be the same predetermined, as the priority selection criteria described above be.

One Another aspect of fair bus access arbitration is the priority of one Parent node opposite his child node. Thus, if a parent node needs the bus, send he gets the BD signal over all its kindports and then spreads the BR signal upwards in the direction of the root node. A potential problem with this mechanism is that a child node has difficulty obtaining can have reasonable bus access if the parent node a huge amount has to transfer information to the bus. It was because of that a gap system introduced, which is widely used and well known in the field. After this a node has used the bus, the node must have a gap period wait before he can request the bus again. This gives everyone Nodes on the bus have the same opportunity for a bus grant, regardless of his topological arrangement on the bus. To ensure a fair arbitration protocol, the length of the gap must be greater than the worst Signal propagation delay over the Be a bus. The gap value can be previously set and hardwired in the node logic. A such solution is a suboptimal use of the. with the exception of the most extreme case Buses lead. The ability to the topology image together with the during the phase of the graph transformation executed Measurement of the propagation delay between adjacent nodes the calculation of an optimal, fair gap, the performance of the bus for each specific execution will maximize.

Prioritätsbusarbitrierung

In according to the above fair bus access arbitration engineered bus arbitration scheme may be desirable be that the root node always has the bus priority. When this is done, The root node can grant itself the bus at any time. This is by sending the BD signal down over all nodes of the graph are executed. A priority bus access for the Root node is for the case very useful the execution an isochronous data transmission of the root node is required.

A token forwarding bus arbitration

As an alternative to the fair and priority bus access arbitration schemes described above, the present invention may be used to execute a token passing bus arbitration scheme. Figuratively speaking, token passing bus access refers to the notion that a node on a bus can communicate when in possession of a token passed between the nodes. The token is forwarded from node to node in a cyclic fashion such that each node receives the bus at a predetermined time in the cycle. The forwarding of the token is carried out in the present invention in the same manner as the above-described physical address assignment routine. The implemented predefined selection mechanisms are used to select the order in which the token is forwarded from node to node. This order is similar to the one in 5 shown order, which dictates the order of assignment of a unique address. Everyone Node will propagate its information packet on the bus upon assignment of the token, while listening to the remaining nodes. Based on the previously defined scheduling method, the node will then forward the token to the next logical node.

preemptive bus initialization

One important, according to the present Invention executable Feature is the concept of preemptive bus initialization. The In each node contained machine logic is able to under certain conditions to be propagated from the node across all its ports Bus initialization (BI) signal to trigger. If a node the need for signaling a Businitialisierungsbedingung has determined, it will be the BI signal over all its ports for spread a period of time that sufficiently ensures that it all adjacent nodes have received and then released. One Node will then enter the initiating procedures, which will then to the graph transformation process in the above-described Lead procedures.

It There are a number of situations that trigger a preemptive Businitialisierung necessary or desirable. This can first a reaction of a node to an unforeseen mistake. additionally can be determined at the level of the host that another node to get the node attribute, for example, a node with isochronous Data transfer. This assignment will be during complied with the entire Businitialisierungsroutine. This will be the desired Node causes, during of the transformation process wait until he gets the root name receives. Another condition that leads to a preemptive bus initialization may be be the break of a connection. In this case, the calculation a new acyclic, directed graph for the connected nodes to be necessary. After all is a significant situation in which a preemptive bus initialization should occur when a device is added to the network. This is called "Hot Addition "[" Add in the current Operation "] of peripheral devices. The port to which the new device is connected becomes the Detect the presence of a new node and trigger a bus initialization, the for the system users are transparent, but for example adding and Removing peripherals without shutting down and Re-activation allowed. It becomes a new acyclic directed Graph calculates the presence of the added node includes. It is possible, that when removing certain nodes, triggering a bus initialization does not is necessary, for example, if a leaf node is removed, there is no damage for the network. However, if a branch node from an in-service Bus removed the need to reconfigure the graph is likely.

Even though the present invention based on preferred embodiments it should be clear that various modifications and changes can be made by professionals without the scope of protection to leave the invention. The invention should therefore be to the following claims be measured.

Claims (10)

A method for fair bus access arbitration in a computer system having a plurality of components interconnected by a plurality of communication links, the plurality of components each including at least a first communication node, the communication nodes providing an interface between their associated component and a communication link form a node port, where the nodes may have multiple ports, the configuration of nodes and communication links forming a directed acyclic graph, where one node is called a root node, all nodes coupled to only one neighboring node are called leaf nodes, and all In the acyclic directed graph, parent-child hierarchical relationships between all adjacent nodes starting at the root node down to d a leaf node having only one parent node and wherein all nodes adjacent to the root node are child nodes with respect to the root node, but are parent nodes with respect to other neighboring nodes, the root node being defined as one having a parent node, wherein a bus request signal is transmitted from a requesting node to its parent node, the requesting node having an information packet to be spread over the bus, all nodes receiving the bus request signal forwarding the bus request signal to their respective parent node, the method being fair Bus access arbitration is characterized by the steps of: upon receipt of a bus request signal from an adjacent node, the root node responding to the neighboring node with a bus grant signal; that all the bus grant signal from a parent node then receiving the bus forward the grant signal to the child node which has previously forwarded the bus request signal unless the node is the requesting node and that upon receiving the bus grant signal, the requesting node issues the information packet onto the bus, the requesting node having issued the information packet; waits for a gap period before requesting access to the bus again, the gap period being greater than a worst case signal propagation delay across the bus. The method of claim 1, further comprising Step that forward the step of sending the request signal to the bus, a bus denied signal sent from the requesting node to each of its child nodes becomes. The method of claim 2, further comprising Step of forwarding a bus denied signal from all forwarding nodes to all Child nodes that were not the source of the bus request signal. The method of claim 3, further comprising after the step of answering the root node to an adjacent one Node with a bus grant signal the step that the root node a bus denied signal to all others sends out neighboring nodes. The method of claim 4, further comprising Step, that all Nodes receiving the bus denied signal receive this bus denied signal to all send out adjacent child nodes. The method of claim 5, further comprising before the step of sending out the information packet by the requesting one Knot, the step that the requesting node acknowledges receipt of the bus grant signal. The method of claim 6, further comprising Step, that all Nodes that receive a bus grant acknowledgment, this confirmation forward to a parent node. The method of claim 1, further comprising Step that the Root node then, if he determines that he has access to the Bus needed, one Bus denied signal to all sends out neighboring nodes and grants itself the bus. The method of claim 7, further comprising Step that the Root node, if he finds that he has access to the Bus needed, a bus denied signal to all sends out neighboring nodes and grants itself the bus. The method of claim 1, wherein the root node conflicting simultaneous requirements of the Bus triggers, by placing the bus on the basis of a predetermined selection criterion adjacent node.